mirror of
https://github.com/fhgwright/SCSI2SD.git
synced 2024-06-02 06:41:36 +00:00
1634 lines
73 KiB
C
1634 lines
73 KiB
C
/*******************************************************************************
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* File Name: cyfitter.h
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*
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* PSoC Creator 4.4
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*
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* Description:
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*
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* This file is automatically generated by PSoC Creator.
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*
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********************************************************************************
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* Copyright (c) 2007-2020 Cypress Semiconductor. All rights reserved.
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* You may use this file only in accordance with the license, terms, conditions,
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* disclaimers, and limitations in the end user license agreement accompanying
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* the software package with which this file was provided.
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********************************************************************************/
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#ifndef INCLUDED_CYFITTER_H
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#define INCLUDED_CYFITTER_H
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#include "cydevice.h"
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#include "cydevice_trm.h"
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/* LED */
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#define LED__0__INTTYPE CYREG_PICU12_INTTYPE2
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#define LED__0__MASK 0x04u
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#define LED__0__PC CYREG_PRT12_PC2
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#define LED__0__PORT 12u
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#define LED__0__SHIFT 2u
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#define LED__1__INTTYPE CYREG_PICU12_INTTYPE3
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#define LED__1__MASK 0x08u
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#define LED__1__PC CYREG_PRT12_PC3
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#define LED__1__PORT 12u
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#define LED__1__SHIFT 3u
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#define LED__AG CYREG_PRT12_AG
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#define LED__BIE CYREG_PRT12_BIE
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#define LED__BIT_MASK CYREG_PRT12_BIT_MASK
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#define LED__BYP CYREG_PRT12_BYP
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#define LED__DM0 CYREG_PRT12_DM0
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#define LED__DM1 CYREG_PRT12_DM1
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#define LED__DM2 CYREG_PRT12_DM2
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#define LED__DR CYREG_PRT12_DR
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#define LED__INP_DIS CYREG_PRT12_INP_DIS
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#define LED__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU12_BASE
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#define LED__MASK 0x0Cu
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#define LED__PORT 12u
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#define LED__PRT CYREG_PRT12_PRT
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#define LED__PRTDSI__DBL_SYNC_IN CYREG_PRT12_DBL_SYNC_IN
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#define LED__PRTDSI__OE_SEL0 CYREG_PRT12_OE_SEL0
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#define LED__PRTDSI__OE_SEL1 CYREG_PRT12_OE_SEL1
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#define LED__PRTDSI__OUT_SEL0 CYREG_PRT12_OUT_SEL0
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#define LED__PRTDSI__OUT_SEL1 CYREG_PRT12_OUT_SEL1
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#define LED__PRTDSI__SYNC_OUT CYREG_PRT12_SYNC_OUT
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#define LED__PS CYREG_PRT12_PS
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#define LED__SHIFT 2u
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#define LED__SIO_CFG CYREG_PRT12_SIO_CFG
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#define LED__SIO_DIFF CYREG_PRT12_SIO_DIFF
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#define LED__SIO_HYST_EN CYREG_PRT12_SIO_HYST_EN
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#define LED__SIO_REG_HIFREQ CYREG_PRT12_SIO_REG_HIFREQ
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#define LED__SLW CYREG_PRT12_SLW
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/* USBFS */
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#define USBFS_arb_int__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
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#define USBFS_arb_int__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
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#define USBFS_arb_int__INTC_MASK 0x400000u
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#define USBFS_arb_int__INTC_NUMBER 22u
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#define USBFS_arb_int__INTC_PRIOR_NUM 7u
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#define USBFS_arb_int__INTC_PRIOR_REG CYREG_NVIC_PRI_22
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#define USBFS_arb_int__INTC_SET_EN_REG CYREG_NVIC_SETENA0
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#define USBFS_arb_int__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
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#define USBFS_bus_reset__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
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#define USBFS_bus_reset__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
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#define USBFS_bus_reset__INTC_MASK 0x800000u
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#define USBFS_bus_reset__INTC_NUMBER 23u
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#define USBFS_bus_reset__INTC_PRIOR_NUM 7u
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#define USBFS_bus_reset__INTC_PRIOR_REG CYREG_NVIC_PRI_23
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#define USBFS_bus_reset__INTC_SET_EN_REG CYREG_NVIC_SETENA0
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#define USBFS_bus_reset__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
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#define USBFS_Dm__0__INTTYPE CYREG_PICU15_INTTYPE7
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#define USBFS_Dm__0__MASK 0x80u
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#define USBFS_Dm__0__PC CYREG_IO_PC_PRT15_7_6_PC1
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#define USBFS_Dm__0__PORT 15u
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#define USBFS_Dm__0__SHIFT 7u
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#define USBFS_Dm__AG CYREG_PRT15_AG
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#define USBFS_Dm__AMUX CYREG_PRT15_AMUX
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#define USBFS_Dm__BIE CYREG_PRT15_BIE
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#define USBFS_Dm__BIT_MASK CYREG_PRT15_BIT_MASK
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#define USBFS_Dm__BYP CYREG_PRT15_BYP
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#define USBFS_Dm__CTL CYREG_PRT15_CTL
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#define USBFS_Dm__DM0 CYREG_PRT15_DM0
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#define USBFS_Dm__DM1 CYREG_PRT15_DM1
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#define USBFS_Dm__DM2 CYREG_PRT15_DM2
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#define USBFS_Dm__DR CYREG_PRT15_DR
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#define USBFS_Dm__INP_DIS CYREG_PRT15_INP_DIS
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#define USBFS_Dm__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU15_BASE
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#define USBFS_Dm__LCD_COM_SEG CYREG_PRT15_LCD_COM_SEG
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#define USBFS_Dm__LCD_EN CYREG_PRT15_LCD_EN
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#define USBFS_Dm__MASK 0x80u
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#define USBFS_Dm__PORT 15u
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#define USBFS_Dm__PRT CYREG_PRT15_PRT
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#define USBFS_Dm__PRTDSI__CAPS_SEL CYREG_PRT15_CAPS_SEL
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#define USBFS_Dm__PRTDSI__DBL_SYNC_IN CYREG_PRT15_DBL_SYNC_IN
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#define USBFS_Dm__PRTDSI__OE_SEL0 CYREG_PRT15_OE_SEL0
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#define USBFS_Dm__PRTDSI__OE_SEL1 CYREG_PRT15_OE_SEL1
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#define USBFS_Dm__PRTDSI__OUT_SEL0 CYREG_PRT15_OUT_SEL0
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#define USBFS_Dm__PRTDSI__OUT_SEL1 CYREG_PRT15_OUT_SEL1
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#define USBFS_Dm__PRTDSI__SYNC_OUT CYREG_PRT15_SYNC_OUT
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#define USBFS_Dm__PS CYREG_PRT15_PS
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#define USBFS_Dm__SHIFT 7u
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#define USBFS_Dm__SLW CYREG_PRT15_SLW
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#define USBFS_Dp__0__INTTYPE CYREG_PICU15_INTTYPE6
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#define USBFS_Dp__0__MASK 0x40u
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#define USBFS_Dp__0__PC CYREG_IO_PC_PRT15_7_6_PC0
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#define USBFS_Dp__0__PORT 15u
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#define USBFS_Dp__0__SHIFT 6u
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#define USBFS_Dp__AG CYREG_PRT15_AG
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#define USBFS_Dp__AMUX CYREG_PRT15_AMUX
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#define USBFS_Dp__BIE CYREG_PRT15_BIE
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#define USBFS_Dp__BIT_MASK CYREG_PRT15_BIT_MASK
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#define USBFS_Dp__BYP CYREG_PRT15_BYP
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#define USBFS_Dp__CTL CYREG_PRT15_CTL
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#define USBFS_Dp__DM0 CYREG_PRT15_DM0
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#define USBFS_Dp__DM1 CYREG_PRT15_DM1
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#define USBFS_Dp__DM2 CYREG_PRT15_DM2
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#define USBFS_Dp__DR CYREG_PRT15_DR
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#define USBFS_Dp__INP_DIS CYREG_PRT15_INP_DIS
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#define USBFS_Dp__INTSTAT CYREG_PICU15_INTSTAT
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#define USBFS_Dp__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU15_BASE
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#define USBFS_Dp__LCD_COM_SEG CYREG_PRT15_LCD_COM_SEG
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#define USBFS_Dp__LCD_EN CYREG_PRT15_LCD_EN
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#define USBFS_Dp__MASK 0x40u
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#define USBFS_Dp__PORT 15u
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#define USBFS_Dp__PRT CYREG_PRT15_PRT
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#define USBFS_Dp__PRTDSI__CAPS_SEL CYREG_PRT15_CAPS_SEL
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#define USBFS_Dp__PRTDSI__DBL_SYNC_IN CYREG_PRT15_DBL_SYNC_IN
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#define USBFS_Dp__PRTDSI__OE_SEL0 CYREG_PRT15_OE_SEL0
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#define USBFS_Dp__PRTDSI__OE_SEL1 CYREG_PRT15_OE_SEL1
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#define USBFS_Dp__PRTDSI__OUT_SEL0 CYREG_PRT15_OUT_SEL0
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#define USBFS_Dp__PRTDSI__OUT_SEL1 CYREG_PRT15_OUT_SEL1
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#define USBFS_Dp__PRTDSI__SYNC_OUT CYREG_PRT15_SYNC_OUT
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#define USBFS_Dp__PS CYREG_PRT15_PS
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#define USBFS_Dp__SHIFT 6u
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#define USBFS_Dp__SLW CYREG_PRT15_SLW
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#define USBFS_Dp__SNAP CYREG_PICU_15_SNAP_15
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#define USBFS_dp_int__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
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#define USBFS_dp_int__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
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#define USBFS_dp_int__INTC_MASK 0x1000u
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#define USBFS_dp_int__INTC_NUMBER 12u
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#define USBFS_dp_int__INTC_PRIOR_NUM 7u
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#define USBFS_dp_int__INTC_PRIOR_REG CYREG_NVIC_PRI_12
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#define USBFS_dp_int__INTC_SET_EN_REG CYREG_NVIC_SETENA0
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#define USBFS_dp_int__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
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#define USBFS_ep_0__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
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#define USBFS_ep_0__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
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#define USBFS_ep_0__INTC_MASK 0x1000000u
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#define USBFS_ep_0__INTC_NUMBER 24u
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#define USBFS_ep_0__INTC_PRIOR_NUM 7u
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#define USBFS_ep_0__INTC_PRIOR_REG CYREG_NVIC_PRI_24
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#define USBFS_ep_0__INTC_SET_EN_REG CYREG_NVIC_SETENA0
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#define USBFS_ep_0__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
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#define USBFS_ep_1__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
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#define USBFS_ep_1__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
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#define USBFS_ep_1__INTC_MASK 0x01u
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#define USBFS_ep_1__INTC_NUMBER 0u
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#define USBFS_ep_1__INTC_PRIOR_NUM 7u
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#define USBFS_ep_1__INTC_PRIOR_REG CYREG_NVIC_PRI_0
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#define USBFS_ep_1__INTC_SET_EN_REG CYREG_NVIC_SETENA0
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#define USBFS_ep_1__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
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#define USBFS_ep_2__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
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#define USBFS_ep_2__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
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#define USBFS_ep_2__INTC_MASK 0x02u
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#define USBFS_ep_2__INTC_NUMBER 1u
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#define USBFS_ep_2__INTC_PRIOR_NUM 7u
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#define USBFS_ep_2__INTC_PRIOR_REG CYREG_NVIC_PRI_1
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#define USBFS_ep_2__INTC_SET_EN_REG CYREG_NVIC_SETENA0
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#define USBFS_ep_2__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
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#define USBFS_sof_int__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
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#define USBFS_sof_int__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
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#define USBFS_sof_int__INTC_MASK 0x200000u
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#define USBFS_sof_int__INTC_NUMBER 21u
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#define USBFS_sof_int__INTC_PRIOR_NUM 7u
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#define USBFS_sof_int__INTC_PRIOR_REG CYREG_NVIC_PRI_21
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#define USBFS_sof_int__INTC_SET_EN_REG CYREG_NVIC_SETENA0
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#define USBFS_sof_int__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
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#define USBFS_USB__ARB_CFG CYREG_USB_ARB_CFG
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#define USBFS_USB__ARB_EP1_CFG CYREG_USB_ARB_EP1_CFG
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#define USBFS_USB__ARB_EP1_INT_EN CYREG_USB_ARB_EP1_INT_EN
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#define USBFS_USB__ARB_EP1_SR CYREG_USB_ARB_EP1_SR
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#define USBFS_USB__ARB_EP2_CFG CYREG_USB_ARB_EP2_CFG
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#define USBFS_USB__ARB_EP2_INT_EN CYREG_USB_ARB_EP2_INT_EN
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#define USBFS_USB__ARB_EP2_SR CYREG_USB_ARB_EP2_SR
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#define USBFS_USB__ARB_EP3_CFG CYREG_USB_ARB_EP3_CFG
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#define USBFS_USB__ARB_EP3_INT_EN CYREG_USB_ARB_EP3_INT_EN
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#define USBFS_USB__ARB_EP3_SR CYREG_USB_ARB_EP3_SR
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#define USBFS_USB__ARB_EP4_CFG CYREG_USB_ARB_EP4_CFG
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#define USBFS_USB__ARB_EP4_INT_EN CYREG_USB_ARB_EP4_INT_EN
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#define USBFS_USB__ARB_EP4_SR CYREG_USB_ARB_EP4_SR
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#define USBFS_USB__ARB_EP5_CFG CYREG_USB_ARB_EP5_CFG
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#define USBFS_USB__ARB_EP5_INT_EN CYREG_USB_ARB_EP5_INT_EN
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#define USBFS_USB__ARB_EP5_SR CYREG_USB_ARB_EP5_SR
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#define USBFS_USB__ARB_EP6_CFG CYREG_USB_ARB_EP6_CFG
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#define USBFS_USB__ARB_EP6_INT_EN CYREG_USB_ARB_EP6_INT_EN
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#define USBFS_USB__ARB_EP6_SR CYREG_USB_ARB_EP6_SR
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#define USBFS_USB__ARB_EP7_CFG CYREG_USB_ARB_EP7_CFG
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#define USBFS_USB__ARB_EP7_INT_EN CYREG_USB_ARB_EP7_INT_EN
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#define USBFS_USB__ARB_EP7_SR CYREG_USB_ARB_EP7_SR
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#define USBFS_USB__ARB_EP8_CFG CYREG_USB_ARB_EP8_CFG
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#define USBFS_USB__ARB_EP8_INT_EN CYREG_USB_ARB_EP8_INT_EN
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#define USBFS_USB__ARB_EP8_SR CYREG_USB_ARB_EP8_SR
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#define USBFS_USB__ARB_INT_EN CYREG_USB_ARB_INT_EN
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#define USBFS_USB__ARB_INT_SR CYREG_USB_ARB_INT_SR
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#define USBFS_USB__ARB_RW1_DR CYREG_USB_ARB_RW1_DR
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#define USBFS_USB__ARB_RW1_RA CYREG_USB_ARB_RW1_RA
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#define USBFS_USB__ARB_RW1_RA_MSB CYREG_USB_ARB_RW1_RA_MSB
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#define USBFS_USB__ARB_RW1_WA CYREG_USB_ARB_RW1_WA
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#define USBFS_USB__ARB_RW1_WA_MSB CYREG_USB_ARB_RW1_WA_MSB
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#define USBFS_USB__ARB_RW2_DR CYREG_USB_ARB_RW2_DR
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#define USBFS_USB__ARB_RW2_RA CYREG_USB_ARB_RW2_RA
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#define USBFS_USB__ARB_RW2_RA_MSB CYREG_USB_ARB_RW2_RA_MSB
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#define USBFS_USB__ARB_RW2_WA CYREG_USB_ARB_RW2_WA
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#define USBFS_USB__ARB_RW2_WA_MSB CYREG_USB_ARB_RW2_WA_MSB
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#define USBFS_USB__ARB_RW3_DR CYREG_USB_ARB_RW3_DR
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#define USBFS_USB__ARB_RW3_RA CYREG_USB_ARB_RW3_RA
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#define USBFS_USB__ARB_RW3_RA_MSB CYREG_USB_ARB_RW3_RA_MSB
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#define USBFS_USB__ARB_RW3_WA CYREG_USB_ARB_RW3_WA
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#define USBFS_USB__ARB_RW3_WA_MSB CYREG_USB_ARB_RW3_WA_MSB
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#define USBFS_USB__ARB_RW4_DR CYREG_USB_ARB_RW4_DR
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#define USBFS_USB__ARB_RW4_RA CYREG_USB_ARB_RW4_RA
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#define USBFS_USB__ARB_RW4_RA_MSB CYREG_USB_ARB_RW4_RA_MSB
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#define USBFS_USB__ARB_RW4_WA CYREG_USB_ARB_RW4_WA
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#define USBFS_USB__ARB_RW4_WA_MSB CYREG_USB_ARB_RW4_WA_MSB
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#define USBFS_USB__ARB_RW5_DR CYREG_USB_ARB_RW5_DR
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#define USBFS_USB__ARB_RW5_RA CYREG_USB_ARB_RW5_RA
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#define USBFS_USB__ARB_RW5_RA_MSB CYREG_USB_ARB_RW5_RA_MSB
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#define USBFS_USB__ARB_RW5_WA CYREG_USB_ARB_RW5_WA
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#define USBFS_USB__ARB_RW5_WA_MSB CYREG_USB_ARB_RW5_WA_MSB
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#define USBFS_USB__ARB_RW6_DR CYREG_USB_ARB_RW6_DR
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#define USBFS_USB__ARB_RW6_RA CYREG_USB_ARB_RW6_RA
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#define USBFS_USB__ARB_RW6_RA_MSB CYREG_USB_ARB_RW6_RA_MSB
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#define USBFS_USB__ARB_RW6_WA CYREG_USB_ARB_RW6_WA
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#define USBFS_USB__ARB_RW6_WA_MSB CYREG_USB_ARB_RW6_WA_MSB
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#define USBFS_USB__ARB_RW7_DR CYREG_USB_ARB_RW7_DR
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#define USBFS_USB__ARB_RW7_RA CYREG_USB_ARB_RW7_RA
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#define USBFS_USB__ARB_RW7_RA_MSB CYREG_USB_ARB_RW7_RA_MSB
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#define USBFS_USB__ARB_RW7_WA CYREG_USB_ARB_RW7_WA
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#define USBFS_USB__ARB_RW7_WA_MSB CYREG_USB_ARB_RW7_WA_MSB
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#define USBFS_USB__ARB_RW8_DR CYREG_USB_ARB_RW8_DR
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#define USBFS_USB__ARB_RW8_RA CYREG_USB_ARB_RW8_RA
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#define USBFS_USB__ARB_RW8_RA_MSB CYREG_USB_ARB_RW8_RA_MSB
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#define USBFS_USB__ARB_RW8_WA CYREG_USB_ARB_RW8_WA
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#define USBFS_USB__ARB_RW8_WA_MSB CYREG_USB_ARB_RW8_WA_MSB
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#define USBFS_USB__BUF_SIZE CYREG_USB_BUF_SIZE
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#define USBFS_USB__BUS_RST_CNT CYREG_USB_BUS_RST_CNT
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#define USBFS_USB__CR0 CYREG_USB_CR0
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#define USBFS_USB__CR1 CYREG_USB_CR1
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#define USBFS_USB__CWA CYREG_USB_CWA
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#define USBFS_USB__CWA_MSB CYREG_USB_CWA_MSB
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#define USBFS_USB__DMA_THRES CYREG_USB_DMA_THRES
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#define USBFS_USB__DMA_THRES_MSB CYREG_USB_DMA_THRES_MSB
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#define USBFS_USB__DYN_RECONFIG CYREG_USB_DYN_RECONFIG
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#define USBFS_USB__EP_ACTIVE CYREG_USB_EP_ACTIVE
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#define USBFS_USB__EP_TYPE CYREG_USB_EP_TYPE
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#define USBFS_USB__EP0_CNT CYREG_USB_EP0_CNT
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#define USBFS_USB__EP0_CR CYREG_USB_EP0_CR
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#define USBFS_USB__EP0_DR0 CYREG_USB_EP0_DR0
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#define USBFS_USB__EP0_DR1 CYREG_USB_EP0_DR1
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#define USBFS_USB__EP0_DR2 CYREG_USB_EP0_DR2
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#define USBFS_USB__EP0_DR3 CYREG_USB_EP0_DR3
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#define USBFS_USB__EP0_DR4 CYREG_USB_EP0_DR4
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#define USBFS_USB__EP0_DR5 CYREG_USB_EP0_DR5
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#define USBFS_USB__EP0_DR6 CYREG_USB_EP0_DR6
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#define USBFS_USB__EP0_DR7 CYREG_USB_EP0_DR7
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#define USBFS_USB__MEM_DATA CYREG_USB_MEM_DATA_MBASE
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#define USBFS_USB__PM_ACT_CFG CYREG_PM_ACT_CFG5
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#define USBFS_USB__PM_ACT_MSK 0x01u
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#define USBFS_USB__PM_STBY_CFG CYREG_PM_STBY_CFG5
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#define USBFS_USB__PM_STBY_MSK 0x01u
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#define USBFS_USB__SIE_EP_INT_EN CYREG_USB_SIE_EP_INT_EN
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#define USBFS_USB__SIE_EP_INT_SR CYREG_USB_SIE_EP_INT_SR
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#define USBFS_USB__SIE_EP1_CNT0 CYREG_USB_SIE_EP1_CNT0
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#define USBFS_USB__SIE_EP1_CNT1 CYREG_USB_SIE_EP1_CNT1
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#define USBFS_USB__SIE_EP1_CR0 CYREG_USB_SIE_EP1_CR0
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#define USBFS_USB__SIE_EP2_CNT0 CYREG_USB_SIE_EP2_CNT0
|
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#define USBFS_USB__SIE_EP2_CNT1 CYREG_USB_SIE_EP2_CNT1
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#define USBFS_USB__SIE_EP2_CR0 CYREG_USB_SIE_EP2_CR0
|
|
#define USBFS_USB__SIE_EP3_CNT0 CYREG_USB_SIE_EP3_CNT0
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#define USBFS_USB__SIE_EP3_CNT1 CYREG_USB_SIE_EP3_CNT1
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#define USBFS_USB__SIE_EP3_CR0 CYREG_USB_SIE_EP3_CR0
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#define USBFS_USB__SIE_EP4_CNT0 CYREG_USB_SIE_EP4_CNT0
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#define USBFS_USB__SIE_EP4_CNT1 CYREG_USB_SIE_EP4_CNT1
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#define USBFS_USB__SIE_EP4_CR0 CYREG_USB_SIE_EP4_CR0
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#define USBFS_USB__SIE_EP5_CNT0 CYREG_USB_SIE_EP5_CNT0
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#define USBFS_USB__SIE_EP5_CNT1 CYREG_USB_SIE_EP5_CNT1
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#define USBFS_USB__SIE_EP5_CR0 CYREG_USB_SIE_EP5_CR0
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#define USBFS_USB__SIE_EP6_CNT0 CYREG_USB_SIE_EP6_CNT0
|
|
#define USBFS_USB__SIE_EP6_CNT1 CYREG_USB_SIE_EP6_CNT1
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#define USBFS_USB__SIE_EP6_CR0 CYREG_USB_SIE_EP6_CR0
|
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#define USBFS_USB__SIE_EP7_CNT0 CYREG_USB_SIE_EP7_CNT0
|
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#define USBFS_USB__SIE_EP7_CNT1 CYREG_USB_SIE_EP7_CNT1
|
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#define USBFS_USB__SIE_EP7_CR0 CYREG_USB_SIE_EP7_CR0
|
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#define USBFS_USB__SIE_EP8_CNT0 CYREG_USB_SIE_EP8_CNT0
|
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#define USBFS_USB__SIE_EP8_CNT1 CYREG_USB_SIE_EP8_CNT1
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#define USBFS_USB__SIE_EP8_CR0 CYREG_USB_SIE_EP8_CR0
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#define USBFS_USB__SOF0 CYREG_USB_SOF0
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#define USBFS_USB__SOF1 CYREG_USB_SOF1
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#define USBFS_USB__USB_CLK_EN CYREG_USB_USB_CLK_EN
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#define USBFS_USB__USBIO_CR0 CYREG_USB_USBIO_CR0
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#define USBFS_USB__USBIO_CR1 CYREG_USB_USBIO_CR1
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/* BOOTLDR */
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#define BOOTLDR__0__INTTYPE CYREG_PICU0_INTTYPE0
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#define BOOTLDR__0__MASK 0x01u
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#define BOOTLDR__0__PC CYREG_PRT0_PC0
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#define BOOTLDR__0__PORT 0u
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#define BOOTLDR__0__SHIFT 0u
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#define BOOTLDR__AG CYREG_PRT0_AG
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#define BOOTLDR__AMUX CYREG_PRT0_AMUX
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#define BOOTLDR__BIE CYREG_PRT0_BIE
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#define BOOTLDR__BIT_MASK CYREG_PRT0_BIT_MASK
|
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#define BOOTLDR__BYP CYREG_PRT0_BYP
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#define BOOTLDR__CTL CYREG_PRT0_CTL
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#define BOOTLDR__DM0 CYREG_PRT0_DM0
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#define BOOTLDR__DM1 CYREG_PRT0_DM1
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#define BOOTLDR__DM2 CYREG_PRT0_DM2
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#define BOOTLDR__DR CYREG_PRT0_DR
|
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#define BOOTLDR__INP_DIS CYREG_PRT0_INP_DIS
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#define BOOTLDR__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU0_BASE
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#define BOOTLDR__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG
|
|
#define BOOTLDR__LCD_EN CYREG_PRT0_LCD_EN
|
|
#define BOOTLDR__MASK 0x01u
|
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#define BOOTLDR__PORT 0u
|
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#define BOOTLDR__PRT CYREG_PRT0_PRT
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#define BOOTLDR__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL
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#define BOOTLDR__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN
|
|
#define BOOTLDR__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0
|
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#define BOOTLDR__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1
|
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#define BOOTLDR__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0
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#define BOOTLDR__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1
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#define BOOTLDR__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT
|
|
#define BOOTLDR__PS CYREG_PRT0_PS
|
|
#define BOOTLDR__SHIFT 0u
|
|
#define BOOTLDR__SLW CYREG_PRT0_SLW
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|
|
/* TERM_EN */
|
|
#define TERM_EN__0__INTTYPE CYREG_PICU15_INTTYPE3
|
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#define TERM_EN__0__MASK 0x08u
|
|
#define TERM_EN__0__PC CYREG_IO_PC_PRT15_PC3
|
|
#define TERM_EN__0__PORT 15u
|
|
#define TERM_EN__0__SHIFT 3u
|
|
#define TERM_EN__AG CYREG_PRT15_AG
|
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#define TERM_EN__AMUX CYREG_PRT15_AMUX
|
|
#define TERM_EN__BIE CYREG_PRT15_BIE
|
|
#define TERM_EN__BIT_MASK CYREG_PRT15_BIT_MASK
|
|
#define TERM_EN__BYP CYREG_PRT15_BYP
|
|
#define TERM_EN__CTL CYREG_PRT15_CTL
|
|
#define TERM_EN__DM0 CYREG_PRT15_DM0
|
|
#define TERM_EN__DM1 CYREG_PRT15_DM1
|
|
#define TERM_EN__DM2 CYREG_PRT15_DM2
|
|
#define TERM_EN__DR CYREG_PRT15_DR
|
|
#define TERM_EN__INP_DIS CYREG_PRT15_INP_DIS
|
|
#define TERM_EN__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU15_BASE
|
|
#define TERM_EN__LCD_COM_SEG CYREG_PRT15_LCD_COM_SEG
|
|
#define TERM_EN__LCD_EN CYREG_PRT15_LCD_EN
|
|
#define TERM_EN__MASK 0x08u
|
|
#define TERM_EN__PORT 15u
|
|
#define TERM_EN__PRT CYREG_PRT15_PRT
|
|
#define TERM_EN__PRTDSI__CAPS_SEL CYREG_PRT15_CAPS_SEL
|
|
#define TERM_EN__PRTDSI__DBL_SYNC_IN CYREG_PRT15_DBL_SYNC_IN
|
|
#define TERM_EN__PRTDSI__OE_SEL0 CYREG_PRT15_OE_SEL0
|
|
#define TERM_EN__PRTDSI__OE_SEL1 CYREG_PRT15_OE_SEL1
|
|
#define TERM_EN__PRTDSI__OUT_SEL0 CYREG_PRT15_OUT_SEL0
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|
#define TERM_EN__PRTDSI__OUT_SEL1 CYREG_PRT15_OUT_SEL1
|
|
#define TERM_EN__PRTDSI__SYNC_OUT CYREG_PRT15_SYNC_OUT
|
|
#define TERM_EN__PS CYREG_PRT15_PS
|
|
#define TERM_EN__SHIFT 3u
|
|
#define TERM_EN__SLW CYREG_PRT15_SLW
|
|
|
|
/* SCSI_Out */
|
|
#define SCSI_Out__0__AG CYREG_PRT6_AG
|
|
#define SCSI_Out__0__AMUX CYREG_PRT6_AMUX
|
|
#define SCSI_Out__0__BIE CYREG_PRT6_BIE
|
|
#define SCSI_Out__0__BIT_MASK CYREG_PRT6_BIT_MASK
|
|
#define SCSI_Out__0__BYP CYREG_PRT6_BYP
|
|
#define SCSI_Out__0__CTL CYREG_PRT6_CTL
|
|
#define SCSI_Out__0__DM0 CYREG_PRT6_DM0
|
|
#define SCSI_Out__0__DM1 CYREG_PRT6_DM1
|
|
#define SCSI_Out__0__DM2 CYREG_PRT6_DM2
|
|
#define SCSI_Out__0__DR CYREG_PRT6_DR
|
|
#define SCSI_Out__0__INP_DIS CYREG_PRT6_INP_DIS
|
|
#define SCSI_Out__0__INTTYPE CYREG_PICU6_INTTYPE2
|
|
#define SCSI_Out__0__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG
|
|
#define SCSI_Out__0__LCD_EN CYREG_PRT6_LCD_EN
|
|
#define SCSI_Out__0__MASK 0x04u
|
|
#define SCSI_Out__0__PC CYREG_PRT6_PC2
|
|
#define SCSI_Out__0__PORT 6u
|
|
#define SCSI_Out__0__PRT CYREG_PRT6_PRT
|
|
#define SCSI_Out__0__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL
|
|
#define SCSI_Out__0__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN
|
|
#define SCSI_Out__0__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0
|
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#define SCSI_Out__0__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1
|
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#define SCSI_Out__0__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0
|
|
#define SCSI_Out__0__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1
|
|
#define SCSI_Out__0__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT
|
|
#define SCSI_Out__0__PS CYREG_PRT6_PS
|
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#define SCSI_Out__0__SHIFT 2u
|
|
#define SCSI_Out__0__SLW CYREG_PRT6_SLW
|
|
#define SCSI_Out__1__AG CYREG_PRT4_AG
|
|
#define SCSI_Out__1__AMUX CYREG_PRT4_AMUX
|
|
#define SCSI_Out__1__BIE CYREG_PRT4_BIE
|
|
#define SCSI_Out__1__BIT_MASK CYREG_PRT4_BIT_MASK
|
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#define SCSI_Out__1__BYP CYREG_PRT4_BYP
|
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#define SCSI_Out__1__CTL CYREG_PRT4_CTL
|
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#define SCSI_Out__1__DM0 CYREG_PRT4_DM0
|
|
#define SCSI_Out__1__DM1 CYREG_PRT4_DM1
|
|
#define SCSI_Out__1__DM2 CYREG_PRT4_DM2
|
|
#define SCSI_Out__1__DR CYREG_PRT4_DR
|
|
#define SCSI_Out__1__INP_DIS CYREG_PRT4_INP_DIS
|
|
#define SCSI_Out__1__INTTYPE CYREG_PICU4_INTTYPE6
|
|
#define SCSI_Out__1__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG
|
|
#define SCSI_Out__1__LCD_EN CYREG_PRT4_LCD_EN
|
|
#define SCSI_Out__1__MASK 0x40u
|
|
#define SCSI_Out__1__PC CYREG_PRT4_PC6
|
|
#define SCSI_Out__1__PORT 4u
|
|
#define SCSI_Out__1__PRT CYREG_PRT4_PRT
|
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#define SCSI_Out__1__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL
|
|
#define SCSI_Out__1__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN
|
|
#define SCSI_Out__1__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0
|
|
#define SCSI_Out__1__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1
|
|
#define SCSI_Out__1__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0
|
|
#define SCSI_Out__1__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1
|
|
#define SCSI_Out__1__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT
|
|
#define SCSI_Out__1__PS CYREG_PRT4_PS
|
|
#define SCSI_Out__1__SHIFT 6u
|
|
#define SCSI_Out__1__SLW CYREG_PRT4_SLW
|
|
#define SCSI_Out__2__AG CYREG_PRT0_AG
|
|
#define SCSI_Out__2__AMUX CYREG_PRT0_AMUX
|
|
#define SCSI_Out__2__BIE CYREG_PRT0_BIE
|
|
#define SCSI_Out__2__BIT_MASK CYREG_PRT0_BIT_MASK
|
|
#define SCSI_Out__2__BYP CYREG_PRT0_BYP
|
|
#define SCSI_Out__2__CTL CYREG_PRT0_CTL
|
|
#define SCSI_Out__2__DM0 CYREG_PRT0_DM0
|
|
#define SCSI_Out__2__DM1 CYREG_PRT0_DM1
|
|
#define SCSI_Out__2__DM2 CYREG_PRT0_DM2
|
|
#define SCSI_Out__2__DR CYREG_PRT0_DR
|
|
#define SCSI_Out__2__INP_DIS CYREG_PRT0_INP_DIS
|
|
#define SCSI_Out__2__INTTYPE CYREG_PICU0_INTTYPE7
|
|
#define SCSI_Out__2__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG
|
|
#define SCSI_Out__2__LCD_EN CYREG_PRT0_LCD_EN
|
|
#define SCSI_Out__2__MASK 0x80u
|
|
#define SCSI_Out__2__PC CYREG_PRT0_PC7
|
|
#define SCSI_Out__2__PORT 0u
|
|
#define SCSI_Out__2__PRT CYREG_PRT0_PRT
|
|
#define SCSI_Out__2__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL
|
|
#define SCSI_Out__2__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN
|
|
#define SCSI_Out__2__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0
|
|
#define SCSI_Out__2__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1
|
|
#define SCSI_Out__2__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0
|
|
#define SCSI_Out__2__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1
|
|
#define SCSI_Out__2__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT
|
|
#define SCSI_Out__2__PS CYREG_PRT0_PS
|
|
#define SCSI_Out__2__SHIFT 7u
|
|
#define SCSI_Out__2__SLW CYREG_PRT0_SLW
|
|
#define SCSI_Out__3__AG CYREG_PRT0_AG
|
|
#define SCSI_Out__3__AMUX CYREG_PRT0_AMUX
|
|
#define SCSI_Out__3__BIE CYREG_PRT0_BIE
|
|
#define SCSI_Out__3__BIT_MASK CYREG_PRT0_BIT_MASK
|
|
#define SCSI_Out__3__BYP CYREG_PRT0_BYP
|
|
#define SCSI_Out__3__CTL CYREG_PRT0_CTL
|
|
#define SCSI_Out__3__DM0 CYREG_PRT0_DM0
|
|
#define SCSI_Out__3__DM1 CYREG_PRT0_DM1
|
|
#define SCSI_Out__3__DM2 CYREG_PRT0_DM2
|
|
#define SCSI_Out__3__DR CYREG_PRT0_DR
|
|
#define SCSI_Out__3__INP_DIS CYREG_PRT0_INP_DIS
|
|
#define SCSI_Out__3__INTTYPE CYREG_PICU0_INTTYPE5
|
|
#define SCSI_Out__3__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG
|
|
#define SCSI_Out__3__LCD_EN CYREG_PRT0_LCD_EN
|
|
#define SCSI_Out__3__MASK 0x20u
|
|
#define SCSI_Out__3__PC CYREG_PRT0_PC5
|
|
#define SCSI_Out__3__PORT 0u
|
|
#define SCSI_Out__3__PRT CYREG_PRT0_PRT
|
|
#define SCSI_Out__3__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL
|
|
#define SCSI_Out__3__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN
|
|
#define SCSI_Out__3__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0
|
|
#define SCSI_Out__3__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1
|
|
#define SCSI_Out__3__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0
|
|
#define SCSI_Out__3__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1
|
|
#define SCSI_Out__3__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT
|
|
#define SCSI_Out__3__PS CYREG_PRT0_PS
|
|
#define SCSI_Out__3__SHIFT 5u
|
|
#define SCSI_Out__3__SLW CYREG_PRT0_SLW
|
|
#define SCSI_Out__4__AG CYREG_PRT0_AG
|
|
#define SCSI_Out__4__AMUX CYREG_PRT0_AMUX
|
|
#define SCSI_Out__4__BIE CYREG_PRT0_BIE
|
|
#define SCSI_Out__4__BIT_MASK CYREG_PRT0_BIT_MASK
|
|
#define SCSI_Out__4__BYP CYREG_PRT0_BYP
|
|
#define SCSI_Out__4__CTL CYREG_PRT0_CTL
|
|
#define SCSI_Out__4__DM0 CYREG_PRT0_DM0
|
|
#define SCSI_Out__4__DM1 CYREG_PRT0_DM1
|
|
#define SCSI_Out__4__DM2 CYREG_PRT0_DM2
|
|
#define SCSI_Out__4__DR CYREG_PRT0_DR
|
|
#define SCSI_Out__4__INP_DIS CYREG_PRT0_INP_DIS
|
|
#define SCSI_Out__4__INTTYPE CYREG_PICU0_INTTYPE3
|
|
#define SCSI_Out__4__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG
|
|
#define SCSI_Out__4__LCD_EN CYREG_PRT0_LCD_EN
|
|
#define SCSI_Out__4__MASK 0x08u
|
|
#define SCSI_Out__4__PC CYREG_PRT0_PC3
|
|
#define SCSI_Out__4__PORT 0u
|
|
#define SCSI_Out__4__PRT CYREG_PRT0_PRT
|
|
#define SCSI_Out__4__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL
|
|
#define SCSI_Out__4__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN
|
|
#define SCSI_Out__4__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0
|
|
#define SCSI_Out__4__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1
|
|
#define SCSI_Out__4__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0
|
|
#define SCSI_Out__4__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1
|
|
#define SCSI_Out__4__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT
|
|
#define SCSI_Out__4__PS CYREG_PRT0_PS
|
|
#define SCSI_Out__4__SHIFT 3u
|
|
#define SCSI_Out__4__SLW CYREG_PRT0_SLW
|
|
#define SCSI_Out__5__AG CYREG_PRT0_AG
|
|
#define SCSI_Out__5__AMUX CYREG_PRT0_AMUX
|
|
#define SCSI_Out__5__BIE CYREG_PRT0_BIE
|
|
#define SCSI_Out__5__BIT_MASK CYREG_PRT0_BIT_MASK
|
|
#define SCSI_Out__5__BYP CYREG_PRT0_BYP
|
|
#define SCSI_Out__5__CTL CYREG_PRT0_CTL
|
|
#define SCSI_Out__5__DM0 CYREG_PRT0_DM0
|
|
#define SCSI_Out__5__DM1 CYREG_PRT0_DM1
|
|
#define SCSI_Out__5__DM2 CYREG_PRT0_DM2
|
|
#define SCSI_Out__5__DR CYREG_PRT0_DR
|
|
#define SCSI_Out__5__INP_DIS CYREG_PRT0_INP_DIS
|
|
#define SCSI_Out__5__INTTYPE CYREG_PICU0_INTTYPE1
|
|
#define SCSI_Out__5__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG
|
|
#define SCSI_Out__5__LCD_EN CYREG_PRT0_LCD_EN
|
|
#define SCSI_Out__5__MASK 0x02u
|
|
#define SCSI_Out__5__PC CYREG_PRT0_PC1
|
|
#define SCSI_Out__5__PORT 0u
|
|
#define SCSI_Out__5__PRT CYREG_PRT0_PRT
|
|
#define SCSI_Out__5__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL
|
|
#define SCSI_Out__5__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN
|
|
#define SCSI_Out__5__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0
|
|
#define SCSI_Out__5__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1
|
|
#define SCSI_Out__5__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0
|
|
#define SCSI_Out__5__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1
|
|
#define SCSI_Out__5__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT
|
|
#define SCSI_Out__5__PS CYREG_PRT0_PS
|
|
#define SCSI_Out__5__SHIFT 1u
|
|
#define SCSI_Out__5__SLW CYREG_PRT0_SLW
|
|
#define SCSI_Out__6__AG CYREG_PRT4_AG
|
|
#define SCSI_Out__6__AMUX CYREG_PRT4_AMUX
|
|
#define SCSI_Out__6__BIE CYREG_PRT4_BIE
|
|
#define SCSI_Out__6__BIT_MASK CYREG_PRT4_BIT_MASK
|
|
#define SCSI_Out__6__BYP CYREG_PRT4_BYP
|
|
#define SCSI_Out__6__CTL CYREG_PRT4_CTL
|
|
#define SCSI_Out__6__DM0 CYREG_PRT4_DM0
|
|
#define SCSI_Out__6__DM1 CYREG_PRT4_DM1
|
|
#define SCSI_Out__6__DM2 CYREG_PRT4_DM2
|
|
#define SCSI_Out__6__DR CYREG_PRT4_DR
|
|
#define SCSI_Out__6__INP_DIS CYREG_PRT4_INP_DIS
|
|
#define SCSI_Out__6__INTTYPE CYREG_PICU4_INTTYPE1
|
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#define SCSI_Out__6__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG
|
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#define SCSI_Out__6__LCD_EN CYREG_PRT4_LCD_EN
|
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#define SCSI_Out__6__MASK 0x02u
|
|
#define SCSI_Out__6__PC CYREG_PRT4_PC1
|
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#define SCSI_Out__6__PORT 4u
|
|
#define SCSI_Out__6__PRT CYREG_PRT4_PRT
|
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#define SCSI_Out__6__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL
|
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#define SCSI_Out__6__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN
|
|
#define SCSI_Out__6__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0
|
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#define SCSI_Out__6__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1
|
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#define SCSI_Out__6__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0
|
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#define SCSI_Out__6__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1
|
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#define SCSI_Out__6__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT
|
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#define SCSI_Out__6__PS CYREG_PRT4_PS
|
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#define SCSI_Out__6__SHIFT 1u
|
|
#define SCSI_Out__6__SLW CYREG_PRT4_SLW
|
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#define SCSI_Out__7__AG CYREG_PRT4_AG
|
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#define SCSI_Out__7__AMUX CYREG_PRT4_AMUX
|
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#define SCSI_Out__7__BIE CYREG_PRT4_BIE
|
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#define SCSI_Out__7__BIT_MASK CYREG_PRT4_BIT_MASK
|
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#define SCSI_Out__7__BYP CYREG_PRT4_BYP
|
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#define SCSI_Out__7__CTL CYREG_PRT4_CTL
|
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#define SCSI_Out__7__DM0 CYREG_PRT4_DM0
|
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#define SCSI_Out__7__DM1 CYREG_PRT4_DM1
|
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#define SCSI_Out__7__DM2 CYREG_PRT4_DM2
|
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#define SCSI_Out__7__DR CYREG_PRT4_DR
|
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#define SCSI_Out__7__INP_DIS CYREG_PRT4_INP_DIS
|
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#define SCSI_Out__7__INTTYPE CYREG_PICU4_INTTYPE0
|
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#define SCSI_Out__7__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG
|
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#define SCSI_Out__7__LCD_EN CYREG_PRT4_LCD_EN
|
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#define SCSI_Out__7__MASK 0x01u
|
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#define SCSI_Out__7__PC CYREG_PRT4_PC0
|
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#define SCSI_Out__7__PORT 4u
|
|
#define SCSI_Out__7__PRT CYREG_PRT4_PRT
|
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#define SCSI_Out__7__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL
|
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#define SCSI_Out__7__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN
|
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#define SCSI_Out__7__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0
|
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#define SCSI_Out__7__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1
|
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#define SCSI_Out__7__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0
|
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#define SCSI_Out__7__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1
|
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#define SCSI_Out__7__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT
|
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#define SCSI_Out__7__PS CYREG_PRT4_PS
|
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#define SCSI_Out__7__SHIFT 0u
|
|
#define SCSI_Out__7__SLW CYREG_PRT4_SLW
|
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#define SCSI_Out__BSY__AG CYREG_PRT4_AG
|
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#define SCSI_Out__BSY__AMUX CYREG_PRT4_AMUX
|
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#define SCSI_Out__BSY__BIE CYREG_PRT4_BIE
|
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#define SCSI_Out__BSY__BIT_MASK CYREG_PRT4_BIT_MASK
|
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#define SCSI_Out__BSY__BYP CYREG_PRT4_BYP
|
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#define SCSI_Out__BSY__CTL CYREG_PRT4_CTL
|
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#define SCSI_Out__BSY__DM0 CYREG_PRT4_DM0
|
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#define SCSI_Out__BSY__DM1 CYREG_PRT4_DM1
|
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#define SCSI_Out__BSY__DM2 CYREG_PRT4_DM2
|
|
#define SCSI_Out__BSY__DR CYREG_PRT4_DR
|
|
#define SCSI_Out__BSY__INP_DIS CYREG_PRT4_INP_DIS
|
|
#define SCSI_Out__BSY__INTTYPE CYREG_PICU4_INTTYPE6
|
|
#define SCSI_Out__BSY__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG
|
|
#define SCSI_Out__BSY__LCD_EN CYREG_PRT4_LCD_EN
|
|
#define SCSI_Out__BSY__MASK 0x40u
|
|
#define SCSI_Out__BSY__PC CYREG_PRT4_PC6
|
|
#define SCSI_Out__BSY__PORT 4u
|
|
#define SCSI_Out__BSY__PRT CYREG_PRT4_PRT
|
|
#define SCSI_Out__BSY__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL
|
|
#define SCSI_Out__BSY__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN
|
|
#define SCSI_Out__BSY__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0
|
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#define SCSI_Out__BSY__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1
|
|
#define SCSI_Out__BSY__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0
|
|
#define SCSI_Out__BSY__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1
|
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#define SCSI_Out__BSY__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT
|
|
#define SCSI_Out__BSY__PS CYREG_PRT4_PS
|
|
#define SCSI_Out__BSY__SHIFT 6u
|
|
#define SCSI_Out__BSY__SLW CYREG_PRT4_SLW
|
|
#define SCSI_Out__CD__AG CYREG_PRT0_AG
|
|
#define SCSI_Out__CD__AMUX CYREG_PRT0_AMUX
|
|
#define SCSI_Out__CD__BIE CYREG_PRT0_BIE
|
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#define SCSI_Out__CD__BIT_MASK CYREG_PRT0_BIT_MASK
|
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#define SCSI_Out__CD__BYP CYREG_PRT0_BYP
|
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#define SCSI_Out__CD__CTL CYREG_PRT0_CTL
|
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#define SCSI_Out__CD__DM0 CYREG_PRT0_DM0
|
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#define SCSI_Out__CD__DM1 CYREG_PRT0_DM1
|
|
#define SCSI_Out__CD__DM2 CYREG_PRT0_DM2
|
|
#define SCSI_Out__CD__DR CYREG_PRT0_DR
|
|
#define SCSI_Out__CD__INP_DIS CYREG_PRT0_INP_DIS
|
|
#define SCSI_Out__CD__INTTYPE CYREG_PICU0_INTTYPE1
|
|
#define SCSI_Out__CD__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG
|
|
#define SCSI_Out__CD__LCD_EN CYREG_PRT0_LCD_EN
|
|
#define SCSI_Out__CD__MASK 0x02u
|
|
#define SCSI_Out__CD__PC CYREG_PRT0_PC1
|
|
#define SCSI_Out__CD__PORT 0u
|
|
#define SCSI_Out__CD__PRT CYREG_PRT0_PRT
|
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#define SCSI_Out__CD__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL
|
|
#define SCSI_Out__CD__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN
|
|
#define SCSI_Out__CD__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0
|
|
#define SCSI_Out__CD__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1
|
|
#define SCSI_Out__CD__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0
|
|
#define SCSI_Out__CD__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1
|
|
#define SCSI_Out__CD__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT
|
|
#define SCSI_Out__CD__PS CYREG_PRT0_PS
|
|
#define SCSI_Out__CD__SHIFT 1u
|
|
#define SCSI_Out__CD__SLW CYREG_PRT0_SLW
|
|
#define SCSI_Out__DBP_raw__AG CYREG_PRT6_AG
|
|
#define SCSI_Out__DBP_raw__AMUX CYREG_PRT6_AMUX
|
|
#define SCSI_Out__DBP_raw__BIE CYREG_PRT6_BIE
|
|
#define SCSI_Out__DBP_raw__BIT_MASK CYREG_PRT6_BIT_MASK
|
|
#define SCSI_Out__DBP_raw__BYP CYREG_PRT6_BYP
|
|
#define SCSI_Out__DBP_raw__CTL CYREG_PRT6_CTL
|
|
#define SCSI_Out__DBP_raw__DM0 CYREG_PRT6_DM0
|
|
#define SCSI_Out__DBP_raw__DM1 CYREG_PRT6_DM1
|
|
#define SCSI_Out__DBP_raw__DM2 CYREG_PRT6_DM2
|
|
#define SCSI_Out__DBP_raw__DR CYREG_PRT6_DR
|
|
#define SCSI_Out__DBP_raw__INP_DIS CYREG_PRT6_INP_DIS
|
|
#define SCSI_Out__DBP_raw__INTTYPE CYREG_PICU6_INTTYPE2
|
|
#define SCSI_Out__DBP_raw__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG
|
|
#define SCSI_Out__DBP_raw__LCD_EN CYREG_PRT6_LCD_EN
|
|
#define SCSI_Out__DBP_raw__MASK 0x04u
|
|
#define SCSI_Out__DBP_raw__PC CYREG_PRT6_PC2
|
|
#define SCSI_Out__DBP_raw__PORT 6u
|
|
#define SCSI_Out__DBP_raw__PRT CYREG_PRT6_PRT
|
|
#define SCSI_Out__DBP_raw__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL
|
|
#define SCSI_Out__DBP_raw__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN
|
|
#define SCSI_Out__DBP_raw__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0
|
|
#define SCSI_Out__DBP_raw__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1
|
|
#define SCSI_Out__DBP_raw__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0
|
|
#define SCSI_Out__DBP_raw__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1
|
|
#define SCSI_Out__DBP_raw__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT
|
|
#define SCSI_Out__DBP_raw__PS CYREG_PRT6_PS
|
|
#define SCSI_Out__DBP_raw__SHIFT 2u
|
|
#define SCSI_Out__DBP_raw__SLW CYREG_PRT6_SLW
|
|
#define SCSI_Out__IO_raw__AG CYREG_PRT4_AG
|
|
#define SCSI_Out__IO_raw__AMUX CYREG_PRT4_AMUX
|
|
#define SCSI_Out__IO_raw__BIE CYREG_PRT4_BIE
|
|
#define SCSI_Out__IO_raw__BIT_MASK CYREG_PRT4_BIT_MASK
|
|
#define SCSI_Out__IO_raw__BYP CYREG_PRT4_BYP
|
|
#define SCSI_Out__IO_raw__CTL CYREG_PRT4_CTL
|
|
#define SCSI_Out__IO_raw__DM0 CYREG_PRT4_DM0
|
|
#define SCSI_Out__IO_raw__DM1 CYREG_PRT4_DM1
|
|
#define SCSI_Out__IO_raw__DM2 CYREG_PRT4_DM2
|
|
#define SCSI_Out__IO_raw__DR CYREG_PRT4_DR
|
|
#define SCSI_Out__IO_raw__INP_DIS CYREG_PRT4_INP_DIS
|
|
#define SCSI_Out__IO_raw__INTTYPE CYREG_PICU4_INTTYPE0
|
|
#define SCSI_Out__IO_raw__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG
|
|
#define SCSI_Out__IO_raw__LCD_EN CYREG_PRT4_LCD_EN
|
|
#define SCSI_Out__IO_raw__MASK 0x01u
|
|
#define SCSI_Out__IO_raw__PC CYREG_PRT4_PC0
|
|
#define SCSI_Out__IO_raw__PORT 4u
|
|
#define SCSI_Out__IO_raw__PRT CYREG_PRT4_PRT
|
|
#define SCSI_Out__IO_raw__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL
|
|
#define SCSI_Out__IO_raw__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN
|
|
#define SCSI_Out__IO_raw__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0
|
|
#define SCSI_Out__IO_raw__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1
|
|
#define SCSI_Out__IO_raw__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0
|
|
#define SCSI_Out__IO_raw__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1
|
|
#define SCSI_Out__IO_raw__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT
|
|
#define SCSI_Out__IO_raw__PS CYREG_PRT4_PS
|
|
#define SCSI_Out__IO_raw__SHIFT 0u
|
|
#define SCSI_Out__IO_raw__SLW CYREG_PRT4_SLW
|
|
#define SCSI_Out__MSG__AG CYREG_PRT0_AG
|
|
#define SCSI_Out__MSG__AMUX CYREG_PRT0_AMUX
|
|
#define SCSI_Out__MSG__BIE CYREG_PRT0_BIE
|
|
#define SCSI_Out__MSG__BIT_MASK CYREG_PRT0_BIT_MASK
|
|
#define SCSI_Out__MSG__BYP CYREG_PRT0_BYP
|
|
#define SCSI_Out__MSG__CTL CYREG_PRT0_CTL
|
|
#define SCSI_Out__MSG__DM0 CYREG_PRT0_DM0
|
|
#define SCSI_Out__MSG__DM1 CYREG_PRT0_DM1
|
|
#define SCSI_Out__MSG__DM2 CYREG_PRT0_DM2
|
|
#define SCSI_Out__MSG__DR CYREG_PRT0_DR
|
|
#define SCSI_Out__MSG__INP_DIS CYREG_PRT0_INP_DIS
|
|
#define SCSI_Out__MSG__INTTYPE CYREG_PICU0_INTTYPE5
|
|
#define SCSI_Out__MSG__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG
|
|
#define SCSI_Out__MSG__LCD_EN CYREG_PRT0_LCD_EN
|
|
#define SCSI_Out__MSG__MASK 0x20u
|
|
#define SCSI_Out__MSG__PC CYREG_PRT0_PC5
|
|
#define SCSI_Out__MSG__PORT 0u
|
|
#define SCSI_Out__MSG__PRT CYREG_PRT0_PRT
|
|
#define SCSI_Out__MSG__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL
|
|
#define SCSI_Out__MSG__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN
|
|
#define SCSI_Out__MSG__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0
|
|
#define SCSI_Out__MSG__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1
|
|
#define SCSI_Out__MSG__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0
|
|
#define SCSI_Out__MSG__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1
|
|
#define SCSI_Out__MSG__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT
|
|
#define SCSI_Out__MSG__PS CYREG_PRT0_PS
|
|
#define SCSI_Out__MSG__SHIFT 5u
|
|
#define SCSI_Out__MSG__SLW CYREG_PRT0_SLW
|
|
#define SCSI_Out__REQ__AG CYREG_PRT4_AG
|
|
#define SCSI_Out__REQ__AMUX CYREG_PRT4_AMUX
|
|
#define SCSI_Out__REQ__BIE CYREG_PRT4_BIE
|
|
#define SCSI_Out__REQ__BIT_MASK CYREG_PRT4_BIT_MASK
|
|
#define SCSI_Out__REQ__BYP CYREG_PRT4_BYP
|
|
#define SCSI_Out__REQ__CTL CYREG_PRT4_CTL
|
|
#define SCSI_Out__REQ__DM0 CYREG_PRT4_DM0
|
|
#define SCSI_Out__REQ__DM1 CYREG_PRT4_DM1
|
|
#define SCSI_Out__REQ__DM2 CYREG_PRT4_DM2
|
|
#define SCSI_Out__REQ__DR CYREG_PRT4_DR
|
|
#define SCSI_Out__REQ__INP_DIS CYREG_PRT4_INP_DIS
|
|
#define SCSI_Out__REQ__INTTYPE CYREG_PICU4_INTTYPE1
|
|
#define SCSI_Out__REQ__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG
|
|
#define SCSI_Out__REQ__LCD_EN CYREG_PRT4_LCD_EN
|
|
#define SCSI_Out__REQ__MASK 0x02u
|
|
#define SCSI_Out__REQ__PC CYREG_PRT4_PC1
|
|
#define SCSI_Out__REQ__PORT 4u
|
|
#define SCSI_Out__REQ__PRT CYREG_PRT4_PRT
|
|
#define SCSI_Out__REQ__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL
|
|
#define SCSI_Out__REQ__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN
|
|
#define SCSI_Out__REQ__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0
|
|
#define SCSI_Out__REQ__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1
|
|
#define SCSI_Out__REQ__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0
|
|
#define SCSI_Out__REQ__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1
|
|
#define SCSI_Out__REQ__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT
|
|
#define SCSI_Out__REQ__PS CYREG_PRT4_PS
|
|
#define SCSI_Out__REQ__SHIFT 1u
|
|
#define SCSI_Out__REQ__SLW CYREG_PRT4_SLW
|
|
#define SCSI_Out__RST__AG CYREG_PRT0_AG
|
|
#define SCSI_Out__RST__AMUX CYREG_PRT0_AMUX
|
|
#define SCSI_Out__RST__BIE CYREG_PRT0_BIE
|
|
#define SCSI_Out__RST__BIT_MASK CYREG_PRT0_BIT_MASK
|
|
#define SCSI_Out__RST__BYP CYREG_PRT0_BYP
|
|
#define SCSI_Out__RST__CTL CYREG_PRT0_CTL
|
|
#define SCSI_Out__RST__DM0 CYREG_PRT0_DM0
|
|
#define SCSI_Out__RST__DM1 CYREG_PRT0_DM1
|
|
#define SCSI_Out__RST__DM2 CYREG_PRT0_DM2
|
|
#define SCSI_Out__RST__DR CYREG_PRT0_DR
|
|
#define SCSI_Out__RST__INP_DIS CYREG_PRT0_INP_DIS
|
|
#define SCSI_Out__RST__INTTYPE CYREG_PICU0_INTTYPE7
|
|
#define SCSI_Out__RST__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG
|
|
#define SCSI_Out__RST__LCD_EN CYREG_PRT0_LCD_EN
|
|
#define SCSI_Out__RST__MASK 0x80u
|
|
#define SCSI_Out__RST__PC CYREG_PRT0_PC7
|
|
#define SCSI_Out__RST__PORT 0u
|
|
#define SCSI_Out__RST__PRT CYREG_PRT0_PRT
|
|
#define SCSI_Out__RST__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL
|
|
#define SCSI_Out__RST__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN
|
|
#define SCSI_Out__RST__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0
|
|
#define SCSI_Out__RST__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1
|
|
#define SCSI_Out__RST__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0
|
|
#define SCSI_Out__RST__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1
|
|
#define SCSI_Out__RST__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT
|
|
#define SCSI_Out__RST__PS CYREG_PRT0_PS
|
|
#define SCSI_Out__RST__SHIFT 7u
|
|
#define SCSI_Out__RST__SLW CYREG_PRT0_SLW
|
|
#define SCSI_Out__SEL__AG CYREG_PRT0_AG
|
|
#define SCSI_Out__SEL__AMUX CYREG_PRT0_AMUX
|
|
#define SCSI_Out__SEL__BIE CYREG_PRT0_BIE
|
|
#define SCSI_Out__SEL__BIT_MASK CYREG_PRT0_BIT_MASK
|
|
#define SCSI_Out__SEL__BYP CYREG_PRT0_BYP
|
|
#define SCSI_Out__SEL__CTL CYREG_PRT0_CTL
|
|
#define SCSI_Out__SEL__DM0 CYREG_PRT0_DM0
|
|
#define SCSI_Out__SEL__DM1 CYREG_PRT0_DM1
|
|
#define SCSI_Out__SEL__DM2 CYREG_PRT0_DM2
|
|
#define SCSI_Out__SEL__DR CYREG_PRT0_DR
|
|
#define SCSI_Out__SEL__INP_DIS CYREG_PRT0_INP_DIS
|
|
#define SCSI_Out__SEL__INTTYPE CYREG_PICU0_INTTYPE3
|
|
#define SCSI_Out__SEL__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG
|
|
#define SCSI_Out__SEL__LCD_EN CYREG_PRT0_LCD_EN
|
|
#define SCSI_Out__SEL__MASK 0x08u
|
|
#define SCSI_Out__SEL__PC CYREG_PRT0_PC3
|
|
#define SCSI_Out__SEL__PORT 0u
|
|
#define SCSI_Out__SEL__PRT CYREG_PRT0_PRT
|
|
#define SCSI_Out__SEL__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL
|
|
#define SCSI_Out__SEL__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN
|
|
#define SCSI_Out__SEL__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0
|
|
#define SCSI_Out__SEL__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1
|
|
#define SCSI_Out__SEL__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0
|
|
#define SCSI_Out__SEL__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1
|
|
#define SCSI_Out__SEL__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT
|
|
#define SCSI_Out__SEL__PS CYREG_PRT0_PS
|
|
#define SCSI_Out__SEL__SHIFT 3u
|
|
#define SCSI_Out__SEL__SLW CYREG_PRT0_SLW
|
|
#define SCSI_Out_DBx__0__AG CYREG_PRT6_AG
|
|
#define SCSI_Out_DBx__0__AMUX CYREG_PRT6_AMUX
|
|
#define SCSI_Out_DBx__0__BIE CYREG_PRT6_BIE
|
|
#define SCSI_Out_DBx__0__BIT_MASK CYREG_PRT6_BIT_MASK
|
|
#define SCSI_Out_DBx__0__BYP CYREG_PRT6_BYP
|
|
#define SCSI_Out_DBx__0__CTL CYREG_PRT6_CTL
|
|
#define SCSI_Out_DBx__0__DM0 CYREG_PRT6_DM0
|
|
#define SCSI_Out_DBx__0__DM1 CYREG_PRT6_DM1
|
|
#define SCSI_Out_DBx__0__DM2 CYREG_PRT6_DM2
|
|
#define SCSI_Out_DBx__0__DR CYREG_PRT6_DR
|
|
#define SCSI_Out_DBx__0__INP_DIS CYREG_PRT6_INP_DIS
|
|
#define SCSI_Out_DBx__0__INTTYPE CYREG_PICU6_INTTYPE7
|
|
#define SCSI_Out_DBx__0__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG
|
|
#define SCSI_Out_DBx__0__LCD_EN CYREG_PRT6_LCD_EN
|
|
#define SCSI_Out_DBx__0__MASK 0x80u
|
|
#define SCSI_Out_DBx__0__PC CYREG_PRT6_PC7
|
|
#define SCSI_Out_DBx__0__PORT 6u
|
|
#define SCSI_Out_DBx__0__PRT CYREG_PRT6_PRT
|
|
#define SCSI_Out_DBx__0__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL
|
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#define SCSI_Out_DBx__0__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN
|
|
#define SCSI_Out_DBx__0__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0
|
|
#define SCSI_Out_DBx__0__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1
|
|
#define SCSI_Out_DBx__0__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0
|
|
#define SCSI_Out_DBx__0__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1
|
|
#define SCSI_Out_DBx__0__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT
|
|
#define SCSI_Out_DBx__0__PS CYREG_PRT6_PS
|
|
#define SCSI_Out_DBx__0__SHIFT 7u
|
|
#define SCSI_Out_DBx__0__SLW CYREG_PRT6_SLW
|
|
#define SCSI_Out_DBx__1__AG CYREG_PRT6_AG
|
|
#define SCSI_Out_DBx__1__AMUX CYREG_PRT6_AMUX
|
|
#define SCSI_Out_DBx__1__BIE CYREG_PRT6_BIE
|
|
#define SCSI_Out_DBx__1__BIT_MASK CYREG_PRT6_BIT_MASK
|
|
#define SCSI_Out_DBx__1__BYP CYREG_PRT6_BYP
|
|
#define SCSI_Out_DBx__1__CTL CYREG_PRT6_CTL
|
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#define SCSI_Out_DBx__1__DM0 CYREG_PRT6_DM0
|
|
#define SCSI_Out_DBx__1__DM1 CYREG_PRT6_DM1
|
|
#define SCSI_Out_DBx__1__DM2 CYREG_PRT6_DM2
|
|
#define SCSI_Out_DBx__1__DR CYREG_PRT6_DR
|
|
#define SCSI_Out_DBx__1__INP_DIS CYREG_PRT6_INP_DIS
|
|
#define SCSI_Out_DBx__1__INTTYPE CYREG_PICU6_INTTYPE5
|
|
#define SCSI_Out_DBx__1__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG
|
|
#define SCSI_Out_DBx__1__LCD_EN CYREG_PRT6_LCD_EN
|
|
#define SCSI_Out_DBx__1__MASK 0x20u
|
|
#define SCSI_Out_DBx__1__PC CYREG_PRT6_PC5
|
|
#define SCSI_Out_DBx__1__PORT 6u
|
|
#define SCSI_Out_DBx__1__PRT CYREG_PRT6_PRT
|
|
#define SCSI_Out_DBx__1__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL
|
|
#define SCSI_Out_DBx__1__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN
|
|
#define SCSI_Out_DBx__1__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0
|
|
#define SCSI_Out_DBx__1__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1
|
|
#define SCSI_Out_DBx__1__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0
|
|
#define SCSI_Out_DBx__1__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1
|
|
#define SCSI_Out_DBx__1__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT
|
|
#define SCSI_Out_DBx__1__PS CYREG_PRT6_PS
|
|
#define SCSI_Out_DBx__1__SHIFT 5u
|
|
#define SCSI_Out_DBx__1__SLW CYREG_PRT6_SLW
|
|
#define SCSI_Out_DBx__2__AG CYREG_PRT12_AG
|
|
#define SCSI_Out_DBx__2__BIE CYREG_PRT12_BIE
|
|
#define SCSI_Out_DBx__2__BIT_MASK CYREG_PRT12_BIT_MASK
|
|
#define SCSI_Out_DBx__2__BYP CYREG_PRT12_BYP
|
|
#define SCSI_Out_DBx__2__DM0 CYREG_PRT12_DM0
|
|
#define SCSI_Out_DBx__2__DM1 CYREG_PRT12_DM1
|
|
#define SCSI_Out_DBx__2__DM2 CYREG_PRT12_DM2
|
|
#define SCSI_Out_DBx__2__DR CYREG_PRT12_DR
|
|
#define SCSI_Out_DBx__2__INP_DIS CYREG_PRT12_INP_DIS
|
|
#define SCSI_Out_DBx__2__INTTYPE CYREG_PICU12_INTTYPE5
|
|
#define SCSI_Out_DBx__2__MASK 0x20u
|
|
#define SCSI_Out_DBx__2__PC CYREG_PRT12_PC5
|
|
#define SCSI_Out_DBx__2__PORT 12u
|
|
#define SCSI_Out_DBx__2__PRT CYREG_PRT12_PRT
|
|
#define SCSI_Out_DBx__2__PRTDSI__DBL_SYNC_IN CYREG_PRT12_DBL_SYNC_IN
|
|
#define SCSI_Out_DBx__2__PRTDSI__OE_SEL0 CYREG_PRT12_OE_SEL0
|
|
#define SCSI_Out_DBx__2__PRTDSI__OE_SEL1 CYREG_PRT12_OE_SEL1
|
|
#define SCSI_Out_DBx__2__PRTDSI__OUT_SEL0 CYREG_PRT12_OUT_SEL0
|
|
#define SCSI_Out_DBx__2__PRTDSI__OUT_SEL1 CYREG_PRT12_OUT_SEL1
|
|
#define SCSI_Out_DBx__2__PRTDSI__SYNC_OUT CYREG_PRT12_SYNC_OUT
|
|
#define SCSI_Out_DBx__2__PS CYREG_PRT12_PS
|
|
#define SCSI_Out_DBx__2__SHIFT 5u
|
|
#define SCSI_Out_DBx__2__SIO_CFG CYREG_PRT12_SIO_CFG
|
|
#define SCSI_Out_DBx__2__SIO_DIFF CYREG_PRT12_SIO_DIFF
|
|
#define SCSI_Out_DBx__2__SIO_HYST_EN CYREG_PRT12_SIO_HYST_EN
|
|
#define SCSI_Out_DBx__2__SIO_REG_HIFREQ CYREG_PRT12_SIO_REG_HIFREQ
|
|
#define SCSI_Out_DBx__2__SLW CYREG_PRT12_SLW
|
|
#define SCSI_Out_DBx__3__AG CYREG_PRT2_AG
|
|
#define SCSI_Out_DBx__3__AMUX CYREG_PRT2_AMUX
|
|
#define SCSI_Out_DBx__3__BIE CYREG_PRT2_BIE
|
|
#define SCSI_Out_DBx__3__BIT_MASK CYREG_PRT2_BIT_MASK
|
|
#define SCSI_Out_DBx__3__BYP CYREG_PRT2_BYP
|
|
#define SCSI_Out_DBx__3__CTL CYREG_PRT2_CTL
|
|
#define SCSI_Out_DBx__3__DM0 CYREG_PRT2_DM0
|
|
#define SCSI_Out_DBx__3__DM1 CYREG_PRT2_DM1
|
|
#define SCSI_Out_DBx__3__DM2 CYREG_PRT2_DM2
|
|
#define SCSI_Out_DBx__3__DR CYREG_PRT2_DR
|
|
#define SCSI_Out_DBx__3__INP_DIS CYREG_PRT2_INP_DIS
|
|
#define SCSI_Out_DBx__3__INTTYPE CYREG_PICU2_INTTYPE7
|
|
#define SCSI_Out_DBx__3__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG
|
|
#define SCSI_Out_DBx__3__LCD_EN CYREG_PRT2_LCD_EN
|
|
#define SCSI_Out_DBx__3__MASK 0x80u
|
|
#define SCSI_Out_DBx__3__PC CYREG_PRT2_PC7
|
|
#define SCSI_Out_DBx__3__PORT 2u
|
|
#define SCSI_Out_DBx__3__PRT CYREG_PRT2_PRT
|
|
#define SCSI_Out_DBx__3__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL
|
|
#define SCSI_Out_DBx__3__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN
|
|
#define SCSI_Out_DBx__3__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0
|
|
#define SCSI_Out_DBx__3__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1
|
|
#define SCSI_Out_DBx__3__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0
|
|
#define SCSI_Out_DBx__3__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1
|
|
#define SCSI_Out_DBx__3__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT
|
|
#define SCSI_Out_DBx__3__PS CYREG_PRT2_PS
|
|
#define SCSI_Out_DBx__3__SHIFT 7u
|
|
#define SCSI_Out_DBx__3__SLW CYREG_PRT2_SLW
|
|
#define SCSI_Out_DBx__4__AG CYREG_PRT2_AG
|
|
#define SCSI_Out_DBx__4__AMUX CYREG_PRT2_AMUX
|
|
#define SCSI_Out_DBx__4__BIE CYREG_PRT2_BIE
|
|
#define SCSI_Out_DBx__4__BIT_MASK CYREG_PRT2_BIT_MASK
|
|
#define SCSI_Out_DBx__4__BYP CYREG_PRT2_BYP
|
|
#define SCSI_Out_DBx__4__CTL CYREG_PRT2_CTL
|
|
#define SCSI_Out_DBx__4__DM0 CYREG_PRT2_DM0
|
|
#define SCSI_Out_DBx__4__DM1 CYREG_PRT2_DM1
|
|
#define SCSI_Out_DBx__4__DM2 CYREG_PRT2_DM2
|
|
#define SCSI_Out_DBx__4__DR CYREG_PRT2_DR
|
|
#define SCSI_Out_DBx__4__INP_DIS CYREG_PRT2_INP_DIS
|
|
#define SCSI_Out_DBx__4__INTTYPE CYREG_PICU2_INTTYPE5
|
|
#define SCSI_Out_DBx__4__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG
|
|
#define SCSI_Out_DBx__4__LCD_EN CYREG_PRT2_LCD_EN
|
|
#define SCSI_Out_DBx__4__MASK 0x20u
|
|
#define SCSI_Out_DBx__4__PC CYREG_PRT2_PC5
|
|
#define SCSI_Out_DBx__4__PORT 2u
|
|
#define SCSI_Out_DBx__4__PRT CYREG_PRT2_PRT
|
|
#define SCSI_Out_DBx__4__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL
|
|
#define SCSI_Out_DBx__4__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN
|
|
#define SCSI_Out_DBx__4__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0
|
|
#define SCSI_Out_DBx__4__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1
|
|
#define SCSI_Out_DBx__4__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0
|
|
#define SCSI_Out_DBx__4__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1
|
|
#define SCSI_Out_DBx__4__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT
|
|
#define SCSI_Out_DBx__4__PS CYREG_PRT2_PS
|
|
#define SCSI_Out_DBx__4__SHIFT 5u
|
|
#define SCSI_Out_DBx__4__SLW CYREG_PRT2_SLW
|
|
#define SCSI_Out_DBx__5__AG CYREG_PRT2_AG
|
|
#define SCSI_Out_DBx__5__AMUX CYREG_PRT2_AMUX
|
|
#define SCSI_Out_DBx__5__BIE CYREG_PRT2_BIE
|
|
#define SCSI_Out_DBx__5__BIT_MASK CYREG_PRT2_BIT_MASK
|
|
#define SCSI_Out_DBx__5__BYP CYREG_PRT2_BYP
|
|
#define SCSI_Out_DBx__5__CTL CYREG_PRT2_CTL
|
|
#define SCSI_Out_DBx__5__DM0 CYREG_PRT2_DM0
|
|
#define SCSI_Out_DBx__5__DM1 CYREG_PRT2_DM1
|
|
#define SCSI_Out_DBx__5__DM2 CYREG_PRT2_DM2
|
|
#define SCSI_Out_DBx__5__DR CYREG_PRT2_DR
|
|
#define SCSI_Out_DBx__5__INP_DIS CYREG_PRT2_INP_DIS
|
|
#define SCSI_Out_DBx__5__INTTYPE CYREG_PICU2_INTTYPE3
|
|
#define SCSI_Out_DBx__5__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG
|
|
#define SCSI_Out_DBx__5__LCD_EN CYREG_PRT2_LCD_EN
|
|
#define SCSI_Out_DBx__5__MASK 0x08u
|
|
#define SCSI_Out_DBx__5__PC CYREG_PRT2_PC3
|
|
#define SCSI_Out_DBx__5__PORT 2u
|
|
#define SCSI_Out_DBx__5__PRT CYREG_PRT2_PRT
|
|
#define SCSI_Out_DBx__5__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL
|
|
#define SCSI_Out_DBx__5__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN
|
|
#define SCSI_Out_DBx__5__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0
|
|
#define SCSI_Out_DBx__5__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1
|
|
#define SCSI_Out_DBx__5__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0
|
|
#define SCSI_Out_DBx__5__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1
|
|
#define SCSI_Out_DBx__5__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT
|
|
#define SCSI_Out_DBx__5__PS CYREG_PRT2_PS
|
|
#define SCSI_Out_DBx__5__SHIFT 3u
|
|
#define SCSI_Out_DBx__5__SLW CYREG_PRT2_SLW
|
|
#define SCSI_Out_DBx__6__AG CYREG_PRT2_AG
|
|
#define SCSI_Out_DBx__6__AMUX CYREG_PRT2_AMUX
|
|
#define SCSI_Out_DBx__6__BIE CYREG_PRT2_BIE
|
|
#define SCSI_Out_DBx__6__BIT_MASK CYREG_PRT2_BIT_MASK
|
|
#define SCSI_Out_DBx__6__BYP CYREG_PRT2_BYP
|
|
#define SCSI_Out_DBx__6__CTL CYREG_PRT2_CTL
|
|
#define SCSI_Out_DBx__6__DM0 CYREG_PRT2_DM0
|
|
#define SCSI_Out_DBx__6__DM1 CYREG_PRT2_DM1
|
|
#define SCSI_Out_DBx__6__DM2 CYREG_PRT2_DM2
|
|
#define SCSI_Out_DBx__6__DR CYREG_PRT2_DR
|
|
#define SCSI_Out_DBx__6__INP_DIS CYREG_PRT2_INP_DIS
|
|
#define SCSI_Out_DBx__6__INTTYPE CYREG_PICU2_INTTYPE1
|
|
#define SCSI_Out_DBx__6__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG
|
|
#define SCSI_Out_DBx__6__LCD_EN CYREG_PRT2_LCD_EN
|
|
#define SCSI_Out_DBx__6__MASK 0x02u
|
|
#define SCSI_Out_DBx__6__PC CYREG_PRT2_PC1
|
|
#define SCSI_Out_DBx__6__PORT 2u
|
|
#define SCSI_Out_DBx__6__PRT CYREG_PRT2_PRT
|
|
#define SCSI_Out_DBx__6__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL
|
|
#define SCSI_Out_DBx__6__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN
|
|
#define SCSI_Out_DBx__6__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0
|
|
#define SCSI_Out_DBx__6__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1
|
|
#define SCSI_Out_DBx__6__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0
|
|
#define SCSI_Out_DBx__6__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1
|
|
#define SCSI_Out_DBx__6__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT
|
|
#define SCSI_Out_DBx__6__PS CYREG_PRT2_PS
|
|
#define SCSI_Out_DBx__6__SHIFT 1u
|
|
#define SCSI_Out_DBx__6__SLW CYREG_PRT2_SLW
|
|
#define SCSI_Out_DBx__7__AG CYREG_PRT15_AG
|
|
#define SCSI_Out_DBx__7__AMUX CYREG_PRT15_AMUX
|
|
#define SCSI_Out_DBx__7__BIE CYREG_PRT15_BIE
|
|
#define SCSI_Out_DBx__7__BIT_MASK CYREG_PRT15_BIT_MASK
|
|
#define SCSI_Out_DBx__7__BYP CYREG_PRT15_BYP
|
|
#define SCSI_Out_DBx__7__CTL CYREG_PRT15_CTL
|
|
#define SCSI_Out_DBx__7__DM0 CYREG_PRT15_DM0
|
|
#define SCSI_Out_DBx__7__DM1 CYREG_PRT15_DM1
|
|
#define SCSI_Out_DBx__7__DM2 CYREG_PRT15_DM2
|
|
#define SCSI_Out_DBx__7__DR CYREG_PRT15_DR
|
|
#define SCSI_Out_DBx__7__INP_DIS CYREG_PRT15_INP_DIS
|
|
#define SCSI_Out_DBx__7__INTTYPE CYREG_PICU15_INTTYPE5
|
|
#define SCSI_Out_DBx__7__LCD_COM_SEG CYREG_PRT15_LCD_COM_SEG
|
|
#define SCSI_Out_DBx__7__LCD_EN CYREG_PRT15_LCD_EN
|
|
#define SCSI_Out_DBx__7__MASK 0x20u
|
|
#define SCSI_Out_DBx__7__PC CYREG_IO_PC_PRT15_PC5
|
|
#define SCSI_Out_DBx__7__PORT 15u
|
|
#define SCSI_Out_DBx__7__PRT CYREG_PRT15_PRT
|
|
#define SCSI_Out_DBx__7__PRTDSI__CAPS_SEL CYREG_PRT15_CAPS_SEL
|
|
#define SCSI_Out_DBx__7__PRTDSI__DBL_SYNC_IN CYREG_PRT15_DBL_SYNC_IN
|
|
#define SCSI_Out_DBx__7__PRTDSI__OE_SEL0 CYREG_PRT15_OE_SEL0
|
|
#define SCSI_Out_DBx__7__PRTDSI__OE_SEL1 CYREG_PRT15_OE_SEL1
|
|
#define SCSI_Out_DBx__7__PRTDSI__OUT_SEL0 CYREG_PRT15_OUT_SEL0
|
|
#define SCSI_Out_DBx__7__PRTDSI__OUT_SEL1 CYREG_PRT15_OUT_SEL1
|
|
#define SCSI_Out_DBx__7__PRTDSI__SYNC_OUT CYREG_PRT15_SYNC_OUT
|
|
#define SCSI_Out_DBx__7__PS CYREG_PRT15_PS
|
|
#define SCSI_Out_DBx__7__SHIFT 5u
|
|
#define SCSI_Out_DBx__7__SLW CYREG_PRT15_SLW
|
|
#define SCSI_Out_DBx__DB0__AG CYREG_PRT6_AG
|
|
#define SCSI_Out_DBx__DB0__AMUX CYREG_PRT6_AMUX
|
|
#define SCSI_Out_DBx__DB0__BIE CYREG_PRT6_BIE
|
|
#define SCSI_Out_DBx__DB0__BIT_MASK CYREG_PRT6_BIT_MASK
|
|
#define SCSI_Out_DBx__DB0__BYP CYREG_PRT6_BYP
|
|
#define SCSI_Out_DBx__DB0__CTL CYREG_PRT6_CTL
|
|
#define SCSI_Out_DBx__DB0__DM0 CYREG_PRT6_DM0
|
|
#define SCSI_Out_DBx__DB0__DM1 CYREG_PRT6_DM1
|
|
#define SCSI_Out_DBx__DB0__DM2 CYREG_PRT6_DM2
|
|
#define SCSI_Out_DBx__DB0__DR CYREG_PRT6_DR
|
|
#define SCSI_Out_DBx__DB0__INP_DIS CYREG_PRT6_INP_DIS
|
|
#define SCSI_Out_DBx__DB0__INTTYPE CYREG_PICU6_INTTYPE7
|
|
#define SCSI_Out_DBx__DB0__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG
|
|
#define SCSI_Out_DBx__DB0__LCD_EN CYREG_PRT6_LCD_EN
|
|
#define SCSI_Out_DBx__DB0__MASK 0x80u
|
|
#define SCSI_Out_DBx__DB0__PC CYREG_PRT6_PC7
|
|
#define SCSI_Out_DBx__DB0__PORT 6u
|
|
#define SCSI_Out_DBx__DB0__PRT CYREG_PRT6_PRT
|
|
#define SCSI_Out_DBx__DB0__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL
|
|
#define SCSI_Out_DBx__DB0__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN
|
|
#define SCSI_Out_DBx__DB0__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0
|
|
#define SCSI_Out_DBx__DB0__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1
|
|
#define SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0
|
|
#define SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1
|
|
#define SCSI_Out_DBx__DB0__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT
|
|
#define SCSI_Out_DBx__DB0__PS CYREG_PRT6_PS
|
|
#define SCSI_Out_DBx__DB0__SHIFT 7u
|
|
#define SCSI_Out_DBx__DB0__SLW CYREG_PRT6_SLW
|
|
#define SCSI_Out_DBx__DB1__AG CYREG_PRT6_AG
|
|
#define SCSI_Out_DBx__DB1__AMUX CYREG_PRT6_AMUX
|
|
#define SCSI_Out_DBx__DB1__BIE CYREG_PRT6_BIE
|
|
#define SCSI_Out_DBx__DB1__BIT_MASK CYREG_PRT6_BIT_MASK
|
|
#define SCSI_Out_DBx__DB1__BYP CYREG_PRT6_BYP
|
|
#define SCSI_Out_DBx__DB1__CTL CYREG_PRT6_CTL
|
|
#define SCSI_Out_DBx__DB1__DM0 CYREG_PRT6_DM0
|
|
#define SCSI_Out_DBx__DB1__DM1 CYREG_PRT6_DM1
|
|
#define SCSI_Out_DBx__DB1__DM2 CYREG_PRT6_DM2
|
|
#define SCSI_Out_DBx__DB1__DR CYREG_PRT6_DR
|
|
#define SCSI_Out_DBx__DB1__INP_DIS CYREG_PRT6_INP_DIS
|
|
#define SCSI_Out_DBx__DB1__INTTYPE CYREG_PICU6_INTTYPE5
|
|
#define SCSI_Out_DBx__DB1__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG
|
|
#define SCSI_Out_DBx__DB1__LCD_EN CYREG_PRT6_LCD_EN
|
|
#define SCSI_Out_DBx__DB1__MASK 0x20u
|
|
#define SCSI_Out_DBx__DB1__PC CYREG_PRT6_PC5
|
|
#define SCSI_Out_DBx__DB1__PORT 6u
|
|
#define SCSI_Out_DBx__DB1__PRT CYREG_PRT6_PRT
|
|
#define SCSI_Out_DBx__DB1__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL
|
|
#define SCSI_Out_DBx__DB1__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN
|
|
#define SCSI_Out_DBx__DB1__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0
|
|
#define SCSI_Out_DBx__DB1__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1
|
|
#define SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0
|
|
#define SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1
|
|
#define SCSI_Out_DBx__DB1__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT
|
|
#define SCSI_Out_DBx__DB1__PS CYREG_PRT6_PS
|
|
#define SCSI_Out_DBx__DB1__SHIFT 5u
|
|
#define SCSI_Out_DBx__DB1__SLW CYREG_PRT6_SLW
|
|
#define SCSI_Out_DBx__DB2__AG CYREG_PRT12_AG
|
|
#define SCSI_Out_DBx__DB2__BIE CYREG_PRT12_BIE
|
|
#define SCSI_Out_DBx__DB2__BIT_MASK CYREG_PRT12_BIT_MASK
|
|
#define SCSI_Out_DBx__DB2__BYP CYREG_PRT12_BYP
|
|
#define SCSI_Out_DBx__DB2__DM0 CYREG_PRT12_DM0
|
|
#define SCSI_Out_DBx__DB2__DM1 CYREG_PRT12_DM1
|
|
#define SCSI_Out_DBx__DB2__DM2 CYREG_PRT12_DM2
|
|
#define SCSI_Out_DBx__DB2__DR CYREG_PRT12_DR
|
|
#define SCSI_Out_DBx__DB2__INP_DIS CYREG_PRT12_INP_DIS
|
|
#define SCSI_Out_DBx__DB2__INTTYPE CYREG_PICU12_INTTYPE5
|
|
#define SCSI_Out_DBx__DB2__MASK 0x20u
|
|
#define SCSI_Out_DBx__DB2__PC CYREG_PRT12_PC5
|
|
#define SCSI_Out_DBx__DB2__PORT 12u
|
|
#define SCSI_Out_DBx__DB2__PRT CYREG_PRT12_PRT
|
|
#define SCSI_Out_DBx__DB2__PRTDSI__DBL_SYNC_IN CYREG_PRT12_DBL_SYNC_IN
|
|
#define SCSI_Out_DBx__DB2__PRTDSI__OE_SEL0 CYREG_PRT12_OE_SEL0
|
|
#define SCSI_Out_DBx__DB2__PRTDSI__OE_SEL1 CYREG_PRT12_OE_SEL1
|
|
#define SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL0 CYREG_PRT12_OUT_SEL0
|
|
#define SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL1 CYREG_PRT12_OUT_SEL1
|
|
#define SCSI_Out_DBx__DB2__PRTDSI__SYNC_OUT CYREG_PRT12_SYNC_OUT
|
|
#define SCSI_Out_DBx__DB2__PS CYREG_PRT12_PS
|
|
#define SCSI_Out_DBx__DB2__SHIFT 5u
|
|
#define SCSI_Out_DBx__DB2__SIO_CFG CYREG_PRT12_SIO_CFG
|
|
#define SCSI_Out_DBx__DB2__SIO_DIFF CYREG_PRT12_SIO_DIFF
|
|
#define SCSI_Out_DBx__DB2__SIO_HYST_EN CYREG_PRT12_SIO_HYST_EN
|
|
#define SCSI_Out_DBx__DB2__SIO_REG_HIFREQ CYREG_PRT12_SIO_REG_HIFREQ
|
|
#define SCSI_Out_DBx__DB2__SLW CYREG_PRT12_SLW
|
|
#define SCSI_Out_DBx__DB3__AG CYREG_PRT2_AG
|
|
#define SCSI_Out_DBx__DB3__AMUX CYREG_PRT2_AMUX
|
|
#define SCSI_Out_DBx__DB3__BIE CYREG_PRT2_BIE
|
|
#define SCSI_Out_DBx__DB3__BIT_MASK CYREG_PRT2_BIT_MASK
|
|
#define SCSI_Out_DBx__DB3__BYP CYREG_PRT2_BYP
|
|
#define SCSI_Out_DBx__DB3__CTL CYREG_PRT2_CTL
|
|
#define SCSI_Out_DBx__DB3__DM0 CYREG_PRT2_DM0
|
|
#define SCSI_Out_DBx__DB3__DM1 CYREG_PRT2_DM1
|
|
#define SCSI_Out_DBx__DB3__DM2 CYREG_PRT2_DM2
|
|
#define SCSI_Out_DBx__DB3__DR CYREG_PRT2_DR
|
|
#define SCSI_Out_DBx__DB3__INP_DIS CYREG_PRT2_INP_DIS
|
|
#define SCSI_Out_DBx__DB3__INTTYPE CYREG_PICU2_INTTYPE7
|
|
#define SCSI_Out_DBx__DB3__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG
|
|
#define SCSI_Out_DBx__DB3__LCD_EN CYREG_PRT2_LCD_EN
|
|
#define SCSI_Out_DBx__DB3__MASK 0x80u
|
|
#define SCSI_Out_DBx__DB3__PC CYREG_PRT2_PC7
|
|
#define SCSI_Out_DBx__DB3__PORT 2u
|
|
#define SCSI_Out_DBx__DB3__PRT CYREG_PRT2_PRT
|
|
#define SCSI_Out_DBx__DB3__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL
|
|
#define SCSI_Out_DBx__DB3__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN
|
|
#define SCSI_Out_DBx__DB3__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0
|
|
#define SCSI_Out_DBx__DB3__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1
|
|
#define SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0
|
|
#define SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1
|
|
#define SCSI_Out_DBx__DB3__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT
|
|
#define SCSI_Out_DBx__DB3__PS CYREG_PRT2_PS
|
|
#define SCSI_Out_DBx__DB3__SHIFT 7u
|
|
#define SCSI_Out_DBx__DB3__SLW CYREG_PRT2_SLW
|
|
#define SCSI_Out_DBx__DB4__AG CYREG_PRT2_AG
|
|
#define SCSI_Out_DBx__DB4__AMUX CYREG_PRT2_AMUX
|
|
#define SCSI_Out_DBx__DB4__BIE CYREG_PRT2_BIE
|
|
#define SCSI_Out_DBx__DB4__BIT_MASK CYREG_PRT2_BIT_MASK
|
|
#define SCSI_Out_DBx__DB4__BYP CYREG_PRT2_BYP
|
|
#define SCSI_Out_DBx__DB4__CTL CYREG_PRT2_CTL
|
|
#define SCSI_Out_DBx__DB4__DM0 CYREG_PRT2_DM0
|
|
#define SCSI_Out_DBx__DB4__DM1 CYREG_PRT2_DM1
|
|
#define SCSI_Out_DBx__DB4__DM2 CYREG_PRT2_DM2
|
|
#define SCSI_Out_DBx__DB4__DR CYREG_PRT2_DR
|
|
#define SCSI_Out_DBx__DB4__INP_DIS CYREG_PRT2_INP_DIS
|
|
#define SCSI_Out_DBx__DB4__INTTYPE CYREG_PICU2_INTTYPE5
|
|
#define SCSI_Out_DBx__DB4__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG
|
|
#define SCSI_Out_DBx__DB4__LCD_EN CYREG_PRT2_LCD_EN
|
|
#define SCSI_Out_DBx__DB4__MASK 0x20u
|
|
#define SCSI_Out_DBx__DB4__PC CYREG_PRT2_PC5
|
|
#define SCSI_Out_DBx__DB4__PORT 2u
|
|
#define SCSI_Out_DBx__DB4__PRT CYREG_PRT2_PRT
|
|
#define SCSI_Out_DBx__DB4__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL
|
|
#define SCSI_Out_DBx__DB4__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN
|
|
#define SCSI_Out_DBx__DB4__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0
|
|
#define SCSI_Out_DBx__DB4__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1
|
|
#define SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0
|
|
#define SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1
|
|
#define SCSI_Out_DBx__DB4__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT
|
|
#define SCSI_Out_DBx__DB4__PS CYREG_PRT2_PS
|
|
#define SCSI_Out_DBx__DB4__SHIFT 5u
|
|
#define SCSI_Out_DBx__DB4__SLW CYREG_PRT2_SLW
|
|
#define SCSI_Out_DBx__DB5__AG CYREG_PRT2_AG
|
|
#define SCSI_Out_DBx__DB5__AMUX CYREG_PRT2_AMUX
|
|
#define SCSI_Out_DBx__DB5__BIE CYREG_PRT2_BIE
|
|
#define SCSI_Out_DBx__DB5__BIT_MASK CYREG_PRT2_BIT_MASK
|
|
#define SCSI_Out_DBx__DB5__BYP CYREG_PRT2_BYP
|
|
#define SCSI_Out_DBx__DB5__CTL CYREG_PRT2_CTL
|
|
#define SCSI_Out_DBx__DB5__DM0 CYREG_PRT2_DM0
|
|
#define SCSI_Out_DBx__DB5__DM1 CYREG_PRT2_DM1
|
|
#define SCSI_Out_DBx__DB5__DM2 CYREG_PRT2_DM2
|
|
#define SCSI_Out_DBx__DB5__DR CYREG_PRT2_DR
|
|
#define SCSI_Out_DBx__DB5__INP_DIS CYREG_PRT2_INP_DIS
|
|
#define SCSI_Out_DBx__DB5__INTTYPE CYREG_PICU2_INTTYPE3
|
|
#define SCSI_Out_DBx__DB5__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG
|
|
#define SCSI_Out_DBx__DB5__LCD_EN CYREG_PRT2_LCD_EN
|
|
#define SCSI_Out_DBx__DB5__MASK 0x08u
|
|
#define SCSI_Out_DBx__DB5__PC CYREG_PRT2_PC3
|
|
#define SCSI_Out_DBx__DB5__PORT 2u
|
|
#define SCSI_Out_DBx__DB5__PRT CYREG_PRT2_PRT
|
|
#define SCSI_Out_DBx__DB5__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL
|
|
#define SCSI_Out_DBx__DB5__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN
|
|
#define SCSI_Out_DBx__DB5__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0
|
|
#define SCSI_Out_DBx__DB5__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1
|
|
#define SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0
|
|
#define SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1
|
|
#define SCSI_Out_DBx__DB5__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT
|
|
#define SCSI_Out_DBx__DB5__PS CYREG_PRT2_PS
|
|
#define SCSI_Out_DBx__DB5__SHIFT 3u
|
|
#define SCSI_Out_DBx__DB5__SLW CYREG_PRT2_SLW
|
|
#define SCSI_Out_DBx__DB6__AG CYREG_PRT2_AG
|
|
#define SCSI_Out_DBx__DB6__AMUX CYREG_PRT2_AMUX
|
|
#define SCSI_Out_DBx__DB6__BIE CYREG_PRT2_BIE
|
|
#define SCSI_Out_DBx__DB6__BIT_MASK CYREG_PRT2_BIT_MASK
|
|
#define SCSI_Out_DBx__DB6__BYP CYREG_PRT2_BYP
|
|
#define SCSI_Out_DBx__DB6__CTL CYREG_PRT2_CTL
|
|
#define SCSI_Out_DBx__DB6__DM0 CYREG_PRT2_DM0
|
|
#define SCSI_Out_DBx__DB6__DM1 CYREG_PRT2_DM1
|
|
#define SCSI_Out_DBx__DB6__DM2 CYREG_PRT2_DM2
|
|
#define SCSI_Out_DBx__DB6__DR CYREG_PRT2_DR
|
|
#define SCSI_Out_DBx__DB6__INP_DIS CYREG_PRT2_INP_DIS
|
|
#define SCSI_Out_DBx__DB6__INTTYPE CYREG_PICU2_INTTYPE1
|
|
#define SCSI_Out_DBx__DB6__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG
|
|
#define SCSI_Out_DBx__DB6__LCD_EN CYREG_PRT2_LCD_EN
|
|
#define SCSI_Out_DBx__DB6__MASK 0x02u
|
|
#define SCSI_Out_DBx__DB6__PC CYREG_PRT2_PC1
|
|
#define SCSI_Out_DBx__DB6__PORT 2u
|
|
#define SCSI_Out_DBx__DB6__PRT CYREG_PRT2_PRT
|
|
#define SCSI_Out_DBx__DB6__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL
|
|
#define SCSI_Out_DBx__DB6__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN
|
|
#define SCSI_Out_DBx__DB6__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0
|
|
#define SCSI_Out_DBx__DB6__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1
|
|
#define SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0
|
|
#define SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1
|
|
#define SCSI_Out_DBx__DB6__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT
|
|
#define SCSI_Out_DBx__DB6__PS CYREG_PRT2_PS
|
|
#define SCSI_Out_DBx__DB6__SHIFT 1u
|
|
#define SCSI_Out_DBx__DB6__SLW CYREG_PRT2_SLW
|
|
#define SCSI_Out_DBx__DB7__AG CYREG_PRT15_AG
|
|
#define SCSI_Out_DBx__DB7__AMUX CYREG_PRT15_AMUX
|
|
#define SCSI_Out_DBx__DB7__BIE CYREG_PRT15_BIE
|
|
#define SCSI_Out_DBx__DB7__BIT_MASK CYREG_PRT15_BIT_MASK
|
|
#define SCSI_Out_DBx__DB7__BYP CYREG_PRT15_BYP
|
|
#define SCSI_Out_DBx__DB7__CTL CYREG_PRT15_CTL
|
|
#define SCSI_Out_DBx__DB7__DM0 CYREG_PRT15_DM0
|
|
#define SCSI_Out_DBx__DB7__DM1 CYREG_PRT15_DM1
|
|
#define SCSI_Out_DBx__DB7__DM2 CYREG_PRT15_DM2
|
|
#define SCSI_Out_DBx__DB7__DR CYREG_PRT15_DR
|
|
#define SCSI_Out_DBx__DB7__INP_DIS CYREG_PRT15_INP_DIS
|
|
#define SCSI_Out_DBx__DB7__INTTYPE CYREG_PICU15_INTTYPE5
|
|
#define SCSI_Out_DBx__DB7__LCD_COM_SEG CYREG_PRT15_LCD_COM_SEG
|
|
#define SCSI_Out_DBx__DB7__LCD_EN CYREG_PRT15_LCD_EN
|
|
#define SCSI_Out_DBx__DB7__MASK 0x20u
|
|
#define SCSI_Out_DBx__DB7__PC CYREG_IO_PC_PRT15_PC5
|
|
#define SCSI_Out_DBx__DB7__PORT 15u
|
|
#define SCSI_Out_DBx__DB7__PRT CYREG_PRT15_PRT
|
|
#define SCSI_Out_DBx__DB7__PRTDSI__CAPS_SEL CYREG_PRT15_CAPS_SEL
|
|
#define SCSI_Out_DBx__DB7__PRTDSI__DBL_SYNC_IN CYREG_PRT15_DBL_SYNC_IN
|
|
#define SCSI_Out_DBx__DB7__PRTDSI__OE_SEL0 CYREG_PRT15_OE_SEL0
|
|
#define SCSI_Out_DBx__DB7__PRTDSI__OE_SEL1 CYREG_PRT15_OE_SEL1
|
|
#define SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL0 CYREG_PRT15_OUT_SEL0
|
|
#define SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL1 CYREG_PRT15_OUT_SEL1
|
|
#define SCSI_Out_DBx__DB7__PRTDSI__SYNC_OUT CYREG_PRT15_SYNC_OUT
|
|
#define SCSI_Out_DBx__DB7__PS CYREG_PRT15_PS
|
|
#define SCSI_Out_DBx__DB7__SHIFT 5u
|
|
#define SCSI_Out_DBx__DB7__SLW CYREG_PRT15_SLW
|
|
|
|
/* SD_PULLUP */
|
|
#define SD_PULLUP__0__INTTYPE CYREG_PICU3_INTTYPE0
|
|
#define SD_PULLUP__0__MASK 0x01u
|
|
#define SD_PULLUP__0__PC CYREG_PRT3_PC0
|
|
#define SD_PULLUP__0__PORT 3u
|
|
#define SD_PULLUP__0__SHIFT 0u
|
|
#define SD_PULLUP__1__INTTYPE CYREG_PICU3_INTTYPE1
|
|
#define SD_PULLUP__1__MASK 0x02u
|
|
#define SD_PULLUP__1__PC CYREG_PRT3_PC1
|
|
#define SD_PULLUP__1__PORT 3u
|
|
#define SD_PULLUP__1__SHIFT 1u
|
|
#define SD_PULLUP__2__INTTYPE CYREG_PICU3_INTTYPE2
|
|
#define SD_PULLUP__2__MASK 0x04u
|
|
#define SD_PULLUP__2__PC CYREG_PRT3_PC2
|
|
#define SD_PULLUP__2__PORT 3u
|
|
#define SD_PULLUP__2__SHIFT 2u
|
|
#define SD_PULLUP__3__INTTYPE CYREG_PICU3_INTTYPE3
|
|
#define SD_PULLUP__3__MASK 0x08u
|
|
#define SD_PULLUP__3__PC CYREG_PRT3_PC3
|
|
#define SD_PULLUP__3__PORT 3u
|
|
#define SD_PULLUP__3__SHIFT 3u
|
|
#define SD_PULLUP__AG CYREG_PRT3_AG
|
|
#define SD_PULLUP__AMUX CYREG_PRT3_AMUX
|
|
#define SD_PULLUP__BIE CYREG_PRT3_BIE
|
|
#define SD_PULLUP__BIT_MASK CYREG_PRT3_BIT_MASK
|
|
#define SD_PULLUP__BYP CYREG_PRT3_BYP
|
|
#define SD_PULLUP__CTL CYREG_PRT3_CTL
|
|
#define SD_PULLUP__DM0 CYREG_PRT3_DM0
|
|
#define SD_PULLUP__DM1 CYREG_PRT3_DM1
|
|
#define SD_PULLUP__DM2 CYREG_PRT3_DM2
|
|
#define SD_PULLUP__DR CYREG_PRT3_DR
|
|
#define SD_PULLUP__INP_DIS CYREG_PRT3_INP_DIS
|
|
#define SD_PULLUP__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU3_BASE
|
|
#define SD_PULLUP__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG
|
|
#define SD_PULLUP__LCD_EN CYREG_PRT3_LCD_EN
|
|
#define SD_PULLUP__MASK 0x0Fu
|
|
#define SD_PULLUP__PORT 3u
|
|
#define SD_PULLUP__PRT CYREG_PRT3_PRT
|
|
#define SD_PULLUP__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL
|
|
#define SD_PULLUP__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN
|
|
#define SD_PULLUP__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0
|
|
#define SD_PULLUP__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1
|
|
#define SD_PULLUP__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0
|
|
#define SD_PULLUP__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1
|
|
#define SD_PULLUP__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT
|
|
#define SD_PULLUP__PS CYREG_PRT3_PS
|
|
#define SD_PULLUP__SHIFT 0u
|
|
#define SD_PULLUP__SLW CYREG_PRT3_SLW
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/* SPI_PULLUP */
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#define SPI_PULLUP__0__INTTYPE CYREG_PICU3_INTTYPE4
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#define SPI_PULLUP__0__MASK 0x10u
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#define SPI_PULLUP__0__PC CYREG_PRT3_PC4
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#define SPI_PULLUP__0__PORT 3u
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#define SPI_PULLUP__0__SHIFT 4u
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#define SPI_PULLUP__1__INTTYPE CYREG_PICU3_INTTYPE5
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#define SPI_PULLUP__1__MASK 0x20u
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#define SPI_PULLUP__1__PC CYREG_PRT3_PC5
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#define SPI_PULLUP__1__PORT 3u
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#define SPI_PULLUP__1__SHIFT 5u
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#define SPI_PULLUP__2__INTTYPE CYREG_PICU3_INTTYPE6
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#define SPI_PULLUP__2__MASK 0x40u
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#define SPI_PULLUP__2__PC CYREG_PRT3_PC6
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#define SPI_PULLUP__2__PORT 3u
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#define SPI_PULLUP__2__SHIFT 6u
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#define SPI_PULLUP__3__INTTYPE CYREG_PICU3_INTTYPE7
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#define SPI_PULLUP__3__MASK 0x80u
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#define SPI_PULLUP__3__PC CYREG_PRT3_PC7
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#define SPI_PULLUP__3__PORT 3u
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#define SPI_PULLUP__3__SHIFT 7u
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#define SPI_PULLUP__AG CYREG_PRT3_AG
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#define SPI_PULLUP__AMUX CYREG_PRT3_AMUX
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#define SPI_PULLUP__BIE CYREG_PRT3_BIE
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#define SPI_PULLUP__BIT_MASK CYREG_PRT3_BIT_MASK
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#define SPI_PULLUP__BYP CYREG_PRT3_BYP
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#define SPI_PULLUP__CTL CYREG_PRT3_CTL
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#define SPI_PULLUP__DM0 CYREG_PRT3_DM0
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#define SPI_PULLUP__DM1 CYREG_PRT3_DM1
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#define SPI_PULLUP__DM2 CYREG_PRT3_DM2
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#define SPI_PULLUP__DR CYREG_PRT3_DR
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#define SPI_PULLUP__INP_DIS CYREG_PRT3_INP_DIS
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#define SPI_PULLUP__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU3_BASE
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#define SPI_PULLUP__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG
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#define SPI_PULLUP__LCD_EN CYREG_PRT3_LCD_EN
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#define SPI_PULLUP__MASK 0xF0u
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#define SPI_PULLUP__PORT 3u
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#define SPI_PULLUP__PRT CYREG_PRT3_PRT
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#define SPI_PULLUP__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL
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#define SPI_PULLUP__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN
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#define SPI_PULLUP__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0
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#define SPI_PULLUP__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1
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#define SPI_PULLUP__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0
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#define SPI_PULLUP__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1
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#define SPI_PULLUP__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT
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#define SPI_PULLUP__PS CYREG_PRT3_PS
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#define SPI_PULLUP__SHIFT 4u
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#define SPI_PULLUP__SLW CYREG_PRT3_SLW
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#define SPI_PULLUP_1__0__INTTYPE CYREG_PICU12_INTTYPE0
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#define SPI_PULLUP_1__0__MASK 0x01u
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#define SPI_PULLUP_1__0__PC CYREG_PRT12_PC0
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#define SPI_PULLUP_1__0__PORT 12u
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#define SPI_PULLUP_1__0__SHIFT 0u
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#define SPI_PULLUP_1__1__INTTYPE CYREG_PICU12_INTTYPE1
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#define SPI_PULLUP_1__1__MASK 0x02u
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#define SPI_PULLUP_1__1__PC CYREG_PRT12_PC1
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#define SPI_PULLUP_1__1__PORT 12u
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#define SPI_PULLUP_1__1__SHIFT 1u
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#define SPI_PULLUP_1__AG CYREG_PRT12_AG
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#define SPI_PULLUP_1__BIE CYREG_PRT12_BIE
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#define SPI_PULLUP_1__BIT_MASK CYREG_PRT12_BIT_MASK
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#define SPI_PULLUP_1__BYP CYREG_PRT12_BYP
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#define SPI_PULLUP_1__DM0 CYREG_PRT12_DM0
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#define SPI_PULLUP_1__DM1 CYREG_PRT12_DM1
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#define SPI_PULLUP_1__DM2 CYREG_PRT12_DM2
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#define SPI_PULLUP_1__DR CYREG_PRT12_DR
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#define SPI_PULLUP_1__INP_DIS CYREG_PRT12_INP_DIS
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#define SPI_PULLUP_1__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU12_BASE
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#define SPI_PULLUP_1__MASK 0x03u
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#define SPI_PULLUP_1__PORT 12u
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#define SPI_PULLUP_1__PRT CYREG_PRT12_PRT
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#define SPI_PULLUP_1__PRTDSI__DBL_SYNC_IN CYREG_PRT12_DBL_SYNC_IN
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#define SPI_PULLUP_1__PRTDSI__OE_SEL0 CYREG_PRT12_OE_SEL0
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#define SPI_PULLUP_1__PRTDSI__OE_SEL1 CYREG_PRT12_OE_SEL1
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#define SPI_PULLUP_1__PRTDSI__OUT_SEL0 CYREG_PRT12_OUT_SEL0
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#define SPI_PULLUP_1__PRTDSI__OUT_SEL1 CYREG_PRT12_OUT_SEL1
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#define SPI_PULLUP_1__PRTDSI__SYNC_OUT CYREG_PRT12_SYNC_OUT
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#define SPI_PULLUP_1__PS CYREG_PRT12_PS
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#define SPI_PULLUP_1__SHIFT 0u
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#define SPI_PULLUP_1__SIO_CFG CYREG_PRT12_SIO_CFG
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#define SPI_PULLUP_1__SIO_DIFF CYREG_PRT12_SIO_DIFF
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#define SPI_PULLUP_1__SIO_HYST_EN CYREG_PRT12_SIO_HYST_EN
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#define SPI_PULLUP_1__SIO_REG_HIFREQ CYREG_PRT12_SIO_REG_HIFREQ
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#define SPI_PULLUP_1__SLW CYREG_PRT12_SLW
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/* Miscellaneous */
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#define BCLK__BUS_CLK__HZ 64000000U
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#define BCLK__BUS_CLK__KHZ 64000U
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#define BCLK__BUS_CLK__MHZ 64U
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#define CY_PROJECT_NAME "USB_Bootloader"
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#define CY_VERSION "PSoC Creator 4.4"
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#define CYDEV_BOOTLOADER_APPLICATIONS 1u
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#define CYDEV_BOOTLOADER_CHECKSUM_BASIC 0
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#define CYDEV_BOOTLOADER_CHECKSUM_CRC 1
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#define CYDEV_BOOTLOADER_IO_COMP_CUSTOM_IO 0
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#define CyBtldr_Custom_Interface CYDEV_BOOTLOADER_IO_COMP_CUSTOM_IO
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#define CYDEV_BOOTLOADER_IO_COMP_LAUNCHER_ONLY 1
|
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#define CyBtldr_LAUNCHER_ONLY CYDEV_BOOTLOADER_IO_COMP_LAUNCHER_ONLY
|
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#define CYDEV_BOOTLOADER_IO_COMP_USBFS 2
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#define CyBtldr_USBFS CYDEV_BOOTLOADER_IO_COMP_USBFS
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#define CYDEV_BOOTLOADER_IO_COMP CYDEV_BOOTLOADER_IO_COMP_USBFS
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#define CYDEV_CHIP_DIE_LEOPARD 1u
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#define CYDEV_CHIP_DIE_PSOC4A 26u
|
|
#define CYDEV_CHIP_DIE_PSOC5LP 2u
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|
#define CYDEV_CHIP_DIE_PSOC5TM 3u
|
|
#define CYDEV_CHIP_DIE_TMA4 4u
|
|
#define CYDEV_CHIP_DIE_UNKNOWN 0u
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|
#define CYDEV_CHIP_FAMILY_FM0P 5u
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#define CYDEV_CHIP_FAMILY_FM3 6u
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#define CYDEV_CHIP_FAMILY_FM4 7u
|
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#define CYDEV_CHIP_FAMILY_PSOC3 1u
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|
#define CYDEV_CHIP_FAMILY_PSOC4 2u
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|
#define CYDEV_CHIP_FAMILY_PSOC5 3u
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|
#define CYDEV_CHIP_FAMILY_PSOC6 4u
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|
#define CYDEV_CHIP_FAMILY_UNKNOWN 0u
|
|
#define CYDEV_CHIP_FAMILY_USED CYDEV_CHIP_FAMILY_PSOC5
|
|
#define CYDEV_CHIP_JTAG_ID 0x2E133069u
|
|
#define CYDEV_CHIP_MEMBER_3A 1u
|
|
#define CYDEV_CHIP_MEMBER_4A 26u
|
|
#define CYDEV_CHIP_MEMBER_4AA 25u
|
|
#define CYDEV_CHIP_MEMBER_4AB 30u
|
|
#define CYDEV_CHIP_MEMBER_4AC 14u
|
|
#define CYDEV_CHIP_MEMBER_4AD 15u
|
|
#define CYDEV_CHIP_MEMBER_4AE 16u
|
|
#define CYDEV_CHIP_MEMBER_4D 20u
|
|
#define CYDEV_CHIP_MEMBER_4E 6u
|
|
#define CYDEV_CHIP_MEMBER_4F 27u
|
|
#define CYDEV_CHIP_MEMBER_4G 4u
|
|
#define CYDEV_CHIP_MEMBER_4H 24u
|
|
#define CYDEV_CHIP_MEMBER_4I 32u
|
|
#define CYDEV_CHIP_MEMBER_4J 21u
|
|
#define CYDEV_CHIP_MEMBER_4K 22u
|
|
#define CYDEV_CHIP_MEMBER_4L 31u
|
|
#define CYDEV_CHIP_MEMBER_4M 29u
|
|
#define CYDEV_CHIP_MEMBER_4N 11u
|
|
#define CYDEV_CHIP_MEMBER_4O 8u
|
|
#define CYDEV_CHIP_MEMBER_4P 28u
|
|
#define CYDEV_CHIP_MEMBER_4Q 17u
|
|
#define CYDEV_CHIP_MEMBER_4R 9u
|
|
#define CYDEV_CHIP_MEMBER_4S 12u
|
|
#define CYDEV_CHIP_MEMBER_4T 10u
|
|
#define CYDEV_CHIP_MEMBER_4U 5u
|
|
#define CYDEV_CHIP_MEMBER_4V 23u
|
|
#define CYDEV_CHIP_MEMBER_4W 13u
|
|
#define CYDEV_CHIP_MEMBER_4X 7u
|
|
#define CYDEV_CHIP_MEMBER_4Y 18u
|
|
#define CYDEV_CHIP_MEMBER_4Z 19u
|
|
#define CYDEV_CHIP_MEMBER_5A 3u
|
|
#define CYDEV_CHIP_MEMBER_5B 2u
|
|
#define CYDEV_CHIP_MEMBER_6A 33u
|
|
#define CYDEV_CHIP_MEMBER_FM3 37u
|
|
#define CYDEV_CHIP_MEMBER_FM4 38u
|
|
#define CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE1 34u
|
|
#define CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE2 35u
|
|
#define CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE3 36u
|
|
#define CYDEV_CHIP_MEMBER_UNKNOWN 0u
|
|
#define CYDEV_CHIP_MEMBER_USED CYDEV_CHIP_MEMBER_5B
|
|
#define CYDEV_CHIP_DIE_EXPECT CYDEV_CHIP_MEMBER_USED
|
|
#define CYDEV_CHIP_DIE_ACTUAL CYDEV_CHIP_DIE_EXPECT
|
|
#define CYDEV_CHIP_REV_LEOPARD_ES1 0u
|
|
#define CYDEV_CHIP_REV_LEOPARD_ES2 1u
|
|
#define CYDEV_CHIP_REV_LEOPARD_ES3 3u
|
|
#define CYDEV_CHIP_REV_LEOPARD_PRODUCTION 3u
|
|
#define CYDEV_CHIP_REV_PSOC4A_ES0 17u
|
|
#define CYDEV_CHIP_REV_PSOC4A_PRODUCTION 17u
|
|
#define CYDEV_CHIP_REV_PSOC5LP_ES0 0u
|
|
#define CYDEV_CHIP_REV_PSOC5LP_PRODUCTION 0u
|
|
#define CYDEV_CHIP_REV_PSOC5TM_ES0 0u
|
|
#define CYDEV_CHIP_REV_PSOC5TM_ES1 1u
|
|
#define CYDEV_CHIP_REV_PSOC5TM_PRODUCTION 1u
|
|
#define CYDEV_CHIP_REV_TMA4_ES 17u
|
|
#define CYDEV_CHIP_REV_TMA4_ES2 33u
|
|
#define CYDEV_CHIP_REV_TMA4_PRODUCTION 17u
|
|
#define CYDEV_CHIP_REVISION_3A_ES1 0u
|
|
#define CYDEV_CHIP_REVISION_3A_ES2 1u
|
|
#define CYDEV_CHIP_REVISION_3A_ES3 3u
|
|
#define CYDEV_CHIP_REVISION_3A_PRODUCTION 3u
|
|
#define CYDEV_CHIP_REVISION_4A_ES0 17u
|
|
#define CYDEV_CHIP_REVISION_4A_PRODUCTION 17u
|
|
#define CYDEV_CHIP_REVISION_4AA_PRODUCTION 0u
|
|
#define CYDEV_CHIP_REVISION_4AB_PRODUCTION 0u
|
|
#define CYDEV_CHIP_REVISION_4AC_PRODUCTION 0u
|
|
#define CYDEV_CHIP_REVISION_4AD_PRODUCTION 0u
|
|
#define CYDEV_CHIP_REVISION_4AE_PRODUCTION 0u
|
|
#define CYDEV_CHIP_REVISION_4D_PRODUCTION 0u
|
|
#define CYDEV_CHIP_REVISION_4E_CCG2_NO_USBPD 0u
|
|
#define CYDEV_CHIP_REVISION_4E_PRODUCTION 0u
|
|
#define CYDEV_CHIP_REVISION_4F_PRODUCTION 0u
|
|
#define CYDEV_CHIP_REVISION_4F_PRODUCTION_256DMA 0u
|
|
#define CYDEV_CHIP_REVISION_4F_PRODUCTION_256K 0u
|
|
#define CYDEV_CHIP_REVISION_4G_ES 17u
|
|
#define CYDEV_CHIP_REVISION_4G_ES2 33u
|
|
#define CYDEV_CHIP_REVISION_4G_PRODUCTION 17u
|
|
#define CYDEV_CHIP_REVISION_4H_PRODUCTION 0u
|
|
#define CYDEV_CHIP_REVISION_4I_PRODUCTION 0u
|
|
#define CYDEV_CHIP_REVISION_4J_PRODUCTION 0u
|
|
#define CYDEV_CHIP_REVISION_4K_PRODUCTION 0u
|
|
#define CYDEV_CHIP_REVISION_4L_PRODUCTION 0u
|
|
#define CYDEV_CHIP_REVISION_4M_PRODUCTION 0u
|
|
#define CYDEV_CHIP_REVISION_4N_PRODUCTION 0u
|
|
#define CYDEV_CHIP_REVISION_4O_PRODUCTION 0u
|
|
#define CYDEV_CHIP_REVISION_4P_PRODUCTION 0u
|
|
#define CYDEV_CHIP_REVISION_4Q_PRODUCTION 0u
|
|
#define CYDEV_CHIP_REVISION_4R_PRODUCTION 0u
|
|
#define CYDEV_CHIP_REVISION_4S_PRODUCTION 0u
|
|
#define CYDEV_CHIP_REVISION_4T_PRODUCTION 0u
|
|
#define CYDEV_CHIP_REVISION_4U_PRODUCTION 0u
|
|
#define CYDEV_CHIP_REVISION_4V_PRODUCTION 0u
|
|
#define CYDEV_CHIP_REVISION_4W_PRODUCTION 0u
|
|
#define CYDEV_CHIP_REVISION_4X_PRODUCTION 0u
|
|
#define CYDEV_CHIP_REVISION_4Y_PRODUCTION 0u
|
|
#define CYDEV_CHIP_REVISION_4Z_PRODUCTION 0u
|
|
#define CYDEV_CHIP_REVISION_5A_ES0 0u
|
|
#define CYDEV_CHIP_REVISION_5A_ES1 1u
|
|
#define CYDEV_CHIP_REVISION_5A_PRODUCTION 1u
|
|
#define CYDEV_CHIP_REVISION_5B_ES0 0u
|
|
#define CYDEV_CHIP_REVISION_5B_PRODUCTION 0u
|
|
#define CYDEV_CHIP_REVISION_6A_ES 17u
|
|
#define CYDEV_CHIP_REVISION_6A_NO_UDB 33u
|
|
#define CYDEV_CHIP_REVISION_6A_PRODUCTION 33u
|
|
#define CYDEV_CHIP_REVISION_FM3_PRODUCTION 0u
|
|
#define CYDEV_CHIP_REVISION_FM4_PRODUCTION 0u
|
|
#define CYDEV_CHIP_REVISION_PDL_FM0P_TYPE1_PRODUCTION 0u
|
|
#define CYDEV_CHIP_REVISION_PDL_FM0P_TYPE2_PRODUCTION 0u
|
|
#define CYDEV_CHIP_REVISION_PDL_FM0P_TYPE3_PRODUCTION 0u
|
|
#define CYDEV_CHIP_REVISION_USED CYDEV_CHIP_REVISION_5B_PRODUCTION
|
|
#define CYDEV_CHIP_REV_EXPECT CYDEV_CHIP_REVISION_USED
|
|
#define CYDEV_CONFIG_FASTBOOT_ENABLED 1
|
|
#define CYDEV_CONFIG_UNUSED_IO_AllowButWarn 0
|
|
#define CYDEV_CONFIG_UNUSED_IO CYDEV_CONFIG_UNUSED_IO_AllowButWarn
|
|
#define CYDEV_CONFIG_UNUSED_IO_AllowWithInfo 1
|
|
#define CYDEV_CONFIG_UNUSED_IO_Disallowed 2
|
|
#define CYDEV_CONFIGURATION_COMPRESSED 1
|
|
#define CYDEV_CONFIGURATION_DMA 0
|
|
#define CYDEV_CONFIGURATION_ECC 1
|
|
#define CYDEV_CONFIGURATION_IMOENABLED CYDEV_CONFIG_FASTBOOT_ENABLED
|
|
#define CYDEV_CONFIGURATION_MODE_COMPRESSED 0
|
|
#define CYDEV_CONFIGURATION_MODE CYDEV_CONFIGURATION_MODE_COMPRESSED
|
|
#define CYDEV_CONFIGURATION_MODE_DMA 2
|
|
#define CYDEV_CONFIGURATION_MODE_UNCOMPRESSED 1
|
|
#define CYDEV_DEBUG_ENABLE_MASK 0x20u
|
|
#define CYDEV_DEBUG_ENABLE_REGISTER CYREG_MLOGIC_DEBUG
|
|
#define CYDEV_DEBUGGING_DPS_Disable 3
|
|
#define CYDEV_DEBUGGING_DPS_JTAG_4 1
|
|
#define CYDEV_DEBUGGING_DPS_JTAG_5 0
|
|
#define CYDEV_DEBUGGING_DPS_SWD 2
|
|
#define CYDEV_DEBUGGING_DPS_SWD_SWV 6
|
|
#define CYDEV_DEBUGGING_DPS CYDEV_DEBUGGING_DPS_SWD_SWV
|
|
#define CYDEV_DEBUGGING_ENABLE 1
|
|
#define CYDEV_DEBUGGING_XRES 0
|
|
#define CYDEV_DMA_CHANNELS_AVAILABLE 24u
|
|
#define CYDEV_ECC_ENABLE 0
|
|
#define CYDEV_HEAP_SIZE 0x0800
|
|
#define CYDEV_INSTRUCT_CACHE_ENABLED 1
|
|
#define CYDEV_INTR_RISING 0x00000000u
|
|
#define CYDEV_IS_EXPORTING_CODE 0
|
|
#define CYDEV_IS_IMPORTING_CODE 0
|
|
#define CYDEV_PROJ_TYPE 1
|
|
#define CYDEV_PROJ_TYPE_BOOTLOADER 1
|
|
#define CYDEV_PROJ_TYPE_LAUNCHER 5
|
|
#define CYDEV_PROJ_TYPE_LOADABLE 2
|
|
#define CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER 4
|
|
#define CYDEV_PROJ_TYPE_MULTIAPPBOOTLOADER 3
|
|
#define CYDEV_PROJ_TYPE_STANDARD 0
|
|
#define CYDEV_PROTECTION_ENABLE 0
|
|
#define CYDEV_STACK_SIZE 0x2000
|
|
#define CYDEV_USB_CLK_OSC_LOCKING_ENABLED_AT_PWR_UP
|
|
#define CYDEV_USE_BUNDLED_CMSIS 1
|
|
#define CYDEV_VARIABLE_VDDA 0
|
|
#define CYDEV_VDDA 5.0
|
|
#define CYDEV_VDDA_MV 5000
|
|
#define CYDEV_VDDD 5.0
|
|
#define CYDEV_VDDD_MV 5000
|
|
#define CYDEV_VDDIO0 5.0
|
|
#define CYDEV_VDDIO0_MV 5000
|
|
#define CYDEV_VDDIO1 5.0
|
|
#define CYDEV_VDDIO1_MV 5000
|
|
#define CYDEV_VDDIO2 5.0
|
|
#define CYDEV_VDDIO2_MV 5000
|
|
#define CYDEV_VDDIO3 3.0
|
|
#define CYDEV_VDDIO3_MV 3000
|
|
#define CYDEV_VIO0 5.0
|
|
#define CYDEV_VIO0_MV 5000
|
|
#define CYDEV_VIO1 5.0
|
|
#define CYDEV_VIO1_MV 5000
|
|
#define CYDEV_VIO2 5.0
|
|
#define CYDEV_VIO2_MV 5000
|
|
#define CYDEV_VIO3 3.0
|
|
#define CYDEV_VIO3_MV 3000
|
|
#define CYIPBLOCK_ARM_CM3_VERSION 0
|
|
#define CYIPBLOCK_P3_ANAIF_VERSION 0
|
|
#define CYIPBLOCK_P3_CAPSENSE_VERSION 0
|
|
#define CYIPBLOCK_P3_COMP_VERSION 0
|
|
#define CYIPBLOCK_P3_DMA_VERSION 0
|
|
#define CYIPBLOCK_P3_DRQ_VERSION 0
|
|
#define CYIPBLOCK_P3_EMIF_VERSION 0
|
|
#define CYIPBLOCK_P3_I2C_VERSION 0
|
|
#define CYIPBLOCK_P3_LCD_VERSION 0
|
|
#define CYIPBLOCK_P3_LPF_VERSION 0
|
|
#define CYIPBLOCK_P3_PM_VERSION 0
|
|
#define CYIPBLOCK_P3_TIMER_VERSION 0
|
|
#define CYIPBLOCK_P3_USB_VERSION 0
|
|
#define CYIPBLOCK_P3_VIDAC_VERSION 0
|
|
#define CYIPBLOCK_P3_VREF_VERSION 0
|
|
#define CYIPBLOCK_S8_GPIO_VERSION 0
|
|
#define CYIPBLOCK_S8_IRQ_VERSION 0
|
|
#define CYIPBLOCK_S8_SAR_VERSION 0
|
|
#define CYIPBLOCK_S8_SIO_VERSION 0
|
|
#define CYIPBLOCK_S8_UDB_VERSION 0
|
|
#define DMA_CHANNELS_USED__MASK0 0x00000000u
|
|
#define CYDEV_BOOTLOADER_ENABLE 1
|
|
|
|
#endif /* INCLUDED_CYFITTER_H */
|