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71 lines
2.8 KiB
C
Executable File
71 lines
2.8 KiB
C
Executable File
/*******************************************************************************
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* File Name: SCSI_TX_DMA_COMPLETE.h
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* Version 1.70
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*
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* Description:
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* Provides the function definitions for the Interrupt Controller.
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*
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*
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********************************************************************************
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* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved.
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* You may use this file only in accordance with the license, terms, conditions,
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* disclaimers, and limitations in the end user license agreement accompanying
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* the software package with which this file was provided.
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*******************************************************************************/
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#if !defined(CY_ISR_SCSI_TX_DMA_COMPLETE_H)
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#define CY_ISR_SCSI_TX_DMA_COMPLETE_H
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#include <cytypes.h>
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#include <cyfitter.h>
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/* Interrupt Controller API. */
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void SCSI_TX_DMA_COMPLETE_Start(void);
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void SCSI_TX_DMA_COMPLETE_StartEx(cyisraddress address);
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void SCSI_TX_DMA_COMPLETE_Stop(void);
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CY_ISR_PROTO(SCSI_TX_DMA_COMPLETE_Interrupt);
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void SCSI_TX_DMA_COMPLETE_SetVector(cyisraddress address);
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cyisraddress SCSI_TX_DMA_COMPLETE_GetVector(void);
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void SCSI_TX_DMA_COMPLETE_SetPriority(uint8 priority);
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uint8 SCSI_TX_DMA_COMPLETE_GetPriority(void);
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void SCSI_TX_DMA_COMPLETE_Enable(void);
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uint8 SCSI_TX_DMA_COMPLETE_GetState(void);
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void SCSI_TX_DMA_COMPLETE_Disable(void);
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void SCSI_TX_DMA_COMPLETE_SetPending(void);
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void SCSI_TX_DMA_COMPLETE_ClearPending(void);
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/* Interrupt Controller Constants */
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/* Address of the INTC.VECT[x] register that contains the Address of the SCSI_TX_DMA_COMPLETE ISR. */
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#define SCSI_TX_DMA_COMPLETE_INTC_VECTOR ((reg32 *) SCSI_TX_DMA_COMPLETE__INTC_VECT)
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/* Address of the SCSI_TX_DMA_COMPLETE ISR priority. */
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#define SCSI_TX_DMA_COMPLETE_INTC_PRIOR ((reg8 *) SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG)
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/* Priority of the SCSI_TX_DMA_COMPLETE interrupt. */
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#define SCSI_TX_DMA_COMPLETE_INTC_PRIOR_NUMBER SCSI_TX_DMA_COMPLETE__INTC_PRIOR_NUM
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/* Address of the INTC.SET_EN[x] byte to bit enable SCSI_TX_DMA_COMPLETE interrupt. */
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#define SCSI_TX_DMA_COMPLETE_INTC_SET_EN ((reg32 *) SCSI_TX_DMA_COMPLETE__INTC_SET_EN_REG)
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/* Address of the INTC.CLR_EN[x] register to bit clear the SCSI_TX_DMA_COMPLETE interrupt. */
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#define SCSI_TX_DMA_COMPLETE_INTC_CLR_EN ((reg32 *) SCSI_TX_DMA_COMPLETE__INTC_CLR_EN_REG)
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/* Address of the INTC.SET_PD[x] register to set the SCSI_TX_DMA_COMPLETE interrupt state to pending. */
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#define SCSI_TX_DMA_COMPLETE_INTC_SET_PD ((reg32 *) SCSI_TX_DMA_COMPLETE__INTC_SET_PD_REG)
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/* Address of the INTC.CLR_PD[x] register to clear the SCSI_TX_DMA_COMPLETE interrupt. */
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#define SCSI_TX_DMA_COMPLETE_INTC_CLR_PD ((reg32 *) SCSI_TX_DMA_COMPLETE__INTC_CLR_PD_REG)
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#endif /* CY_ISR_SCSI_TX_DMA_COMPLETE_H */
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/* [] END OF FILE */
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