165 lines
4.1 KiB
Plaintext
165 lines
4.1 KiB
Plaintext
# This is the template file for creating symbols with tragesym
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# every line starting with '#' is a comment line.
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[options]
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# wordswap swaps labels if the pin is on the right side an looks like this:
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# "PB1 (CLK)". That's useful for micro controller port labels
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# rotate_labels rotates the pintext of top and bottom pins
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# this is useful for large symbols like FPGAs with more than 100 pins
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# sort_labels will sort the pins by it's labels
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# useful for address ports, busses, ...
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wordswap=yes
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rotate_labels=yes
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sort_labels=no
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generate_pinseq=yes
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sym_width=18000
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pinwidthvertical=700
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pinwidthhorizontal=700
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[geda_attr]
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# name will be printed in the top of the symbol
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# name is only some graphical text, not an attribute
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# version specifies a gschem version.
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# if you have a device with slots, you'll have to use slot= and slotdef=
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# use comment= if there are special information you want to add
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version=20060113 1
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name=CY8C53
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device=CY8C53
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refdes=U?
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footprint=TQFP100_14
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description=Cypress PSoC5 CY8C53
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documentation=http://www.cypress.com/?id=2233
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author=Michael McMaster <michael@codesrc.com>
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dist-license=gpl3+
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use-license=gpl3+
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numslots=0
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#slot=1
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#slotdef=1:
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#slotdef=2:
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#slotdef=3:
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#slotdef=4:
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#comment=
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#comment=
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#comment=
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[pins]
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# tabseparated list of pin descriptions
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# ----------------------------------------
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# pinnr is the physical number of the pin
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# seq is the pinseq= attribute, leave it blank if it doesn't matter
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# type can be (in, out, io, oc, oe, pas, tp, tri, clk, pwr)
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# style can be (line,dot,clk,dotclk,spacer,none). none if only want to add a net
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# posit. can be (l,r,t,b) or empty for nets.
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# net specifies the name of the net. Vcc or GND for example.
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# label represents the pinlabel.
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# negation lines can be added with "\_" example: \_enable\_
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# if you want to write a "\" use "\\" as escape sequence
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#-----------------------------------------------------
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#pinnr seq type style posit. net label
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#-----------------------------------------------------
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1 io line l P2[5]
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2 io line l P2[6]
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3 io line l P2[7]
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4 io line l P12[4]
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5 io line l P12[5]
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6 io line l P6[4]
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7 io line l P6[5]
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8 io line l P6[6]
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9 io line l P6[7]
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10 pwr line l GND VSSD
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11 io line l NC
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12 pwr line l GND VSSD
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13 pwr line l GND VSSD
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14 pwr line l GND VSSD
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15 in line l \_XRES\_
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16 io line l P5[0]
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17 io line l P5[1]
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18 io line l P5[2]
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19 io line l P5[3]
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20 io line l SWDIO,P1[0]
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21 io line l SWDCK,P1[1]
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22 io line l P1[2]
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23 io line l SWV,P1[3]
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24 io line l P1[4]
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25 io line l P1[5]
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26 pwr line b VDDIO1
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27 io line b P1[6]
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28 io line b P1[7]
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29 io line b P12[6]
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30 io line b P12[7]
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31 io line b P5[4]
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32 io line b P5[5]
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33 io line b P5[6]
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34 io line b P5[7]
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35 io line b SWDIO,USB D+
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36 io line b SWDCK,USB D-
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37 pwr line b VDDD
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38 pwr line b GND VSSD
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39 pwr line b VCCD
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40 io line b NC
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41 io line b NC
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42 clk clk b MHZ XTAL XO
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43 clk clk b MHZ XTAL XI
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44 io line b P3[0]
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45 io line b P3[1]
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46 io line b P3[2]
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47 io line b P3[3]
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48 io line b P3[4]
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49 io line b P3[5]
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50 pwr line b VDDIO3
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75 pwr line r VDDIO0
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74 io line r P0[3]
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73 io line r P0[2]
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72 io line r P0[1]
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71 io line r P0[0]
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70 io line r P4[1]
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69 io line r P4[0]
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68 io line r P12[3]
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67 io line r P12[2]
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66 pwr line r GND VSSD
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65 pwr line r VDDA
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64 pwr line r GND VSSA
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63 pwr line r VCCA
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62 io line r NC
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61 io line r NC
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60 io line r NC
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59 io line r NC
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58 io line r NC
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57 io line r NC
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56 io line r P15[3],KHZ XTAL XI
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55 io line r P15[2],KHZ XTAL XO
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54 io line r P12[1]
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53 io line r P12[0]
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52 io line r P3[7]
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51 io line r P3[6]
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100 pwr line t VDDIO2
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99 io line t P2[4]
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98 io line t P2[3]
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97 io line t P2[2]
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96 io line t P2[1]
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95 io line t P2[0]
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94 io line t P15[5]
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93 io line t P15[4]
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92 io line t P6[3]
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91 io line t P6[2]
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90 io line t P6[1]
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89 io line t P6[0]
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88 pwr line t VDDD
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87 pwr line t GND VSSD
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86 pwr line t VCCD
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85 io line t P4[7]
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84 io line t P4[6]
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83 io line t P4[5]
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82 io line t P4[4]
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81 io line t P4[3]
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80 io line t P4[2]
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79 io line t P0[7]
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78 io line t P0[6]
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77 io line t P0[5]
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76 io line t P0[4]
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