160 lines
6.7 KiB
C
160 lines
6.7 KiB
C
/*******************************************************************************
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* File Name: CySpc.c
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* Version 3.40
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*
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* Description:
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* Provides definitions for the System Performance Component API.
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* The SPC functions are not meant to be called directly by the user
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* application.
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*
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********************************************************************************
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* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.
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* You may use this file only in accordance with the license, terms, conditions,
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* disclaimers, and limitations in the end user license agreement accompanying
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* the software package with which this file was provided.
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*******************************************************************************/
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#if !defined(CY_BOOT_CYSPC_H)
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#define CY_BOOT_CYSPC_H
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#include "cytypes.h"
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#include "CyLib.h"
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#include "cydevice_trm.h"
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/***************************************
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* Global Variables
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***************************************/
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extern uint8 SpcLockState;
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/***************************************
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* Function Prototypes
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***************************************/
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void CySpcStart(void);
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void CySpcStop(void);
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uint8 CySpcReadData(uint8 buffer[], uint8 size);
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cystatus CySpcLoadMultiByte(uint8 array, uint16 address, const uint8 buffer[], uint8 size) ;
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cystatus CySpcLoadRow(uint8 array, const uint8 buffer[], uint16 size);
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cystatus CySpcWriteRow(uint8 array, uint16 address, uint8 tempPolarity, uint8 tempMagnitude) ;
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cystatus CySpcEraseSector(uint8 array, uint8 sectorNumber);
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#if(CY_PSOC5A)
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cystatus CySpcGetTemp(uint8 numSamples, uint16 timerPeriod, uint8 clkDivSelect);
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#else
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cystatus CySpcGetTemp(uint8 numSamples);
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#endif /* (CY_PSOC5A) */
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cystatus CySpcLock(void);
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void CySpcUnlock(void);
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/***************************************
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* API Constants
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***************************************/
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#define CY_SPC_LOCKED (0x01u)
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#define CY_SPC_UNLOCKED (0x00u)
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/*******************************************************************************
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* The Array ID indicates the unique ID of the SONOS array being accessed:
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* - 0x00-0x3E : Flash Arrays
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* - 0x3F : Selects all Flash arrays simultaneously
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* - 0x40-0x7F : Embedded EEPROM Arrays
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*******************************************************************************/
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#define CY_SPC_FIRST_FLASH_ARRAYID (0x00u)
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#define CY_SPC_LAST_FLASH_ARRAYID (0x3Fu)
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#define CY_SPC_FIRST_EE_ARRAYID (0x40u)
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#define CY_SPC_LAST_EE_ARRAYID (0x7Fu)
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#define CY_SPC_STATUS_DATA_READY_MASK (0x01u)
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#define CY_SPC_STATUS_IDLE_MASK (0x02u)
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#define CY_SPC_STATUS_CODE_MASK (0xFCu)
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#define CY_SPC_STATUS_CODE_SHIFT (0x02u)
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/* Status codes for the SPC. */
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#define CY_SPC_STATUS_SUCCESS (0x00u) /* Operation Successful */
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#define CY_SPC_STATUS_INVALID_ARRAY_ID (0x01u) /* Invalid Array ID for given command */
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#define CY_SPC_STATUS_INVALID_2BYTEKEY (0x02u) /* Invalid 2-byte key */
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#define CY_SPC_STATUS_ARRAY_ASLEEP (0x03u) /* Addressed Array is Asleep */
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#define CY_SPC_STATUS_EXTERN_ACCESS (0x04u) /* External Access Failure (SPC is not in external access mode) */
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#define CY_SPC_STATUS_INVALID_NUMBER (0x05u) /* Invalid 'N' Value for given command */
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#define CY_SPC_STATUS_TEST_MODE (0x06u) /* Test Mode Failure (SPC is not in test mode) */
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#define CY_SPC_STATUS_ALG_CSUM (0x07u) /* Smart Write Algorithm Checksum Failure */
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#define CY_SPC_STATUS_PARAM_CSUM (0x08u) /* Smart Write Parameter Checksum Failure */
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#define CY_SPC_STATUS_PROTECTION (0x09u) /* Protection Check Failure */
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#define CY_SPC_STATUS_ADDRESS_PARAM (0x0Au) /* Invalid Address parameter for the given command */
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#define CY_SPC_STATUS_COMMAND_CODE (0x0Bu) /* Invalid Command Code */
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#define CY_SPC_STATUS_ROW_ID (0x0Cu) /* Invalid Row ID parameter for given command */
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#define CY_SPC_STATUS_TADC_INPUT (0x0Du) /* Invalid input value for Get Temp & Get ADC commands */
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#define CY_SPC_STATUS_BUSY (0xFFu) /* SPC is busy */
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#if(CY_PSOC5LP)
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/* Wait-state pipeline */
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#define CY_SPC_CPU_WAITPIPE_BYPASS ((uint32)0x01u)
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#endif /* (CY_PSOC5LP) */
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/***************************************
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* Registers
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***************************************/
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/* SPC CPU Data Register */
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#define CY_SPC_CPU_DATA_REG (* (reg8 *) CYREG_SPC_CPU_DATA )
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#define CY_SPC_CPU_DATA_PTR ( (reg8 *) CYREG_SPC_CPU_DATA )
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/* SPC Status Register */
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#define CY_SPC_STATUS_REG (* (reg8 *) CYREG_SPC_SR )
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#define CY_SPC_STATUS_PTR ( (reg8 *) CYREG_SPC_SR )
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/* Active Power Mode Configuration Register 0 */
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#define CY_SPC_PM_ACT_REG (* (reg8 *) CYREG_PM_ACT_CFG0 )
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#define CY_SPC_PM_ACT_PTR ( (reg8 *) CYREG_PM_ACT_CFG0 )
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/* Standby Power Mode Configuration Register 0 */
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#define CY_SPC_PM_STBY_REG (* (reg8 *) CYREG_PM_STBY_CFG0 )
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#define CY_SPC_PM_STBY_PTR ( (reg8 *) CYREG_PM_STBY_CFG0 )
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#if(CY_PSOC5LP)
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/* Wait State Pipeline */
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#define CY_SPC_CPU_WAITPIPE_REG (* (reg32 *) CYREG_PANTHER_WAITPIPE )
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#define CY_SPC_CPU_WAITPIPE_PTR ( (reg32 *) CYREG_PANTHER_WAITPIPE )
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#endif /* (CY_PSOC5LP) */
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/***************************************
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* Macros
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***************************************/
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#define CY_SPC_IDLE (0u != (CY_SPC_STATUS_REG & CY_SPC_STATUS_IDLE_MASK))
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#define CY_SPC_BUSY (0u == (CY_SPC_STATUS_REG & CY_SPC_STATUS_IDLE_MASK))
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#define CY_SPC_DATA_READY (0u != (CY_SPC_STATUS_REG & CY_SPC_STATUS_DATA_READY_MASK))
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/* SPC must be in idle state in order to obtain correct status */
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#define CY_SPC_READ_STATUS (CY_SPC_IDLE ? \
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((uint8)(CY_SPC_STATUS_REG >> CY_SPC_STATUS_CODE_SHIFT)) : \
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((uint8) CY_SPC_STATUS_BUSY))
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/*******************************************************************************
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* Following code are OBSOLETE and must not be used starting from cy_boot 3.0
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*******************************************************************************/
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#define FIRST_FLASH_ARRAYID (CY_SPC_FIRST_FLASH_ARRAYID)
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#define LAST_FLASH_ARRAYID (CY_SPC_LAST_FLASH_ARRAYID)
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#define FIRST_EE_ARRAYID (CY_SPC_FIRST_EE_ARRAYID)
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#define LAST_EE_ARRAYID (CY_SPC_LAST_EE_ARRAYID)
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#define SIZEOF_ECC_ROW (CYDEV_ECC_ROW_SIZE)
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#define SIZEOF_FLASH_ROW (CYDEV_FLS_ROW_SIZE)
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#define SIZEOF_EEPROM_ROW (CYDEV_EEPROM_ROW_SIZE)
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#endif /* (CY_BOOT_CYSPC_H) */
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/* [] END OF FILE */
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