131 lines
5.2 KiB
C
131 lines
5.2 KiB
C
/*******************************************************************************
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* File Name: PARITY_EN.h
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* Version 1.90
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*
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* Description:
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* This file containts Control Register function prototypes and register defines
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*
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* Note:
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*
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********************************************************************************
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* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
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* You may use this file only in accordance with the license, terms, conditions,
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* disclaimers, and limitations in the end user license agreement accompanying
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* the software package with which this file was provided.
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*******************************************************************************/
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#if !defined(CY_PINS_PARITY_EN_H) /* Pins PARITY_EN_H */
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#define CY_PINS_PARITY_EN_H
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#include "cytypes.h"
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#include "cyfitter.h"
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#include "cypins.h"
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#include "PARITY_EN_aliases.h"
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/* Check to see if required defines such as CY_PSOC5A are available */
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/* They are defined starting with cy_boot v3.0 */
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#if !defined (CY_PSOC5A)
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#error Component cy_pins_v1_90 requires cy_boot v3.0 or later
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#endif /* (CY_PSOC5A) */
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/* APIs are not generated for P15[7:6] */
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#if !(CY_PSOC5A &&\
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PARITY_EN__PORT == 15 && ((PARITY_EN__MASK & 0xC0) != 0))
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/***************************************
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* Function Prototypes
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***************************************/
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void PARITY_EN_Write(uint8 value) ;
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void PARITY_EN_SetDriveMode(uint8 mode) ;
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uint8 PARITY_EN_ReadDataReg(void) ;
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uint8 PARITY_EN_Read(void) ;
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uint8 PARITY_EN_ClearInterrupt(void) ;
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/***************************************
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* API Constants
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***************************************/
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/* Drive Modes */
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#define PARITY_EN_DM_ALG_HIZ PIN_DM_ALG_HIZ
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#define PARITY_EN_DM_DIG_HIZ PIN_DM_DIG_HIZ
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#define PARITY_EN_DM_RES_UP PIN_DM_RES_UP
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#define PARITY_EN_DM_RES_DWN PIN_DM_RES_DWN
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#define PARITY_EN_DM_OD_LO PIN_DM_OD_LO
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#define PARITY_EN_DM_OD_HI PIN_DM_OD_HI
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#define PARITY_EN_DM_STRONG PIN_DM_STRONG
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#define PARITY_EN_DM_RES_UPDWN PIN_DM_RES_UPDWN
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/* Digital Port Constants */
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#define PARITY_EN_MASK PARITY_EN__MASK
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#define PARITY_EN_SHIFT PARITY_EN__SHIFT
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#define PARITY_EN_WIDTH 1u
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/***************************************
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* Registers
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***************************************/
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/* Main Port Registers */
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/* Pin State */
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#define PARITY_EN_PS (* (reg8 *) PARITY_EN__PS)
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/* Data Register */
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#define PARITY_EN_DR (* (reg8 *) PARITY_EN__DR)
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/* Port Number */
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#define PARITY_EN_PRT_NUM (* (reg8 *) PARITY_EN__PRT)
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/* Connect to Analog Globals */
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#define PARITY_EN_AG (* (reg8 *) PARITY_EN__AG)
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/* Analog MUX bux enable */
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#define PARITY_EN_AMUX (* (reg8 *) PARITY_EN__AMUX)
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/* Bidirectional Enable */
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#define PARITY_EN_BIE (* (reg8 *) PARITY_EN__BIE)
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/* Bit-mask for Aliased Register Access */
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#define PARITY_EN_BIT_MASK (* (reg8 *) PARITY_EN__BIT_MASK)
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/* Bypass Enable */
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#define PARITY_EN_BYP (* (reg8 *) PARITY_EN__BYP)
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/* Port wide control signals */
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#define PARITY_EN_CTL (* (reg8 *) PARITY_EN__CTL)
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/* Drive Modes */
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#define PARITY_EN_DM0 (* (reg8 *) PARITY_EN__DM0)
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#define PARITY_EN_DM1 (* (reg8 *) PARITY_EN__DM1)
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#define PARITY_EN_DM2 (* (reg8 *) PARITY_EN__DM2)
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/* Input Buffer Disable Override */
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#define PARITY_EN_INP_DIS (* (reg8 *) PARITY_EN__INP_DIS)
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/* LCD Common or Segment Drive */
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#define PARITY_EN_LCD_COM_SEG (* (reg8 *) PARITY_EN__LCD_COM_SEG)
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/* Enable Segment LCD */
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#define PARITY_EN_LCD_EN (* (reg8 *) PARITY_EN__LCD_EN)
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/* Slew Rate Control */
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#define PARITY_EN_SLW (* (reg8 *) PARITY_EN__SLW)
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/* DSI Port Registers */
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/* Global DSI Select Register */
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#define PARITY_EN_PRTDSI__CAPS_SEL (* (reg8 *) PARITY_EN__PRTDSI__CAPS_SEL)
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/* Double Sync Enable */
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#define PARITY_EN_PRTDSI__DBL_SYNC_IN (* (reg8 *) PARITY_EN__PRTDSI__DBL_SYNC_IN)
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/* Output Enable Select Drive Strength */
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#define PARITY_EN_PRTDSI__OE_SEL0 (* (reg8 *) PARITY_EN__PRTDSI__OE_SEL0)
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#define PARITY_EN_PRTDSI__OE_SEL1 (* (reg8 *) PARITY_EN__PRTDSI__OE_SEL1)
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/* Port Pin Output Select Registers */
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#define PARITY_EN_PRTDSI__OUT_SEL0 (* (reg8 *) PARITY_EN__PRTDSI__OUT_SEL0)
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#define PARITY_EN_PRTDSI__OUT_SEL1 (* (reg8 *) PARITY_EN__PRTDSI__OUT_SEL1)
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/* Sync Output Enable Registers */
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#define PARITY_EN_PRTDSI__SYNC_OUT (* (reg8 *) PARITY_EN__PRTDSI__SYNC_OUT)
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#if defined(PARITY_EN__INTSTAT) /* Interrupt Registers */
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#define PARITY_EN_INTSTAT (* (reg8 *) PARITY_EN__INTSTAT)
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#define PARITY_EN_SNAP (* (reg8 *) PARITY_EN__SNAP)
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#endif /* Interrupt Registers */
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#endif /* CY_PSOC5A... */
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#endif /* CY_PINS_PARITY_EN_H */
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/* [] END OF FILE */
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