390 lines
16 KiB
C
390 lines
16 KiB
C
/*******************************************************************************
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* File Name: SD.h
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* Version 2.40
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*
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* Description:
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* Contains the function prototypes, constants and register definition
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* of the SPI Master Component.
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*
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* Note:
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* None
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*
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********************************************************************************
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* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
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* You may use this file only in accordance with the license, terms, conditions,
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* disclaimers, and limitations in the end user license agreement accompanying
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* the software package with which this file was provided.
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*******************************************************************************/
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#if !defined(CY_SPIM_SD_H)
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#define CY_SPIM_SD_H
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#include "cytypes.h"
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#include "cyfitter.h"
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#include "CyLib.h"
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/* Check to see if required defines such as CY_PSOC5A are available */
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/* They are defined starting with cy_boot v3.0 */
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#if !defined (CY_PSOC5A)
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#error Component SPI_Master_v2_40 requires cy_boot v3.0 or later
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#endif /* (CY_PSOC5A) */
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/***************************************
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* Conditional Compilation Parameters
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***************************************/
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#define SD_INTERNAL_CLOCK (0u)
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#if(0u != SD_INTERNAL_CLOCK)
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#include "SD_IntClock.h"
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#endif /* (0u != SD_INTERNAL_CLOCK) */
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#define SD_MODE (1u)
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#define SD_DATA_WIDTH (8u)
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#define SD_MODE_USE_ZERO (1u)
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#define SD_BIDIRECTIONAL_MODE (0u)
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/* Internal interrupt handling */
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#define SD_TX_BUFFER_SIZE (4u)
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#define SD_RX_BUFFER_SIZE (4u)
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#define SD_INTERNAL_TX_INT_ENABLED (0u)
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#define SD_INTERNAL_RX_INT_ENABLED (0u)
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#define SD_SINGLE_REG_SIZE (8u)
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#define SD_USE_SECOND_DATAPATH (SD_DATA_WIDTH > SD_SINGLE_REG_SIZE)
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#define SD_FIFO_SIZE (4u)
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#define SD_TX_SOFTWARE_BUF_ENABLED ((0u != SD_INTERNAL_TX_INT_ENABLED) && \
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(SD_TX_BUFFER_SIZE > SD_FIFO_SIZE))
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#define SD_RX_SOFTWARE_BUF_ENABLED ((0u != SD_INTERNAL_RX_INT_ENABLED) && \
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(SD_RX_BUFFER_SIZE > SD_FIFO_SIZE))
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/***************************************
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* Data Struct Definition
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***************************************/
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/* Sleep Mode API Support */
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typedef struct
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{
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uint8 enableState;
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uint8 cntrPeriod;
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#if(CY_UDB_V0)
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uint8 saveSrTxIntMask;
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uint8 saveSrRxIntMask;
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#endif /* (CY_UDB_V0) */
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} SD_BACKUP_STRUCT;
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/***************************************
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* Function Prototypes
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***************************************/
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void SD_Init(void) ;
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void SD_Enable(void) ;
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void SD_Start(void) ;
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void SD_Stop(void) ;
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void SD_EnableTxInt(void) ;
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void SD_EnableRxInt(void) ;
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void SD_DisableTxInt(void) ;
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void SD_DisableRxInt(void) ;
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void SD_Sleep(void) ;
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void SD_Wakeup(void) ;
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void SD_SaveConfig(void) ;
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void SD_RestoreConfig(void) ;
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void SD_SetTxInterruptMode(uint8 intSrc) ;
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void SD_SetRxInterruptMode(uint8 intSrc) ;
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uint8 SD_ReadTxStatus(void) ;
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uint8 SD_ReadRxStatus(void) ;
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void SD_WriteTxData(uint8 txData) \
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;
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uint8 SD_ReadRxData(void) \
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;
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uint8 SD_GetRxBufferSize(void) ;
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uint8 SD_GetTxBufferSize(void) ;
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void SD_ClearRxBuffer(void) ;
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void SD_ClearTxBuffer(void) ;
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void SD_ClearFIFO(void) ;
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void SD_PutArray(const uint8 buffer[], uint8 byteCount) \
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;
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#if(0u != SD_BIDIRECTIONAL_MODE)
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void SD_TxEnable(void) ;
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void SD_TxDisable(void) ;
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#endif /* (0u != SD_BIDIRECTIONAL_MODE) */
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CY_ISR_PROTO(SD_TX_ISR);
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CY_ISR_PROTO(SD_RX_ISR);
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/**********************************
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* Variable with external linkage
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**********************************/
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extern uint8 SD_initVar;
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/***************************************
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* API Constants
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***************************************/
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#define SD_TX_ISR_NUMBER ((uint8) (SD_TxInternalInterrupt__INTC_NUMBER))
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#define SD_RX_ISR_NUMBER ((uint8) (SD_RxInternalInterrupt__INTC_NUMBER))
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#define SD_TX_ISR_PRIORITY ((uint8) (SD_TxInternalInterrupt__INTC_PRIOR_NUM))
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#define SD_RX_ISR_PRIORITY ((uint8) (SD_RxInternalInterrupt__INTC_PRIOR_NUM))
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/***************************************
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* Initial Parameter Constants
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***************************************/
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#define SD_INT_ON_SPI_DONE ((uint8) (0u << SD_STS_SPI_DONE_SHIFT))
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#define SD_INT_ON_TX_EMPTY ((uint8) (0u << SD_STS_TX_FIFO_EMPTY_SHIFT))
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#define SD_INT_ON_TX_NOT_FULL ((uint8) (0u << \
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SD_STS_TX_FIFO_NOT_FULL_SHIFT))
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#define SD_INT_ON_BYTE_COMP ((uint8) (0u << SD_STS_BYTE_COMPLETE_SHIFT))
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#define SD_INT_ON_SPI_IDLE ((uint8) (0u << SD_STS_SPI_IDLE_SHIFT))
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/* Disable TX_NOT_FULL if software buffer is used */
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#define SD_INT_ON_TX_NOT_FULL_DEF ((SD_TX_SOFTWARE_BUF_ENABLED) ? \
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(0u) : (SD_INT_ON_TX_NOT_FULL))
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/* TX interrupt mask */
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#define SD_TX_INIT_INTERRUPTS_MASK (SD_INT_ON_SPI_DONE | \
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SD_INT_ON_TX_EMPTY | \
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SD_INT_ON_TX_NOT_FULL_DEF | \
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SD_INT_ON_BYTE_COMP | \
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SD_INT_ON_SPI_IDLE)
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#define SD_INT_ON_RX_FULL ((uint8) (0u << \
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SD_STS_RX_FIFO_FULL_SHIFT))
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#define SD_INT_ON_RX_NOT_EMPTY ((uint8) (0u << \
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SD_STS_RX_FIFO_NOT_EMPTY_SHIFT))
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#define SD_INT_ON_RX_OVER ((uint8) (0u << \
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SD_STS_RX_FIFO_OVERRUN_SHIFT))
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/* RX interrupt mask */
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#define SD_RX_INIT_INTERRUPTS_MASK (SD_INT_ON_RX_FULL | \
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SD_INT_ON_RX_NOT_EMPTY | \
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SD_INT_ON_RX_OVER)
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/* Nubmer of bits to receive/transmit */
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#define SD_BITCTR_INIT (((uint8) (SD_DATA_WIDTH << 1u)) - 1u)
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/***************************************
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* Registers
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***************************************/
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#if(CY_PSOC3 || CY_PSOC5)
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#define SD_TXDATA_REG (* (reg8 *) \
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SD_BSPIM_sR8_Dp_u0__F0_REG)
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#define SD_TXDATA_PTR ( (reg8 *) \
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SD_BSPIM_sR8_Dp_u0__F0_REG)
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#define SD_RXDATA_REG (* (reg8 *) \
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SD_BSPIM_sR8_Dp_u0__F1_REG)
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#define SD_RXDATA_PTR ( (reg8 *) \
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SD_BSPIM_sR8_Dp_u0__F1_REG)
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#else /* PSOC4 */
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#if(SD_USE_SECOND_DATAPATH)
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#define SD_TXDATA_REG (* (reg16 *) \
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SD_BSPIM_sR8_Dp_u0__16BIT_F0_REG)
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#define SD_TXDATA_PTR ( (reg16 *) \
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SD_BSPIM_sR8_Dp_u0__16BIT_F0_REG)
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#define SD_RXDATA_REG (* (reg16 *) \
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SD_BSPIM_sR8_Dp_u0__16BIT_F1_REG)
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#define SD_RXDATA_PTR ( (reg16 *) \
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SD_BSPIM_sR8_Dp_u0__16BIT_F1_REG)
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#else
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#define SD_TXDATA_REG (* (reg8 *) \
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SD_BSPIM_sR8_Dp_u0__F0_REG)
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#define SD_TXDATA_PTR ( (reg8 *) \
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SD_BSPIM_sR8_Dp_u0__F0_REG)
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#define SD_RXDATA_REG (* (reg8 *) \
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SD_BSPIM_sR8_Dp_u0__F1_REG)
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#define SD_RXDATA_PTR ( (reg8 *) \
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SD_BSPIM_sR8_Dp_u0__F1_REG)
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#endif /* (SD_USE_SECOND_DATAPATH) */
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#endif /* (CY_PSOC3 || CY_PSOC5) */
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#define SD_AUX_CONTROL_DP0_REG (* (reg8 *) \
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SD_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG)
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#define SD_AUX_CONTROL_DP0_PTR ( (reg8 *) \
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SD_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG)
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#if(SD_USE_SECOND_DATAPATH)
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#define SD_AUX_CONTROL_DP1_REG (* (reg8 *) \
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SD_BSPIM_sR8_Dp_u1__DP_AUX_CTL_REG)
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#define SD_AUX_CONTROL_DP1_PTR ( (reg8 *) \
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SD_BSPIM_sR8_Dp_u1__DP_AUX_CTL_REG)
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#endif /* (SD_USE_SECOND_DATAPATH) */
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#define SD_COUNTER_PERIOD_REG (* (reg8 *) SD_BSPIM_BitCounter__PERIOD_REG)
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#define SD_COUNTER_PERIOD_PTR ( (reg8 *) SD_BSPIM_BitCounter__PERIOD_REG)
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#define SD_COUNTER_CONTROL_REG (* (reg8 *) SD_BSPIM_BitCounter__CONTROL_AUX_CTL_REG)
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#define SD_COUNTER_CONTROL_PTR ( (reg8 *) SD_BSPIM_BitCounter__CONTROL_AUX_CTL_REG)
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#define SD_TX_STATUS_REG (* (reg8 *) SD_BSPIM_TxStsReg__STATUS_REG)
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#define SD_TX_STATUS_PTR ( (reg8 *) SD_BSPIM_TxStsReg__STATUS_REG)
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#define SD_RX_STATUS_REG (* (reg8 *) SD_BSPIM_RxStsReg__STATUS_REG)
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#define SD_RX_STATUS_PTR ( (reg8 *) SD_BSPIM_RxStsReg__STATUS_REG)
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#define SD_CONTROL_REG (* (reg8 *) \
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SD_BSPIM_BidirMode_SyncCtl_CtrlReg__CONTROL_REG)
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#define SD_CONTROL_PTR ( (reg8 *) \
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SD_BSPIM_BidirMode_SyncCtl_CtrlReg__CONTROL_REG)
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#define SD_TX_STATUS_MASK_REG (* (reg8 *) SD_BSPIM_TxStsReg__MASK_REG)
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#define SD_TX_STATUS_MASK_PTR ( (reg8 *) SD_BSPIM_TxStsReg__MASK_REG)
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#define SD_RX_STATUS_MASK_REG (* (reg8 *) SD_BSPIM_RxStsReg__MASK_REG)
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#define SD_RX_STATUS_MASK_PTR ( (reg8 *) SD_BSPIM_RxStsReg__MASK_REG)
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#define SD_TX_STATUS_ACTL_REG (* (reg8 *) SD_BSPIM_TxStsReg__STATUS_AUX_CTL_REG)
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#define SD_TX_STATUS_ACTL_PTR ( (reg8 *) SD_BSPIM_TxStsReg__STATUS_AUX_CTL_REG)
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#define SD_RX_STATUS_ACTL_REG (* (reg8 *) SD_BSPIM_RxStsReg__STATUS_AUX_CTL_REG)
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#define SD_RX_STATUS_ACTL_PTR ( (reg8 *) SD_BSPIM_RxStsReg__STATUS_AUX_CTL_REG)
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#if(SD_USE_SECOND_DATAPATH)
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#define SD_AUX_CONTROLDP1 (SD_AUX_CONTROL_DP1_REG)
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#endif /* (SD_USE_SECOND_DATAPATH) */
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/***************************************
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* Register Constants
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***************************************/
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/* Status Register Definitions */
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#define SD_STS_SPI_DONE_SHIFT (0x00u)
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#define SD_STS_TX_FIFO_EMPTY_SHIFT (0x01u)
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#define SD_STS_TX_FIFO_NOT_FULL_SHIFT (0x02u)
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#define SD_STS_BYTE_COMPLETE_SHIFT (0x03u)
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#define SD_STS_SPI_IDLE_SHIFT (0x04u)
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#define SD_STS_RX_FIFO_FULL_SHIFT (0x04u)
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#define SD_STS_RX_FIFO_NOT_EMPTY_SHIFT (0x05u)
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#define SD_STS_RX_FIFO_OVERRUN_SHIFT (0x06u)
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#define SD_STS_SPI_DONE ((uint8) (0x01u << SD_STS_SPI_DONE_SHIFT))
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#define SD_STS_TX_FIFO_EMPTY ((uint8) (0x01u << SD_STS_TX_FIFO_EMPTY_SHIFT))
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#define SD_STS_TX_FIFO_NOT_FULL ((uint8) (0x01u << SD_STS_TX_FIFO_NOT_FULL_SHIFT))
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#define SD_STS_BYTE_COMPLETE ((uint8) (0x01u << SD_STS_BYTE_COMPLETE_SHIFT))
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#define SD_STS_SPI_IDLE ((uint8) (0x01u << SD_STS_SPI_IDLE_SHIFT))
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#define SD_STS_RX_FIFO_FULL ((uint8) (0x01u << SD_STS_RX_FIFO_FULL_SHIFT))
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#define SD_STS_RX_FIFO_NOT_EMPTY ((uint8) (0x01u << SD_STS_RX_FIFO_NOT_EMPTY_SHIFT))
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#define SD_STS_RX_FIFO_OVERRUN ((uint8) (0x01u << SD_STS_RX_FIFO_OVERRUN_SHIFT))
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/* TX and RX masks for clear on read bits */
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#define SD_TX_STS_CLR_ON_RD_BYTES_MASK (0x09u)
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#define SD_RX_STS_CLR_ON_RD_BYTES_MASK (0x40u)
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/* StatusI Register Interrupt Enable Control Bits */
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/* As defined by the Register map for the AUX Control Register */
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#define SD_INT_ENABLE (0x10u) /* Enable interrupt from statusi */
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#define SD_TX_FIFO_CLR (0x01u) /* F0 - TX FIFO */
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#define SD_RX_FIFO_CLR (0x02u) /* F1 - RX FIFO */
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#define SD_FIFO_CLR (SD_TX_FIFO_CLR | SD_RX_FIFO_CLR)
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/* Bit Counter (7-bit) Control Register Bit Definitions */
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/* As defined by the Register map for the AUX Control Register */
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#define SD_CNTR_ENABLE (0x20u) /* Enable CNT7 */
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/* Bi-Directional mode control bit */
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#define SD_CTRL_TX_SIGNAL_EN (0x01u)
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/* Datapath Auxillary Control Register definitions */
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#define SD_AUX_CTRL_FIFO0_CLR (0x01u)
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#define SD_AUX_CTRL_FIFO1_CLR (0x02u)
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#define SD_AUX_CTRL_FIFO0_LVL (0x04u)
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#define SD_AUX_CTRL_FIFO1_LVL (0x08u)
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#define SD_STATUS_ACTL_INT_EN_MASK (0x10u)
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/* Component disabled */
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#define SD_DISABLED (0u)
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/***************************************
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* Macros
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***************************************/
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/* Returns true if componentn enabled */
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#define SD_IS_ENABLED (0u != (SD_TX_STATUS_ACTL_REG & SD_INT_ENABLE))
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/* Retuns TX status register */
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#define SD_GET_STATUS_TX(swTxSts) ( (uint8)(SD_TX_STATUS_REG | \
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((swTxSts) & SD_TX_STS_CLR_ON_RD_BYTES_MASK)) )
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/* Retuns RX status register */
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#define SD_GET_STATUS_RX(swRxSts) ( (uint8)(SD_RX_STATUS_REG | \
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((swRxSts) & SD_RX_STS_CLR_ON_RD_BYTES_MASK)) )
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/***************************************
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* Obsolete definitions
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***************************************/
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/* Following definitions are for version compatibility.
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* They are obsolete in SPIM v2_30.
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* Please do not use it in new projects
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*/
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#define SD_WriteByte SD_WriteTxData
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#define SD_ReadByte SD_ReadRxData
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void SD_SetInterruptMode(uint8 intSrc) ;
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uint8 SD_ReadStatus(void) ;
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void SD_EnableInt(void) ;
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void SD_DisableInt(void) ;
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/* Obsolete register names. Not to be used in new designs */
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#define SD_TXDATA (SD_TXDATA_REG)
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#define SD_RXDATA (SD_RXDATA_REG)
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#define SD_AUX_CONTROLDP0 (SD_AUX_CONTROL_DP0_REG)
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#define SD_TXBUFFERREAD (SD_txBufferRead)
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#define SD_TXBUFFERWRITE (SD_txBufferWrite)
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#define SD_RXBUFFERREAD (SD_rxBufferRead)
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#define SD_RXBUFFERWRITE (SD_rxBufferWrite)
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#define SD_COUNTER_PERIOD (SD_COUNTER_PERIOD_REG)
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#define SD_COUNTER_CONTROL (SD_COUNTER_CONTROL_REG)
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#define SD_STATUS (SD_TX_STATUS_REG)
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#define SD_CONTROL (SD_CONTROL_REG)
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#define SD_STATUS_MASK (SD_TX_STATUS_MASK_REG)
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#define SD_STATUS_ACTL (SD_TX_STATUS_ACTL_REG)
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#define SD_INIT_INTERRUPTS_MASK (SD_INT_ON_SPI_DONE | \
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SD_INT_ON_TX_EMPTY | \
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SD_INT_ON_TX_NOT_FULL_DEF | \
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SD_INT_ON_RX_FULL | \
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SD_INT_ON_RX_NOT_EMPTY | \
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SD_INT_ON_RX_OVER | \
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SD_INT_ON_BYTE_COMP)
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/* Following definitions are for version Compatibility.
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* They are obsolete in SPIM v2_40.
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* Please do not use it in new projects
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*/
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#define SD_DataWidth (SD_DATA_WIDTH)
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#define SD_InternalClockUsed (SD_INTERNAL_CLOCK)
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#define SD_InternalTxInterruptEnabled (SD_INTERNAL_TX_INT_ENABLED)
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#define SD_InternalRxInterruptEnabled (SD_INTERNAL_RX_INT_ENABLED)
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#define SD_ModeUseZero (SD_MODE_USE_ZERO)
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#define SD_BidirectionalMode (SD_BIDIRECTIONAL_MODE)
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#define SD_Mode (SD_MODE)
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#define SD_DATAWIDHT (SD_DATA_WIDTH)
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#define SD_InternalInterruptEnabled (0u)
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#define SD_TXBUFFERSIZE (SD_TX_BUFFER_SIZE)
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#define SD_RXBUFFERSIZE (SD_RX_BUFFER_SIZE)
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#define SD_TXBUFFER SD_txBuffer
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#define SD_RXBUFFER SD_rxBuffer
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#endif /* (CY_SPIM_SD_H) */
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/* [] END OF FILE */
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