2961 lines
137 KiB
C
2961 lines
137 KiB
C
#ifndef INCLUDED_CYFITTER_H
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#define INCLUDED_CYFITTER_H
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#include <cydevice.h>
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#include <cydevice_trm.h>
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/* Debug_Timer_Interrupt */
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#define Debug_Timer_Interrupt__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
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#define Debug_Timer_Interrupt__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
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#define Debug_Timer_Interrupt__INTC_MASK 0x02u
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#define Debug_Timer_Interrupt__INTC_NUMBER 1u
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#define Debug_Timer_Interrupt__INTC_PRIOR_NUM 7u
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#define Debug_Timer_Interrupt__INTC_PRIOR_REG CYREG_NVIC_PRI_1
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#define Debug_Timer_Interrupt__INTC_SET_EN_REG CYREG_NVIC_SETENA0
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#define Debug_Timer_Interrupt__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
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/* SCSI_RX_DMA_COMPLETE */
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#define SCSI_RX_DMA_COMPLETE__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
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#define SCSI_RX_DMA_COMPLETE__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
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#define SCSI_RX_DMA_COMPLETE__INTC_MASK 0x01u
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#define SCSI_RX_DMA_COMPLETE__INTC_NUMBER 0u
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#define SCSI_RX_DMA_COMPLETE__INTC_PRIOR_NUM 7u
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#define SCSI_RX_DMA_COMPLETE__INTC_PRIOR_REG CYREG_NVIC_PRI_0
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#define SCSI_RX_DMA_COMPLETE__INTC_SET_EN_REG CYREG_NVIC_SETENA0
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#define SCSI_RX_DMA_COMPLETE__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
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/* SCSI_TX_DMA_COMPLETE */
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#define SCSI_TX_DMA_COMPLETE__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
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#define SCSI_TX_DMA_COMPLETE__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
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#define SCSI_TX_DMA_COMPLETE__INTC_MASK 0x04u
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#define SCSI_TX_DMA_COMPLETE__INTC_NUMBER 2u
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#define SCSI_TX_DMA_COMPLETE__INTC_PRIOR_NUM 7u
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#define SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG CYREG_NVIC_PRI_2
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#define SCSI_TX_DMA_COMPLETE__INTC_SET_EN_REG CYREG_NVIC_SETENA0
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#define SCSI_TX_DMA_COMPLETE__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
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/* Debug_Timer_TimerHW */
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#define Debug_Timer_TimerHW__CAP0 CYREG_TMR0_CAP0
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#define Debug_Timer_TimerHW__CAP1 CYREG_TMR0_CAP1
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#define Debug_Timer_TimerHW__CFG0 CYREG_TMR0_CFG0
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#define Debug_Timer_TimerHW__CFG1 CYREG_TMR0_CFG1
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#define Debug_Timer_TimerHW__CFG2 CYREG_TMR0_CFG2
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#define Debug_Timer_TimerHW__CNT_CMP0 CYREG_TMR0_CNT_CMP0
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#define Debug_Timer_TimerHW__CNT_CMP1 CYREG_TMR0_CNT_CMP1
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#define Debug_Timer_TimerHW__PER0 CYREG_TMR0_PER0
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#define Debug_Timer_TimerHW__PER1 CYREG_TMR0_PER1
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#define Debug_Timer_TimerHW__PM_ACT_CFG CYREG_PM_ACT_CFG3
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#define Debug_Timer_TimerHW__PM_ACT_MSK 0x01u
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#define Debug_Timer_TimerHW__PM_STBY_CFG CYREG_PM_STBY_CFG3
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#define Debug_Timer_TimerHW__PM_STBY_MSK 0x01u
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#define Debug_Timer_TimerHW__RT0 CYREG_TMR0_RT0
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#define Debug_Timer_TimerHW__RT1 CYREG_TMR0_RT1
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#define Debug_Timer_TimerHW__SR0 CYREG_TMR0_SR0
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/* SD_RX_DMA_COMPLETE */
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#define SD_RX_DMA_COMPLETE__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
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#define SD_RX_DMA_COMPLETE__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
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#define SD_RX_DMA_COMPLETE__INTC_MASK 0x08u
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#define SD_RX_DMA_COMPLETE__INTC_NUMBER 3u
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#define SD_RX_DMA_COMPLETE__INTC_PRIOR_NUM 7u
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#define SD_RX_DMA_COMPLETE__INTC_PRIOR_REG CYREG_NVIC_PRI_3
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#define SD_RX_DMA_COMPLETE__INTC_SET_EN_REG CYREG_NVIC_SETENA0
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#define SD_RX_DMA_COMPLETE__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
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/* SD_TX_DMA_COMPLETE */
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#define SD_TX_DMA_COMPLETE__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
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#define SD_TX_DMA_COMPLETE__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
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#define SD_TX_DMA_COMPLETE__INTC_MASK 0x10u
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#define SD_TX_DMA_COMPLETE__INTC_NUMBER 4u
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#define SD_TX_DMA_COMPLETE__INTC_PRIOR_NUM 7u
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#define SD_TX_DMA_COMPLETE__INTC_PRIOR_REG CYREG_NVIC_PRI_4
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#define SD_TX_DMA_COMPLETE__INTC_SET_EN_REG CYREG_NVIC_SETENA0
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#define SD_TX_DMA_COMPLETE__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
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/* SCSI_Parity_Error */
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#define SCSI_Parity_Error_sts_sts_reg__0__MASK 0x01u
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#define SCSI_Parity_Error_sts_sts_reg__0__POS 0
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#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB10_11_ACTL
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#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB10_11_ST
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#define SCSI_Parity_Error_sts_sts_reg__MASK 0x01u
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#define SCSI_Parity_Error_sts_sts_reg__MASK_REG CYREG_B0_UDB10_MSK
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#define SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB10_ACTL
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#define SCSI_Parity_Error_sts_sts_reg__STATUS_REG CYREG_B0_UDB10_ST
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/* USBFS_bus_reset */
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#define USBFS_bus_reset__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
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#define USBFS_bus_reset__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
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#define USBFS_bus_reset__INTC_MASK 0x800000u
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#define USBFS_bus_reset__INTC_NUMBER 23u
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#define USBFS_bus_reset__INTC_PRIOR_NUM 7u
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#define USBFS_bus_reset__INTC_PRIOR_REG CYREG_NVIC_PRI_23
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#define USBFS_bus_reset__INTC_SET_EN_REG CYREG_NVIC_SETENA0
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#define USBFS_bus_reset__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
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/* SCSI_CTL_PHASE */
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#define SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK 0x01u
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#define SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS 0
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#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB01_02_ACTL
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#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB01_02_CTL
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#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB01_02_CTL
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#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB01_02_CTL
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#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB01_02_CTL
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#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB01_02_MSK
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#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB01_02_MSK
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#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB01_02_MSK
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#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB01_02_MSK
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#define SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK 0x02u
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#define SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS 1
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#define SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK 0x04u
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#define SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS 2
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#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB01_ACTL
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#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB01_CTL
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#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB01_ST_CTL
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#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB01_CTL
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#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB01_ST_CTL
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#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK 0x07u
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#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB01_MSK_ACTL
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#define SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB01_MSK
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#define SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB01_MSK_ACTL
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/* SCSI_Out_Bits */
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#define SCSI_Out_Bits_Sync_ctrl_reg__0__MASK 0x01u
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#define SCSI_Out_Bits_Sync_ctrl_reg__0__POS 0
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#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB11_12_ACTL
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#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB11_12_CTL
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#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB11_12_CTL
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#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB11_12_CTL
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#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB11_12_CTL
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#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB11_12_MSK
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#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB11_12_MSK
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#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB11_12_MSK
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#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB11_12_MSK
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#define SCSI_Out_Bits_Sync_ctrl_reg__1__MASK 0x02u
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#define SCSI_Out_Bits_Sync_ctrl_reg__1__POS 1
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#define SCSI_Out_Bits_Sync_ctrl_reg__2__MASK 0x04u
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#define SCSI_Out_Bits_Sync_ctrl_reg__2__POS 2
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#define SCSI_Out_Bits_Sync_ctrl_reg__3__MASK 0x08u
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#define SCSI_Out_Bits_Sync_ctrl_reg__3__POS 3
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#define SCSI_Out_Bits_Sync_ctrl_reg__4__MASK 0x10u
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#define SCSI_Out_Bits_Sync_ctrl_reg__4__POS 4
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#define SCSI_Out_Bits_Sync_ctrl_reg__5__MASK 0x20u
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#define SCSI_Out_Bits_Sync_ctrl_reg__5__POS 5
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#define SCSI_Out_Bits_Sync_ctrl_reg__6__MASK 0x40u
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#define SCSI_Out_Bits_Sync_ctrl_reg__6__POS 6
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#define SCSI_Out_Bits_Sync_ctrl_reg__7__MASK 0x80u
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#define SCSI_Out_Bits_Sync_ctrl_reg__7__POS 7
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#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB11_ACTL
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#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB11_CTL
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#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB11_ST_CTL
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#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB11_CTL
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#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB11_ST_CTL
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#define SCSI_Out_Bits_Sync_ctrl_reg__MASK 0xFFu
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#define SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL
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#define SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB11_MSK
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#define SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL
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/* USBFS_arb_int */
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#define USBFS_arb_int__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
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#define USBFS_arb_int__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
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#define USBFS_arb_int__INTC_MASK 0x400000u
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#define USBFS_arb_int__INTC_NUMBER 22u
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#define USBFS_arb_int__INTC_PRIOR_NUM 7u
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#define USBFS_arb_int__INTC_PRIOR_REG CYREG_NVIC_PRI_22
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#define USBFS_arb_int__INTC_SET_EN_REG CYREG_NVIC_SETENA0
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#define USBFS_arb_int__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
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/* USBFS_sof_int */
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#define USBFS_sof_int__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
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#define USBFS_sof_int__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
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#define USBFS_sof_int__INTC_MASK 0x200000u
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#define USBFS_sof_int__INTC_NUMBER 21u
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#define USBFS_sof_int__INTC_PRIOR_NUM 7u
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#define USBFS_sof_int__INTC_PRIOR_REG CYREG_NVIC_PRI_21
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#define USBFS_sof_int__INTC_SET_EN_REG CYREG_NVIC_SETENA0
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#define USBFS_sof_int__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
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/* SCSI_Out_Ctl */
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#define SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK 0x01u
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#define SCSI_Out_Ctl_Sync_ctrl_reg__0__POS 0
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#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB14_15_ACTL
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#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB14_15_CTL
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#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB14_15_CTL
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#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB14_15_CTL
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#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB14_15_CTL
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#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB14_15_MSK
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#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB14_15_MSK
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#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB14_15_MSK
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#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB14_15_MSK
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#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB14_ACTL
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#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB14_CTL
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#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB14_ST_CTL
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#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB14_CTL
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#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB14_ST_CTL
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#define SCSI_Out_Ctl_Sync_ctrl_reg__MASK 0x01u
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#define SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB14_MSK_ACTL
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#define SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB14_MSK
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#define SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB14_MSK_ACTL
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/* SCSI_Out_DBx */
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#define SCSI_Out_DBx__0__AG CYREG_PRT6_AG
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#define SCSI_Out_DBx__0__AMUX CYREG_PRT6_AMUX
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#define SCSI_Out_DBx__0__BIE CYREG_PRT6_BIE
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#define SCSI_Out_DBx__0__BIT_MASK CYREG_PRT6_BIT_MASK
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#define SCSI_Out_DBx__0__BYP CYREG_PRT6_BYP
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#define SCSI_Out_DBx__0__CTL CYREG_PRT6_CTL
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#define SCSI_Out_DBx__0__DM0 CYREG_PRT6_DM0
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#define SCSI_Out_DBx__0__DM1 CYREG_PRT6_DM1
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#define SCSI_Out_DBx__0__DM2 CYREG_PRT6_DM2
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#define SCSI_Out_DBx__0__DR CYREG_PRT6_DR
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#define SCSI_Out_DBx__0__INP_DIS CYREG_PRT6_INP_DIS
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#define SCSI_Out_DBx__0__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG
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#define SCSI_Out_DBx__0__LCD_EN CYREG_PRT6_LCD_EN
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#define SCSI_Out_DBx__0__MASK 0x08u
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#define SCSI_Out_DBx__0__PC CYREG_PRT6_PC3
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#define SCSI_Out_DBx__0__PORT 6u
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#define SCSI_Out_DBx__0__PRT CYREG_PRT6_PRT
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#define SCSI_Out_DBx__0__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL
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#define SCSI_Out_DBx__0__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN
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#define SCSI_Out_DBx__0__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0
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#define SCSI_Out_DBx__0__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1
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#define SCSI_Out_DBx__0__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0
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#define SCSI_Out_DBx__0__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1
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#define SCSI_Out_DBx__0__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT
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#define SCSI_Out_DBx__0__PS CYREG_PRT6_PS
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#define SCSI_Out_DBx__0__SHIFT 3
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#define SCSI_Out_DBx__0__SLW CYREG_PRT6_SLW
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#define SCSI_Out_DBx__1__AG CYREG_PRT6_AG
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#define SCSI_Out_DBx__1__AMUX CYREG_PRT6_AMUX
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#define SCSI_Out_DBx__1__BIE CYREG_PRT6_BIE
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#define SCSI_Out_DBx__1__BIT_MASK CYREG_PRT6_BIT_MASK
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#define SCSI_Out_DBx__1__BYP CYREG_PRT6_BYP
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#define SCSI_Out_DBx__1__CTL CYREG_PRT6_CTL
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#define SCSI_Out_DBx__1__DM0 CYREG_PRT6_DM0
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#define SCSI_Out_DBx__1__DM1 CYREG_PRT6_DM1
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#define SCSI_Out_DBx__1__DM2 CYREG_PRT6_DM2
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#define SCSI_Out_DBx__1__DR CYREG_PRT6_DR
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#define SCSI_Out_DBx__1__INP_DIS CYREG_PRT6_INP_DIS
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#define SCSI_Out_DBx__1__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG
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#define SCSI_Out_DBx__1__LCD_EN CYREG_PRT6_LCD_EN
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#define SCSI_Out_DBx__1__MASK 0x04u
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#define SCSI_Out_DBx__1__PC CYREG_PRT6_PC2
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#define SCSI_Out_DBx__1__PORT 6u
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#define SCSI_Out_DBx__1__PRT CYREG_PRT6_PRT
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#define SCSI_Out_DBx__1__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL
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#define SCSI_Out_DBx__1__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN
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#define SCSI_Out_DBx__1__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0
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#define SCSI_Out_DBx__1__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1
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#define SCSI_Out_DBx__1__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0
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#define SCSI_Out_DBx__1__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1
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#define SCSI_Out_DBx__1__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT
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#define SCSI_Out_DBx__1__PS CYREG_PRT6_PS
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#define SCSI_Out_DBx__1__SHIFT 2
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#define SCSI_Out_DBx__1__SLW CYREG_PRT6_SLW
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#define SCSI_Out_DBx__2__AG CYREG_PRT6_AG
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#define SCSI_Out_DBx__2__AMUX CYREG_PRT6_AMUX
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#define SCSI_Out_DBx__2__BIE CYREG_PRT6_BIE
|
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#define SCSI_Out_DBx__2__BIT_MASK CYREG_PRT6_BIT_MASK
|
|
#define SCSI_Out_DBx__2__BYP CYREG_PRT6_BYP
|
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#define SCSI_Out_DBx__2__CTL CYREG_PRT6_CTL
|
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#define SCSI_Out_DBx__2__DM0 CYREG_PRT6_DM0
|
|
#define SCSI_Out_DBx__2__DM1 CYREG_PRT6_DM1
|
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#define SCSI_Out_DBx__2__DM2 CYREG_PRT6_DM2
|
|
#define SCSI_Out_DBx__2__DR CYREG_PRT6_DR
|
|
#define SCSI_Out_DBx__2__INP_DIS CYREG_PRT6_INP_DIS
|
|
#define SCSI_Out_DBx__2__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG
|
|
#define SCSI_Out_DBx__2__LCD_EN CYREG_PRT6_LCD_EN
|
|
#define SCSI_Out_DBx__2__MASK 0x02u
|
|
#define SCSI_Out_DBx__2__PC CYREG_PRT6_PC1
|
|
#define SCSI_Out_DBx__2__PORT 6u
|
|
#define SCSI_Out_DBx__2__PRT CYREG_PRT6_PRT
|
|
#define SCSI_Out_DBx__2__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL
|
|
#define SCSI_Out_DBx__2__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN
|
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#define SCSI_Out_DBx__2__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0
|
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#define SCSI_Out_DBx__2__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1
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#define SCSI_Out_DBx__2__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0
|
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#define SCSI_Out_DBx__2__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1
|
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#define SCSI_Out_DBx__2__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT
|
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#define SCSI_Out_DBx__2__PS CYREG_PRT6_PS
|
|
#define SCSI_Out_DBx__2__SHIFT 1
|
|
#define SCSI_Out_DBx__2__SLW CYREG_PRT6_SLW
|
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#define SCSI_Out_DBx__3__AG CYREG_PRT6_AG
|
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#define SCSI_Out_DBx__3__AMUX CYREG_PRT6_AMUX
|
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#define SCSI_Out_DBx__3__BIE CYREG_PRT6_BIE
|
|
#define SCSI_Out_DBx__3__BIT_MASK CYREG_PRT6_BIT_MASK
|
|
#define SCSI_Out_DBx__3__BYP CYREG_PRT6_BYP
|
|
#define SCSI_Out_DBx__3__CTL CYREG_PRT6_CTL
|
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#define SCSI_Out_DBx__3__DM0 CYREG_PRT6_DM0
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|
#define SCSI_Out_DBx__3__DM1 CYREG_PRT6_DM1
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|
#define SCSI_Out_DBx__3__DM2 CYREG_PRT6_DM2
|
|
#define SCSI_Out_DBx__3__DR CYREG_PRT6_DR
|
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#define SCSI_Out_DBx__3__INP_DIS CYREG_PRT6_INP_DIS
|
|
#define SCSI_Out_DBx__3__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG
|
|
#define SCSI_Out_DBx__3__LCD_EN CYREG_PRT6_LCD_EN
|
|
#define SCSI_Out_DBx__3__MASK 0x01u
|
|
#define SCSI_Out_DBx__3__PC CYREG_PRT6_PC0
|
|
#define SCSI_Out_DBx__3__PORT 6u
|
|
#define SCSI_Out_DBx__3__PRT CYREG_PRT6_PRT
|
|
#define SCSI_Out_DBx__3__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL
|
|
#define SCSI_Out_DBx__3__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN
|
|
#define SCSI_Out_DBx__3__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0
|
|
#define SCSI_Out_DBx__3__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1
|
|
#define SCSI_Out_DBx__3__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0
|
|
#define SCSI_Out_DBx__3__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1
|
|
#define SCSI_Out_DBx__3__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT
|
|
#define SCSI_Out_DBx__3__PS CYREG_PRT6_PS
|
|
#define SCSI_Out_DBx__3__SHIFT 0
|
|
#define SCSI_Out_DBx__3__SLW CYREG_PRT6_SLW
|
|
#define SCSI_Out_DBx__4__AG CYREG_PRT4_AG
|
|
#define SCSI_Out_DBx__4__AMUX CYREG_PRT4_AMUX
|
|
#define SCSI_Out_DBx__4__BIE CYREG_PRT4_BIE
|
|
#define SCSI_Out_DBx__4__BIT_MASK CYREG_PRT4_BIT_MASK
|
|
#define SCSI_Out_DBx__4__BYP CYREG_PRT4_BYP
|
|
#define SCSI_Out_DBx__4__CTL CYREG_PRT4_CTL
|
|
#define SCSI_Out_DBx__4__DM0 CYREG_PRT4_DM0
|
|
#define SCSI_Out_DBx__4__DM1 CYREG_PRT4_DM1
|
|
#define SCSI_Out_DBx__4__DM2 CYREG_PRT4_DM2
|
|
#define SCSI_Out_DBx__4__DR CYREG_PRT4_DR
|
|
#define SCSI_Out_DBx__4__INP_DIS CYREG_PRT4_INP_DIS
|
|
#define SCSI_Out_DBx__4__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG
|
|
#define SCSI_Out_DBx__4__LCD_EN CYREG_PRT4_LCD_EN
|
|
#define SCSI_Out_DBx__4__MASK 0x80u
|
|
#define SCSI_Out_DBx__4__PC CYREG_PRT4_PC7
|
|
#define SCSI_Out_DBx__4__PORT 4u
|
|
#define SCSI_Out_DBx__4__PRT CYREG_PRT4_PRT
|
|
#define SCSI_Out_DBx__4__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL
|
|
#define SCSI_Out_DBx__4__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN
|
|
#define SCSI_Out_DBx__4__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0
|
|
#define SCSI_Out_DBx__4__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1
|
|
#define SCSI_Out_DBx__4__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0
|
|
#define SCSI_Out_DBx__4__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1
|
|
#define SCSI_Out_DBx__4__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT
|
|
#define SCSI_Out_DBx__4__PS CYREG_PRT4_PS
|
|
#define SCSI_Out_DBx__4__SHIFT 7
|
|
#define SCSI_Out_DBx__4__SLW CYREG_PRT4_SLW
|
|
#define SCSI_Out_DBx__5__AG CYREG_PRT4_AG
|
|
#define SCSI_Out_DBx__5__AMUX CYREG_PRT4_AMUX
|
|
#define SCSI_Out_DBx__5__BIE CYREG_PRT4_BIE
|
|
#define SCSI_Out_DBx__5__BIT_MASK CYREG_PRT4_BIT_MASK
|
|
#define SCSI_Out_DBx__5__BYP CYREG_PRT4_BYP
|
|
#define SCSI_Out_DBx__5__CTL CYREG_PRT4_CTL
|
|
#define SCSI_Out_DBx__5__DM0 CYREG_PRT4_DM0
|
|
#define SCSI_Out_DBx__5__DM1 CYREG_PRT4_DM1
|
|
#define SCSI_Out_DBx__5__DM2 CYREG_PRT4_DM2
|
|
#define SCSI_Out_DBx__5__DR CYREG_PRT4_DR
|
|
#define SCSI_Out_DBx__5__INP_DIS CYREG_PRT4_INP_DIS
|
|
#define SCSI_Out_DBx__5__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG
|
|
#define SCSI_Out_DBx__5__LCD_EN CYREG_PRT4_LCD_EN
|
|
#define SCSI_Out_DBx__5__MASK 0x40u
|
|
#define SCSI_Out_DBx__5__PC CYREG_PRT4_PC6
|
|
#define SCSI_Out_DBx__5__PORT 4u
|
|
#define SCSI_Out_DBx__5__PRT CYREG_PRT4_PRT
|
|
#define SCSI_Out_DBx__5__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL
|
|
#define SCSI_Out_DBx__5__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN
|
|
#define SCSI_Out_DBx__5__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0
|
|
#define SCSI_Out_DBx__5__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1
|
|
#define SCSI_Out_DBx__5__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0
|
|
#define SCSI_Out_DBx__5__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1
|
|
#define SCSI_Out_DBx__5__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT
|
|
#define SCSI_Out_DBx__5__PS CYREG_PRT4_PS
|
|
#define SCSI_Out_DBx__5__SHIFT 6
|
|
#define SCSI_Out_DBx__5__SLW CYREG_PRT4_SLW
|
|
#define SCSI_Out_DBx__6__AG CYREG_PRT4_AG
|
|
#define SCSI_Out_DBx__6__AMUX CYREG_PRT4_AMUX
|
|
#define SCSI_Out_DBx__6__BIE CYREG_PRT4_BIE
|
|
#define SCSI_Out_DBx__6__BIT_MASK CYREG_PRT4_BIT_MASK
|
|
#define SCSI_Out_DBx__6__BYP CYREG_PRT4_BYP
|
|
#define SCSI_Out_DBx__6__CTL CYREG_PRT4_CTL
|
|
#define SCSI_Out_DBx__6__DM0 CYREG_PRT4_DM0
|
|
#define SCSI_Out_DBx__6__DM1 CYREG_PRT4_DM1
|
|
#define SCSI_Out_DBx__6__DM2 CYREG_PRT4_DM2
|
|
#define SCSI_Out_DBx__6__DR CYREG_PRT4_DR
|
|
#define SCSI_Out_DBx__6__INP_DIS CYREG_PRT4_INP_DIS
|
|
#define SCSI_Out_DBx__6__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG
|
|
#define SCSI_Out_DBx__6__LCD_EN CYREG_PRT4_LCD_EN
|
|
#define SCSI_Out_DBx__6__MASK 0x20u
|
|
#define SCSI_Out_DBx__6__PC CYREG_PRT4_PC5
|
|
#define SCSI_Out_DBx__6__PORT 4u
|
|
#define SCSI_Out_DBx__6__PRT CYREG_PRT4_PRT
|
|
#define SCSI_Out_DBx__6__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL
|
|
#define SCSI_Out_DBx__6__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN
|
|
#define SCSI_Out_DBx__6__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0
|
|
#define SCSI_Out_DBx__6__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1
|
|
#define SCSI_Out_DBx__6__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0
|
|
#define SCSI_Out_DBx__6__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1
|
|
#define SCSI_Out_DBx__6__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT
|
|
#define SCSI_Out_DBx__6__PS CYREG_PRT4_PS
|
|
#define SCSI_Out_DBx__6__SHIFT 5
|
|
#define SCSI_Out_DBx__6__SLW CYREG_PRT4_SLW
|
|
#define SCSI_Out_DBx__7__AG CYREG_PRT4_AG
|
|
#define SCSI_Out_DBx__7__AMUX CYREG_PRT4_AMUX
|
|
#define SCSI_Out_DBx__7__BIE CYREG_PRT4_BIE
|
|
#define SCSI_Out_DBx__7__BIT_MASK CYREG_PRT4_BIT_MASK
|
|
#define SCSI_Out_DBx__7__BYP CYREG_PRT4_BYP
|
|
#define SCSI_Out_DBx__7__CTL CYREG_PRT4_CTL
|
|
#define SCSI_Out_DBx__7__DM0 CYREG_PRT4_DM0
|
|
#define SCSI_Out_DBx__7__DM1 CYREG_PRT4_DM1
|
|
#define SCSI_Out_DBx__7__DM2 CYREG_PRT4_DM2
|
|
#define SCSI_Out_DBx__7__DR CYREG_PRT4_DR
|
|
#define SCSI_Out_DBx__7__INP_DIS CYREG_PRT4_INP_DIS
|
|
#define SCSI_Out_DBx__7__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG
|
|
#define SCSI_Out_DBx__7__LCD_EN CYREG_PRT4_LCD_EN
|
|
#define SCSI_Out_DBx__7__MASK 0x10u
|
|
#define SCSI_Out_DBx__7__PC CYREG_PRT4_PC4
|
|
#define SCSI_Out_DBx__7__PORT 4u
|
|
#define SCSI_Out_DBx__7__PRT CYREG_PRT4_PRT
|
|
#define SCSI_Out_DBx__7__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL
|
|
#define SCSI_Out_DBx__7__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN
|
|
#define SCSI_Out_DBx__7__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0
|
|
#define SCSI_Out_DBx__7__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1
|
|
#define SCSI_Out_DBx__7__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0
|
|
#define SCSI_Out_DBx__7__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1
|
|
#define SCSI_Out_DBx__7__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT
|
|
#define SCSI_Out_DBx__7__PS CYREG_PRT4_PS
|
|
#define SCSI_Out_DBx__7__SHIFT 4
|
|
#define SCSI_Out_DBx__7__SLW CYREG_PRT4_SLW
|
|
#define SCSI_Out_DBx__DB0__AG CYREG_PRT6_AG
|
|
#define SCSI_Out_DBx__DB0__AMUX CYREG_PRT6_AMUX
|
|
#define SCSI_Out_DBx__DB0__BIE CYREG_PRT6_BIE
|
|
#define SCSI_Out_DBx__DB0__BIT_MASK CYREG_PRT6_BIT_MASK
|
|
#define SCSI_Out_DBx__DB0__BYP CYREG_PRT6_BYP
|
|
#define SCSI_Out_DBx__DB0__CTL CYREG_PRT6_CTL
|
|
#define SCSI_Out_DBx__DB0__DM0 CYREG_PRT6_DM0
|
|
#define SCSI_Out_DBx__DB0__DM1 CYREG_PRT6_DM1
|
|
#define SCSI_Out_DBx__DB0__DM2 CYREG_PRT6_DM2
|
|
#define SCSI_Out_DBx__DB0__DR CYREG_PRT6_DR
|
|
#define SCSI_Out_DBx__DB0__INP_DIS CYREG_PRT6_INP_DIS
|
|
#define SCSI_Out_DBx__DB0__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG
|
|
#define SCSI_Out_DBx__DB0__LCD_EN CYREG_PRT6_LCD_EN
|
|
#define SCSI_Out_DBx__DB0__MASK 0x08u
|
|
#define SCSI_Out_DBx__DB0__PC CYREG_PRT6_PC3
|
|
#define SCSI_Out_DBx__DB0__PORT 6u
|
|
#define SCSI_Out_DBx__DB0__PRT CYREG_PRT6_PRT
|
|
#define SCSI_Out_DBx__DB0__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL
|
|
#define SCSI_Out_DBx__DB0__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN
|
|
#define SCSI_Out_DBx__DB0__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0
|
|
#define SCSI_Out_DBx__DB0__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1
|
|
#define SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0
|
|
#define SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1
|
|
#define SCSI_Out_DBx__DB0__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT
|
|
#define SCSI_Out_DBx__DB0__PS CYREG_PRT6_PS
|
|
#define SCSI_Out_DBx__DB0__SHIFT 3
|
|
#define SCSI_Out_DBx__DB0__SLW CYREG_PRT6_SLW
|
|
#define SCSI_Out_DBx__DB1__AG CYREG_PRT6_AG
|
|
#define SCSI_Out_DBx__DB1__AMUX CYREG_PRT6_AMUX
|
|
#define SCSI_Out_DBx__DB1__BIE CYREG_PRT6_BIE
|
|
#define SCSI_Out_DBx__DB1__BIT_MASK CYREG_PRT6_BIT_MASK
|
|
#define SCSI_Out_DBx__DB1__BYP CYREG_PRT6_BYP
|
|
#define SCSI_Out_DBx__DB1__CTL CYREG_PRT6_CTL
|
|
#define SCSI_Out_DBx__DB1__DM0 CYREG_PRT6_DM0
|
|
#define SCSI_Out_DBx__DB1__DM1 CYREG_PRT6_DM1
|
|
#define SCSI_Out_DBx__DB1__DM2 CYREG_PRT6_DM2
|
|
#define SCSI_Out_DBx__DB1__DR CYREG_PRT6_DR
|
|
#define SCSI_Out_DBx__DB1__INP_DIS CYREG_PRT6_INP_DIS
|
|
#define SCSI_Out_DBx__DB1__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG
|
|
#define SCSI_Out_DBx__DB1__LCD_EN CYREG_PRT6_LCD_EN
|
|
#define SCSI_Out_DBx__DB1__MASK 0x04u
|
|
#define SCSI_Out_DBx__DB1__PC CYREG_PRT6_PC2
|
|
#define SCSI_Out_DBx__DB1__PORT 6u
|
|
#define SCSI_Out_DBx__DB1__PRT CYREG_PRT6_PRT
|
|
#define SCSI_Out_DBx__DB1__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL
|
|
#define SCSI_Out_DBx__DB1__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN
|
|
#define SCSI_Out_DBx__DB1__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0
|
|
#define SCSI_Out_DBx__DB1__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1
|
|
#define SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0
|
|
#define SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1
|
|
#define SCSI_Out_DBx__DB1__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT
|
|
#define SCSI_Out_DBx__DB1__PS CYREG_PRT6_PS
|
|
#define SCSI_Out_DBx__DB1__SHIFT 2
|
|
#define SCSI_Out_DBx__DB1__SLW CYREG_PRT6_SLW
|
|
#define SCSI_Out_DBx__DB2__AG CYREG_PRT6_AG
|
|
#define SCSI_Out_DBx__DB2__AMUX CYREG_PRT6_AMUX
|
|
#define SCSI_Out_DBx__DB2__BIE CYREG_PRT6_BIE
|
|
#define SCSI_Out_DBx__DB2__BIT_MASK CYREG_PRT6_BIT_MASK
|
|
#define SCSI_Out_DBx__DB2__BYP CYREG_PRT6_BYP
|
|
#define SCSI_Out_DBx__DB2__CTL CYREG_PRT6_CTL
|
|
#define SCSI_Out_DBx__DB2__DM0 CYREG_PRT6_DM0
|
|
#define SCSI_Out_DBx__DB2__DM1 CYREG_PRT6_DM1
|
|
#define SCSI_Out_DBx__DB2__DM2 CYREG_PRT6_DM2
|
|
#define SCSI_Out_DBx__DB2__DR CYREG_PRT6_DR
|
|
#define SCSI_Out_DBx__DB2__INP_DIS CYREG_PRT6_INP_DIS
|
|
#define SCSI_Out_DBx__DB2__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG
|
|
#define SCSI_Out_DBx__DB2__LCD_EN CYREG_PRT6_LCD_EN
|
|
#define SCSI_Out_DBx__DB2__MASK 0x02u
|
|
#define SCSI_Out_DBx__DB2__PC CYREG_PRT6_PC1
|
|
#define SCSI_Out_DBx__DB2__PORT 6u
|
|
#define SCSI_Out_DBx__DB2__PRT CYREG_PRT6_PRT
|
|
#define SCSI_Out_DBx__DB2__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL
|
|
#define SCSI_Out_DBx__DB2__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN
|
|
#define SCSI_Out_DBx__DB2__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0
|
|
#define SCSI_Out_DBx__DB2__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1
|
|
#define SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0
|
|
#define SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1
|
|
#define SCSI_Out_DBx__DB2__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT
|
|
#define SCSI_Out_DBx__DB2__PS CYREG_PRT6_PS
|
|
#define SCSI_Out_DBx__DB2__SHIFT 1
|
|
#define SCSI_Out_DBx__DB2__SLW CYREG_PRT6_SLW
|
|
#define SCSI_Out_DBx__DB3__AG CYREG_PRT6_AG
|
|
#define SCSI_Out_DBx__DB3__AMUX CYREG_PRT6_AMUX
|
|
#define SCSI_Out_DBx__DB3__BIE CYREG_PRT6_BIE
|
|
#define SCSI_Out_DBx__DB3__BIT_MASK CYREG_PRT6_BIT_MASK
|
|
#define SCSI_Out_DBx__DB3__BYP CYREG_PRT6_BYP
|
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#define SCSI_Out_DBx__DB3__CTL CYREG_PRT6_CTL
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#define SCSI_Out_DBx__DB3__DM0 CYREG_PRT6_DM0
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#define SCSI_Out_DBx__DB3__DM1 CYREG_PRT6_DM1
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#define SCSI_Out_DBx__DB3__DM2 CYREG_PRT6_DM2
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#define SCSI_Out_DBx__DB3__DR CYREG_PRT6_DR
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#define SCSI_Out_DBx__DB3__INP_DIS CYREG_PRT6_INP_DIS
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#define SCSI_Out_DBx__DB3__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG
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#define SCSI_Out_DBx__DB3__LCD_EN CYREG_PRT6_LCD_EN
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#define SCSI_Out_DBx__DB3__MASK 0x01u
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#define SCSI_Out_DBx__DB3__PC CYREG_PRT6_PC0
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#define SCSI_Out_DBx__DB3__PORT 6u
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#define SCSI_Out_DBx__DB3__PRT CYREG_PRT6_PRT
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#define SCSI_Out_DBx__DB3__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL
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#define SCSI_Out_DBx__DB3__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN
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#define SCSI_Out_DBx__DB3__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0
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#define SCSI_Out_DBx__DB3__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1
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#define SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0
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#define SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1
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#define SCSI_Out_DBx__DB3__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT
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#define SCSI_Out_DBx__DB3__PS CYREG_PRT6_PS
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#define SCSI_Out_DBx__DB3__SHIFT 0
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#define SCSI_Out_DBx__DB3__SLW CYREG_PRT6_SLW
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#define SCSI_Out_DBx__DB4__AG CYREG_PRT4_AG
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#define SCSI_Out_DBx__DB4__AMUX CYREG_PRT4_AMUX
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#define SCSI_Out_DBx__DB4__BIE CYREG_PRT4_BIE
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#define SCSI_Out_DBx__DB4__BIT_MASK CYREG_PRT4_BIT_MASK
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#define SCSI_Out_DBx__DB4__BYP CYREG_PRT4_BYP
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#define SCSI_Out_DBx__DB4__CTL CYREG_PRT4_CTL
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#define SCSI_Out_DBx__DB4__DM0 CYREG_PRT4_DM0
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#define SCSI_Out_DBx__DB4__DM1 CYREG_PRT4_DM1
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#define SCSI_Out_DBx__DB4__DM2 CYREG_PRT4_DM2
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#define SCSI_Out_DBx__DB4__DR CYREG_PRT4_DR
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#define SCSI_Out_DBx__DB4__INP_DIS CYREG_PRT4_INP_DIS
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#define SCSI_Out_DBx__DB4__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG
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#define SCSI_Out_DBx__DB4__LCD_EN CYREG_PRT4_LCD_EN
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#define SCSI_Out_DBx__DB4__MASK 0x80u
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#define SCSI_Out_DBx__DB4__PC CYREG_PRT4_PC7
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#define SCSI_Out_DBx__DB4__PORT 4u
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#define SCSI_Out_DBx__DB4__PRT CYREG_PRT4_PRT
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#define SCSI_Out_DBx__DB4__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL
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#define SCSI_Out_DBx__DB4__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN
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#define SCSI_Out_DBx__DB4__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0
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#define SCSI_Out_DBx__DB4__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1
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#define SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0
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#define SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1
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#define SCSI_Out_DBx__DB4__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT
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#define SCSI_Out_DBx__DB4__PS CYREG_PRT4_PS
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#define SCSI_Out_DBx__DB4__SHIFT 7
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#define SCSI_Out_DBx__DB4__SLW CYREG_PRT4_SLW
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#define SCSI_Out_DBx__DB5__AG CYREG_PRT4_AG
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#define SCSI_Out_DBx__DB5__AMUX CYREG_PRT4_AMUX
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#define SCSI_Out_DBx__DB5__BIE CYREG_PRT4_BIE
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#define SCSI_Out_DBx__DB5__BIT_MASK CYREG_PRT4_BIT_MASK
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#define SCSI_Out_DBx__DB5__BYP CYREG_PRT4_BYP
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#define SCSI_Out_DBx__DB5__CTL CYREG_PRT4_CTL
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#define SCSI_Out_DBx__DB5__DM0 CYREG_PRT4_DM0
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#define SCSI_Out_DBx__DB5__DM1 CYREG_PRT4_DM1
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#define SCSI_Out_DBx__DB5__DM2 CYREG_PRT4_DM2
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#define SCSI_Out_DBx__DB5__DR CYREG_PRT4_DR
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#define SCSI_Out_DBx__DB5__INP_DIS CYREG_PRT4_INP_DIS
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#define SCSI_Out_DBx__DB5__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG
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#define SCSI_Out_DBx__DB5__LCD_EN CYREG_PRT4_LCD_EN
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#define SCSI_Out_DBx__DB5__MASK 0x40u
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#define SCSI_Out_DBx__DB5__PC CYREG_PRT4_PC6
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#define SCSI_Out_DBx__DB5__PORT 4u
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#define SCSI_Out_DBx__DB5__PRT CYREG_PRT4_PRT
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#define SCSI_Out_DBx__DB5__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL
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#define SCSI_Out_DBx__DB5__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN
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#define SCSI_Out_DBx__DB5__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0
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#define SCSI_Out_DBx__DB5__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1
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#define SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0
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#define SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1
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#define SCSI_Out_DBx__DB5__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT
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#define SCSI_Out_DBx__DB5__PS CYREG_PRT4_PS
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#define SCSI_Out_DBx__DB5__SHIFT 6
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#define SCSI_Out_DBx__DB5__SLW CYREG_PRT4_SLW
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#define SCSI_Out_DBx__DB6__AG CYREG_PRT4_AG
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#define SCSI_Out_DBx__DB6__AMUX CYREG_PRT4_AMUX
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#define SCSI_Out_DBx__DB6__BIE CYREG_PRT4_BIE
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#define SCSI_Out_DBx__DB6__BIT_MASK CYREG_PRT4_BIT_MASK
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#define SCSI_Out_DBx__DB6__BYP CYREG_PRT4_BYP
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#define SCSI_Out_DBx__DB6__CTL CYREG_PRT4_CTL
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#define SCSI_Out_DBx__DB6__DM0 CYREG_PRT4_DM0
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#define SCSI_Out_DBx__DB6__DM1 CYREG_PRT4_DM1
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#define SCSI_Out_DBx__DB6__DM2 CYREG_PRT4_DM2
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#define SCSI_Out_DBx__DB6__DR CYREG_PRT4_DR
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#define SCSI_Out_DBx__DB6__INP_DIS CYREG_PRT4_INP_DIS
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#define SCSI_Out_DBx__DB6__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG
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#define SCSI_Out_DBx__DB6__LCD_EN CYREG_PRT4_LCD_EN
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#define SCSI_Out_DBx__DB6__MASK 0x20u
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#define SCSI_Out_DBx__DB6__PC CYREG_PRT4_PC5
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#define SCSI_Out_DBx__DB6__PORT 4u
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#define SCSI_Out_DBx__DB6__PRT CYREG_PRT4_PRT
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#define SCSI_Out_DBx__DB6__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL
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#define SCSI_Out_DBx__DB6__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN
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#define SCSI_Out_DBx__DB6__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0
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#define SCSI_Out_DBx__DB6__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1
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#define SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0
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#define SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1
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#define SCSI_Out_DBx__DB6__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT
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#define SCSI_Out_DBx__DB6__PS CYREG_PRT4_PS
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#define SCSI_Out_DBx__DB6__SHIFT 5
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#define SCSI_Out_DBx__DB6__SLW CYREG_PRT4_SLW
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#define SCSI_Out_DBx__DB7__AG CYREG_PRT4_AG
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#define SCSI_Out_DBx__DB7__AMUX CYREG_PRT4_AMUX
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#define SCSI_Out_DBx__DB7__BIE CYREG_PRT4_BIE
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#define SCSI_Out_DBx__DB7__BIT_MASK CYREG_PRT4_BIT_MASK
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#define SCSI_Out_DBx__DB7__BYP CYREG_PRT4_BYP
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#define SCSI_Out_DBx__DB7__CTL CYREG_PRT4_CTL
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#define SCSI_Out_DBx__DB7__DM0 CYREG_PRT4_DM0
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#define SCSI_Out_DBx__DB7__DM1 CYREG_PRT4_DM1
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#define SCSI_Out_DBx__DB7__DM2 CYREG_PRT4_DM2
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#define SCSI_Out_DBx__DB7__DR CYREG_PRT4_DR
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#define SCSI_Out_DBx__DB7__INP_DIS CYREG_PRT4_INP_DIS
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#define SCSI_Out_DBx__DB7__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG
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#define SCSI_Out_DBx__DB7__LCD_EN CYREG_PRT4_LCD_EN
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#define SCSI_Out_DBx__DB7__MASK 0x10u
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#define SCSI_Out_DBx__DB7__PC CYREG_PRT4_PC4
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#define SCSI_Out_DBx__DB7__PORT 4u
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#define SCSI_Out_DBx__DB7__PRT CYREG_PRT4_PRT
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#define SCSI_Out_DBx__DB7__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL
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#define SCSI_Out_DBx__DB7__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN
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#define SCSI_Out_DBx__DB7__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0
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#define SCSI_Out_DBx__DB7__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1
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#define SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0
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#define SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1
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#define SCSI_Out_DBx__DB7__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT
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#define SCSI_Out_DBx__DB7__PS CYREG_PRT4_PS
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#define SCSI_Out_DBx__DB7__SHIFT 4
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#define SCSI_Out_DBx__DB7__SLW CYREG_PRT4_SLW
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/* SCSI_RST_ISR */
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#define SCSI_RST_ISR__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
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#define SCSI_RST_ISR__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
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#define SCSI_RST_ISR__INTC_MASK 0x400u
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#define SCSI_RST_ISR__INTC_NUMBER 10u
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#define SCSI_RST_ISR__INTC_PRIOR_NUM 7u
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#define SCSI_RST_ISR__INTC_PRIOR_REG CYREG_NVIC_PRI_10
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#define SCSI_RST_ISR__INTC_SET_EN_REG CYREG_NVIC_SETENA0
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#define SCSI_RST_ISR__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
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/* SDCard_BSPIM */
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#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB06_07_ACTL
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#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG CYREG_B0_UDB06_07_ST
|
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#define SDCard_BSPIM_BitCounter_ST__MASK_REG CYREG_B0_UDB06_MSK
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#define SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG CYREG_B0_UDB06_MSK_ACTL
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#define SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG CYREG_B0_UDB06_MSK_ACTL
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#define SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG CYREG_B0_UDB06_ACTL
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#define SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG CYREG_B0_UDB06_ST_CTL
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#define SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG CYREG_B0_UDB06_ST_CTL
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#define SDCard_BSPIM_BitCounter_ST__STATUS_REG CYREG_B0_UDB06_ST
|
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#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB06_07_ACTL
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#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB06_07_CTL
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#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB06_07_CTL
|
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#define SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB06_07_CTL
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#define SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG CYREG_B0_UDB06_07_CTL
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#define SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG CYREG_B0_UDB06_07_MSK
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#define SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG CYREG_B0_UDB06_07_MSK
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#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG CYREG_B0_UDB06_07_MSK
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#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB06_07_MSK
|
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#define SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG CYREG_B0_UDB06_ACTL
|
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#define SDCard_BSPIM_BitCounter__CONTROL_REG CYREG_B0_UDB06_CTL
|
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#define SDCard_BSPIM_BitCounter__CONTROL_ST_REG CYREG_B0_UDB06_ST_CTL
|
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#define SDCard_BSPIM_BitCounter__COUNT_REG CYREG_B0_UDB06_CTL
|
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#define SDCard_BSPIM_BitCounter__COUNT_ST_REG CYREG_B0_UDB06_ST_CTL
|
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#define SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB06_MSK_ACTL
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#define SDCard_BSPIM_BitCounter__PERIOD_REG CYREG_B0_UDB06_MSK
|
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#define SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG CYREG_B0_UDB06_MSK_ACTL
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#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB05_06_ACTL
|
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#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B1_UDB05_06_ST
|
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#define SDCard_BSPIM_RxStsReg__4__MASK 0x10u
|
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#define SDCard_BSPIM_RxStsReg__4__POS 4
|
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#define SDCard_BSPIM_RxStsReg__5__MASK 0x20u
|
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#define SDCard_BSPIM_RxStsReg__5__POS 5
|
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#define SDCard_BSPIM_RxStsReg__6__MASK 0x40u
|
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#define SDCard_BSPIM_RxStsReg__6__POS 6
|
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#define SDCard_BSPIM_RxStsReg__MASK 0x70u
|
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#define SDCard_BSPIM_RxStsReg__MASK_REG CYREG_B1_UDB05_MSK
|
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#define SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB05_ACTL
|
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#define SDCard_BSPIM_RxStsReg__STATUS_REG CYREG_B1_UDB05_ST
|
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#define SDCard_BSPIM_TxStsReg__0__MASK 0x01u
|
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#define SDCard_BSPIM_TxStsReg__0__POS 0
|
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#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB05_06_ACTL
|
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#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG CYREG_B0_UDB05_06_ST
|
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#define SDCard_BSPIM_TxStsReg__1__MASK 0x02u
|
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#define SDCard_BSPIM_TxStsReg__1__POS 1
|
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#define SDCard_BSPIM_TxStsReg__2__MASK 0x04u
|
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#define SDCard_BSPIM_TxStsReg__2__POS 2
|
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#define SDCard_BSPIM_TxStsReg__3__MASK 0x08u
|
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#define SDCard_BSPIM_TxStsReg__3__POS 3
|
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#define SDCard_BSPIM_TxStsReg__4__MASK 0x10u
|
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#define SDCard_BSPIM_TxStsReg__4__POS 4
|
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#define SDCard_BSPIM_TxStsReg__MASK 0x1Fu
|
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#define SDCard_BSPIM_TxStsReg__MASK_REG CYREG_B0_UDB05_MSK
|
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#define SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG CYREG_B0_UDB05_ACTL
|
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#define SDCard_BSPIM_TxStsReg__STATUS_REG CYREG_B0_UDB05_ST
|
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#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG CYREG_B1_UDB06_07_A0
|
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#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG CYREG_B1_UDB06_07_A1
|
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#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG CYREG_B1_UDB06_07_D0
|
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#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG CYREG_B1_UDB06_07_D1
|
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#define SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG CYREG_B1_UDB06_07_ACTL
|
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#define SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG CYREG_B1_UDB06_07_F0
|
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#define SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG CYREG_B1_UDB06_07_F1
|
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#define SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG CYREG_B1_UDB06_A0_A1
|
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#define SDCard_BSPIM_sR8_Dp_u0__A0_REG CYREG_B1_UDB06_A0
|
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#define SDCard_BSPIM_sR8_Dp_u0__A1_REG CYREG_B1_UDB06_A1
|
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#define SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG CYREG_B1_UDB06_D0_D1
|
|
#define SDCard_BSPIM_sR8_Dp_u0__D0_REG CYREG_B1_UDB06_D0
|
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#define SDCard_BSPIM_sR8_Dp_u0__D1_REG CYREG_B1_UDB06_D1
|
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#define SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG CYREG_B1_UDB06_ACTL
|
|
#define SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG CYREG_B1_UDB06_F0_F1
|
|
#define SDCard_BSPIM_sR8_Dp_u0__F0_REG CYREG_B1_UDB06_F0
|
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#define SDCard_BSPIM_sR8_Dp_u0__F1_REG CYREG_B1_UDB06_F1
|
|
|
|
/* USBFS_dp_int */
|
|
#define USBFS_dp_int__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
|
|
#define USBFS_dp_int__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
|
|
#define USBFS_dp_int__INTC_MASK 0x1000u
|
|
#define USBFS_dp_int__INTC_NUMBER 12u
|
|
#define USBFS_dp_int__INTC_PRIOR_NUM 7u
|
|
#define USBFS_dp_int__INTC_PRIOR_REG CYREG_NVIC_PRI_12
|
|
#define USBFS_dp_int__INTC_SET_EN_REG CYREG_NVIC_SETENA0
|
|
#define USBFS_dp_int__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
|
|
|
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/* SCSI_In_DBx */
|
|
#define SCSI_In_DBx__0__AG CYREG_PRT12_AG
|
|
#define SCSI_In_DBx__0__BIE CYREG_PRT12_BIE
|
|
#define SCSI_In_DBx__0__BIT_MASK CYREG_PRT12_BIT_MASK
|
|
#define SCSI_In_DBx__0__BYP CYREG_PRT12_BYP
|
|
#define SCSI_In_DBx__0__DM0 CYREG_PRT12_DM0
|
|
#define SCSI_In_DBx__0__DM1 CYREG_PRT12_DM1
|
|
#define SCSI_In_DBx__0__DM2 CYREG_PRT12_DM2
|
|
#define SCSI_In_DBx__0__DR CYREG_PRT12_DR
|
|
#define SCSI_In_DBx__0__INP_DIS CYREG_PRT12_INP_DIS
|
|
#define SCSI_In_DBx__0__MASK 0x10u
|
|
#define SCSI_In_DBx__0__PC CYREG_PRT12_PC4
|
|
#define SCSI_In_DBx__0__PORT 12u
|
|
#define SCSI_In_DBx__0__PRT CYREG_PRT12_PRT
|
|
#define SCSI_In_DBx__0__PRTDSI__DBL_SYNC_IN CYREG_PRT12_DBL_SYNC_IN
|
|
#define SCSI_In_DBx__0__PRTDSI__OE_SEL0 CYREG_PRT12_OE_SEL0
|
|
#define SCSI_In_DBx__0__PRTDSI__OE_SEL1 CYREG_PRT12_OE_SEL1
|
|
#define SCSI_In_DBx__0__PRTDSI__OUT_SEL0 CYREG_PRT12_OUT_SEL0
|
|
#define SCSI_In_DBx__0__PRTDSI__OUT_SEL1 CYREG_PRT12_OUT_SEL1
|
|
#define SCSI_In_DBx__0__PRTDSI__SYNC_OUT CYREG_PRT12_SYNC_OUT
|
|
#define SCSI_In_DBx__0__PS CYREG_PRT12_PS
|
|
#define SCSI_In_DBx__0__SHIFT 4
|
|
#define SCSI_In_DBx__0__SIO_CFG CYREG_PRT12_SIO_CFG
|
|
#define SCSI_In_DBx__0__SIO_DIFF CYREG_PRT12_SIO_DIFF
|
|
#define SCSI_In_DBx__0__SIO_HYST_EN CYREG_PRT12_SIO_HYST_EN
|
|
#define SCSI_In_DBx__0__SIO_REG_HIFREQ CYREG_PRT12_SIO_REG_HIFREQ
|
|
#define SCSI_In_DBx__0__SLW CYREG_PRT12_SLW
|
|
#define SCSI_In_DBx__1__AG CYREG_PRT2_AG
|
|
#define SCSI_In_DBx__1__AMUX CYREG_PRT2_AMUX
|
|
#define SCSI_In_DBx__1__BIE CYREG_PRT2_BIE
|
|
#define SCSI_In_DBx__1__BIT_MASK CYREG_PRT2_BIT_MASK
|
|
#define SCSI_In_DBx__1__BYP CYREG_PRT2_BYP
|
|
#define SCSI_In_DBx__1__CTL CYREG_PRT2_CTL
|
|
#define SCSI_In_DBx__1__DM0 CYREG_PRT2_DM0
|
|
#define SCSI_In_DBx__1__DM1 CYREG_PRT2_DM1
|
|
#define SCSI_In_DBx__1__DM2 CYREG_PRT2_DM2
|
|
#define SCSI_In_DBx__1__DR CYREG_PRT2_DR
|
|
#define SCSI_In_DBx__1__INP_DIS CYREG_PRT2_INP_DIS
|
|
#define SCSI_In_DBx__1__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG
|
|
#define SCSI_In_DBx__1__LCD_EN CYREG_PRT2_LCD_EN
|
|
#define SCSI_In_DBx__1__MASK 0x80u
|
|
#define SCSI_In_DBx__1__PC CYREG_PRT2_PC7
|
|
#define SCSI_In_DBx__1__PORT 2u
|
|
#define SCSI_In_DBx__1__PRT CYREG_PRT2_PRT
|
|
#define SCSI_In_DBx__1__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL
|
|
#define SCSI_In_DBx__1__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN
|
|
#define SCSI_In_DBx__1__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0
|
|
#define SCSI_In_DBx__1__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1
|
|
#define SCSI_In_DBx__1__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0
|
|
#define SCSI_In_DBx__1__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1
|
|
#define SCSI_In_DBx__1__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT
|
|
#define SCSI_In_DBx__1__PS CYREG_PRT2_PS
|
|
#define SCSI_In_DBx__1__SHIFT 7
|
|
#define SCSI_In_DBx__1__SLW CYREG_PRT2_SLW
|
|
#define SCSI_In_DBx__2__AG CYREG_PRT2_AG
|
|
#define SCSI_In_DBx__2__AMUX CYREG_PRT2_AMUX
|
|
#define SCSI_In_DBx__2__BIE CYREG_PRT2_BIE
|
|
#define SCSI_In_DBx__2__BIT_MASK CYREG_PRT2_BIT_MASK
|
|
#define SCSI_In_DBx__2__BYP CYREG_PRT2_BYP
|
|
#define SCSI_In_DBx__2__CTL CYREG_PRT2_CTL
|
|
#define SCSI_In_DBx__2__DM0 CYREG_PRT2_DM0
|
|
#define SCSI_In_DBx__2__DM1 CYREG_PRT2_DM1
|
|
#define SCSI_In_DBx__2__DM2 CYREG_PRT2_DM2
|
|
#define SCSI_In_DBx__2__DR CYREG_PRT2_DR
|
|
#define SCSI_In_DBx__2__INP_DIS CYREG_PRT2_INP_DIS
|
|
#define SCSI_In_DBx__2__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG
|
|
#define SCSI_In_DBx__2__LCD_EN CYREG_PRT2_LCD_EN
|
|
#define SCSI_In_DBx__2__MASK 0x40u
|
|
#define SCSI_In_DBx__2__PC CYREG_PRT2_PC6
|
|
#define SCSI_In_DBx__2__PORT 2u
|
|
#define SCSI_In_DBx__2__PRT CYREG_PRT2_PRT
|
|
#define SCSI_In_DBx__2__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL
|
|
#define SCSI_In_DBx__2__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN
|
|
#define SCSI_In_DBx__2__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0
|
|
#define SCSI_In_DBx__2__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1
|
|
#define SCSI_In_DBx__2__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0
|
|
#define SCSI_In_DBx__2__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1
|
|
#define SCSI_In_DBx__2__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT
|
|
#define SCSI_In_DBx__2__PS CYREG_PRT2_PS
|
|
#define SCSI_In_DBx__2__SHIFT 6
|
|
#define SCSI_In_DBx__2__SLW CYREG_PRT2_SLW
|
|
#define SCSI_In_DBx__3__AG CYREG_PRT2_AG
|
|
#define SCSI_In_DBx__3__AMUX CYREG_PRT2_AMUX
|
|
#define SCSI_In_DBx__3__BIE CYREG_PRT2_BIE
|
|
#define SCSI_In_DBx__3__BIT_MASK CYREG_PRT2_BIT_MASK
|
|
#define SCSI_In_DBx__3__BYP CYREG_PRT2_BYP
|
|
#define SCSI_In_DBx__3__CTL CYREG_PRT2_CTL
|
|
#define SCSI_In_DBx__3__DM0 CYREG_PRT2_DM0
|
|
#define SCSI_In_DBx__3__DM1 CYREG_PRT2_DM1
|
|
#define SCSI_In_DBx__3__DM2 CYREG_PRT2_DM2
|
|
#define SCSI_In_DBx__3__DR CYREG_PRT2_DR
|
|
#define SCSI_In_DBx__3__INP_DIS CYREG_PRT2_INP_DIS
|
|
#define SCSI_In_DBx__3__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG
|
|
#define SCSI_In_DBx__3__LCD_EN CYREG_PRT2_LCD_EN
|
|
#define SCSI_In_DBx__3__MASK 0x20u
|
|
#define SCSI_In_DBx__3__PC CYREG_PRT2_PC5
|
|
#define SCSI_In_DBx__3__PORT 2u
|
|
#define SCSI_In_DBx__3__PRT CYREG_PRT2_PRT
|
|
#define SCSI_In_DBx__3__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL
|
|
#define SCSI_In_DBx__3__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN
|
|
#define SCSI_In_DBx__3__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0
|
|
#define SCSI_In_DBx__3__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1
|
|
#define SCSI_In_DBx__3__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0
|
|
#define SCSI_In_DBx__3__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1
|
|
#define SCSI_In_DBx__3__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT
|
|
#define SCSI_In_DBx__3__PS CYREG_PRT2_PS
|
|
#define SCSI_In_DBx__3__SHIFT 5
|
|
#define SCSI_In_DBx__3__SLW CYREG_PRT2_SLW
|
|
#define SCSI_In_DBx__4__AG CYREG_PRT2_AG
|
|
#define SCSI_In_DBx__4__AMUX CYREG_PRT2_AMUX
|
|
#define SCSI_In_DBx__4__BIE CYREG_PRT2_BIE
|
|
#define SCSI_In_DBx__4__BIT_MASK CYREG_PRT2_BIT_MASK
|
|
#define SCSI_In_DBx__4__BYP CYREG_PRT2_BYP
|
|
#define SCSI_In_DBx__4__CTL CYREG_PRT2_CTL
|
|
#define SCSI_In_DBx__4__DM0 CYREG_PRT2_DM0
|
|
#define SCSI_In_DBx__4__DM1 CYREG_PRT2_DM1
|
|
#define SCSI_In_DBx__4__DM2 CYREG_PRT2_DM2
|
|
#define SCSI_In_DBx__4__DR CYREG_PRT2_DR
|
|
#define SCSI_In_DBx__4__INP_DIS CYREG_PRT2_INP_DIS
|
|
#define SCSI_In_DBx__4__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG
|
|
#define SCSI_In_DBx__4__LCD_EN CYREG_PRT2_LCD_EN
|
|
#define SCSI_In_DBx__4__MASK 0x10u
|
|
#define SCSI_In_DBx__4__PC CYREG_PRT2_PC4
|
|
#define SCSI_In_DBx__4__PORT 2u
|
|
#define SCSI_In_DBx__4__PRT CYREG_PRT2_PRT
|
|
#define SCSI_In_DBx__4__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL
|
|
#define SCSI_In_DBx__4__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN
|
|
#define SCSI_In_DBx__4__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0
|
|
#define SCSI_In_DBx__4__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1
|
|
#define SCSI_In_DBx__4__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0
|
|
#define SCSI_In_DBx__4__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1
|
|
#define SCSI_In_DBx__4__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT
|
|
#define SCSI_In_DBx__4__PS CYREG_PRT2_PS
|
|
#define SCSI_In_DBx__4__SHIFT 4
|
|
#define SCSI_In_DBx__4__SLW CYREG_PRT2_SLW
|
|
#define SCSI_In_DBx__5__AG CYREG_PRT2_AG
|
|
#define SCSI_In_DBx__5__AMUX CYREG_PRT2_AMUX
|
|
#define SCSI_In_DBx__5__BIE CYREG_PRT2_BIE
|
|
#define SCSI_In_DBx__5__BIT_MASK CYREG_PRT2_BIT_MASK
|
|
#define SCSI_In_DBx__5__BYP CYREG_PRT2_BYP
|
|
#define SCSI_In_DBx__5__CTL CYREG_PRT2_CTL
|
|
#define SCSI_In_DBx__5__DM0 CYREG_PRT2_DM0
|
|
#define SCSI_In_DBx__5__DM1 CYREG_PRT2_DM1
|
|
#define SCSI_In_DBx__5__DM2 CYREG_PRT2_DM2
|
|
#define SCSI_In_DBx__5__DR CYREG_PRT2_DR
|
|
#define SCSI_In_DBx__5__INP_DIS CYREG_PRT2_INP_DIS
|
|
#define SCSI_In_DBx__5__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG
|
|
#define SCSI_In_DBx__5__LCD_EN CYREG_PRT2_LCD_EN
|
|
#define SCSI_In_DBx__5__MASK 0x08u
|
|
#define SCSI_In_DBx__5__PC CYREG_PRT2_PC3
|
|
#define SCSI_In_DBx__5__PORT 2u
|
|
#define SCSI_In_DBx__5__PRT CYREG_PRT2_PRT
|
|
#define SCSI_In_DBx__5__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL
|
|
#define SCSI_In_DBx__5__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN
|
|
#define SCSI_In_DBx__5__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0
|
|
#define SCSI_In_DBx__5__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1
|
|
#define SCSI_In_DBx__5__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0
|
|
#define SCSI_In_DBx__5__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1
|
|
#define SCSI_In_DBx__5__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT
|
|
#define SCSI_In_DBx__5__PS CYREG_PRT2_PS
|
|
#define SCSI_In_DBx__5__SHIFT 3
|
|
#define SCSI_In_DBx__5__SLW CYREG_PRT2_SLW
|
|
#define SCSI_In_DBx__6__AG CYREG_PRT2_AG
|
|
#define SCSI_In_DBx__6__AMUX CYREG_PRT2_AMUX
|
|
#define SCSI_In_DBx__6__BIE CYREG_PRT2_BIE
|
|
#define SCSI_In_DBx__6__BIT_MASK CYREG_PRT2_BIT_MASK
|
|
#define SCSI_In_DBx__6__BYP CYREG_PRT2_BYP
|
|
#define SCSI_In_DBx__6__CTL CYREG_PRT2_CTL
|
|
#define SCSI_In_DBx__6__DM0 CYREG_PRT2_DM0
|
|
#define SCSI_In_DBx__6__DM1 CYREG_PRT2_DM1
|
|
#define SCSI_In_DBx__6__DM2 CYREG_PRT2_DM2
|
|
#define SCSI_In_DBx__6__DR CYREG_PRT2_DR
|
|
#define SCSI_In_DBx__6__INP_DIS CYREG_PRT2_INP_DIS
|
|
#define SCSI_In_DBx__6__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG
|
|
#define SCSI_In_DBx__6__LCD_EN CYREG_PRT2_LCD_EN
|
|
#define SCSI_In_DBx__6__MASK 0x04u
|
|
#define SCSI_In_DBx__6__PC CYREG_PRT2_PC2
|
|
#define SCSI_In_DBx__6__PORT 2u
|
|
#define SCSI_In_DBx__6__PRT CYREG_PRT2_PRT
|
|
#define SCSI_In_DBx__6__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL
|
|
#define SCSI_In_DBx__6__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN
|
|
#define SCSI_In_DBx__6__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0
|
|
#define SCSI_In_DBx__6__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1
|
|
#define SCSI_In_DBx__6__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0
|
|
#define SCSI_In_DBx__6__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1
|
|
#define SCSI_In_DBx__6__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT
|
|
#define SCSI_In_DBx__6__PS CYREG_PRT2_PS
|
|
#define SCSI_In_DBx__6__SHIFT 2
|
|
#define SCSI_In_DBx__6__SLW CYREG_PRT2_SLW
|
|
#define SCSI_In_DBx__7__AG CYREG_PRT2_AG
|
|
#define SCSI_In_DBx__7__AMUX CYREG_PRT2_AMUX
|
|
#define SCSI_In_DBx__7__BIE CYREG_PRT2_BIE
|
|
#define SCSI_In_DBx__7__BIT_MASK CYREG_PRT2_BIT_MASK
|
|
#define SCSI_In_DBx__7__BYP CYREG_PRT2_BYP
|
|
#define SCSI_In_DBx__7__CTL CYREG_PRT2_CTL
|
|
#define SCSI_In_DBx__7__DM0 CYREG_PRT2_DM0
|
|
#define SCSI_In_DBx__7__DM1 CYREG_PRT2_DM1
|
|
#define SCSI_In_DBx__7__DM2 CYREG_PRT2_DM2
|
|
#define SCSI_In_DBx__7__DR CYREG_PRT2_DR
|
|
#define SCSI_In_DBx__7__INP_DIS CYREG_PRT2_INP_DIS
|
|
#define SCSI_In_DBx__7__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG
|
|
#define SCSI_In_DBx__7__LCD_EN CYREG_PRT2_LCD_EN
|
|
#define SCSI_In_DBx__7__MASK 0x02u
|
|
#define SCSI_In_DBx__7__PC CYREG_PRT2_PC1
|
|
#define SCSI_In_DBx__7__PORT 2u
|
|
#define SCSI_In_DBx__7__PRT CYREG_PRT2_PRT
|
|
#define SCSI_In_DBx__7__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL
|
|
#define SCSI_In_DBx__7__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN
|
|
#define SCSI_In_DBx__7__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0
|
|
#define SCSI_In_DBx__7__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1
|
|
#define SCSI_In_DBx__7__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0
|
|
#define SCSI_In_DBx__7__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1
|
|
#define SCSI_In_DBx__7__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT
|
|
#define SCSI_In_DBx__7__PS CYREG_PRT2_PS
|
|
#define SCSI_In_DBx__7__SHIFT 1
|
|
#define SCSI_In_DBx__7__SLW CYREG_PRT2_SLW
|
|
#define SCSI_In_DBx__DB0__AG CYREG_PRT12_AG
|
|
#define SCSI_In_DBx__DB0__BIE CYREG_PRT12_BIE
|
|
#define SCSI_In_DBx__DB0__BIT_MASK CYREG_PRT12_BIT_MASK
|
|
#define SCSI_In_DBx__DB0__BYP CYREG_PRT12_BYP
|
|
#define SCSI_In_DBx__DB0__DM0 CYREG_PRT12_DM0
|
|
#define SCSI_In_DBx__DB0__DM1 CYREG_PRT12_DM1
|
|
#define SCSI_In_DBx__DB0__DM2 CYREG_PRT12_DM2
|
|
#define SCSI_In_DBx__DB0__DR CYREG_PRT12_DR
|
|
#define SCSI_In_DBx__DB0__INP_DIS CYREG_PRT12_INP_DIS
|
|
#define SCSI_In_DBx__DB0__MASK 0x10u
|
|
#define SCSI_In_DBx__DB0__PC CYREG_PRT12_PC4
|
|
#define SCSI_In_DBx__DB0__PORT 12u
|
|
#define SCSI_In_DBx__DB0__PRT CYREG_PRT12_PRT
|
|
#define SCSI_In_DBx__DB0__PRTDSI__DBL_SYNC_IN CYREG_PRT12_DBL_SYNC_IN
|
|
#define SCSI_In_DBx__DB0__PRTDSI__OE_SEL0 CYREG_PRT12_OE_SEL0
|
|
#define SCSI_In_DBx__DB0__PRTDSI__OE_SEL1 CYREG_PRT12_OE_SEL1
|
|
#define SCSI_In_DBx__DB0__PRTDSI__OUT_SEL0 CYREG_PRT12_OUT_SEL0
|
|
#define SCSI_In_DBx__DB0__PRTDSI__OUT_SEL1 CYREG_PRT12_OUT_SEL1
|
|
#define SCSI_In_DBx__DB0__PRTDSI__SYNC_OUT CYREG_PRT12_SYNC_OUT
|
|
#define SCSI_In_DBx__DB0__PS CYREG_PRT12_PS
|
|
#define SCSI_In_DBx__DB0__SHIFT 4
|
|
#define SCSI_In_DBx__DB0__SIO_CFG CYREG_PRT12_SIO_CFG
|
|
#define SCSI_In_DBx__DB0__SIO_DIFF CYREG_PRT12_SIO_DIFF
|
|
#define SCSI_In_DBx__DB0__SIO_HYST_EN CYREG_PRT12_SIO_HYST_EN
|
|
#define SCSI_In_DBx__DB0__SIO_REG_HIFREQ CYREG_PRT12_SIO_REG_HIFREQ
|
|
#define SCSI_In_DBx__DB0__SLW CYREG_PRT12_SLW
|
|
#define SCSI_In_DBx__DB1__AG CYREG_PRT2_AG
|
|
#define SCSI_In_DBx__DB1__AMUX CYREG_PRT2_AMUX
|
|
#define SCSI_In_DBx__DB1__BIE CYREG_PRT2_BIE
|
|
#define SCSI_In_DBx__DB1__BIT_MASK CYREG_PRT2_BIT_MASK
|
|
#define SCSI_In_DBx__DB1__BYP CYREG_PRT2_BYP
|
|
#define SCSI_In_DBx__DB1__CTL CYREG_PRT2_CTL
|
|
#define SCSI_In_DBx__DB1__DM0 CYREG_PRT2_DM0
|
|
#define SCSI_In_DBx__DB1__DM1 CYREG_PRT2_DM1
|
|
#define SCSI_In_DBx__DB1__DM2 CYREG_PRT2_DM2
|
|
#define SCSI_In_DBx__DB1__DR CYREG_PRT2_DR
|
|
#define SCSI_In_DBx__DB1__INP_DIS CYREG_PRT2_INP_DIS
|
|
#define SCSI_In_DBx__DB1__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG
|
|
#define SCSI_In_DBx__DB1__LCD_EN CYREG_PRT2_LCD_EN
|
|
#define SCSI_In_DBx__DB1__MASK 0x80u
|
|
#define SCSI_In_DBx__DB1__PC CYREG_PRT2_PC7
|
|
#define SCSI_In_DBx__DB1__PORT 2u
|
|
#define SCSI_In_DBx__DB1__PRT CYREG_PRT2_PRT
|
|
#define SCSI_In_DBx__DB1__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL
|
|
#define SCSI_In_DBx__DB1__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN
|
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#define SCSI_In_DBx__DB1__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0
|
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#define SCSI_In_DBx__DB1__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1
|
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#define SCSI_In_DBx__DB1__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0
|
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#define SCSI_In_DBx__DB1__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1
|
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#define SCSI_In_DBx__DB1__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT
|
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#define SCSI_In_DBx__DB1__PS CYREG_PRT2_PS
|
|
#define SCSI_In_DBx__DB1__SHIFT 7
|
|
#define SCSI_In_DBx__DB1__SLW CYREG_PRT2_SLW
|
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#define SCSI_In_DBx__DB2__AG CYREG_PRT2_AG
|
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#define SCSI_In_DBx__DB2__AMUX CYREG_PRT2_AMUX
|
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#define SCSI_In_DBx__DB2__BIE CYREG_PRT2_BIE
|
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#define SCSI_In_DBx__DB2__BIT_MASK CYREG_PRT2_BIT_MASK
|
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#define SCSI_In_DBx__DB2__BYP CYREG_PRT2_BYP
|
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#define SCSI_In_DBx__DB2__CTL CYREG_PRT2_CTL
|
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#define SCSI_In_DBx__DB2__DM0 CYREG_PRT2_DM0
|
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#define SCSI_In_DBx__DB2__DM1 CYREG_PRT2_DM1
|
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#define SCSI_In_DBx__DB2__DM2 CYREG_PRT2_DM2
|
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#define SCSI_In_DBx__DB2__DR CYREG_PRT2_DR
|
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#define SCSI_In_DBx__DB2__INP_DIS CYREG_PRT2_INP_DIS
|
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#define SCSI_In_DBx__DB2__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG
|
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#define SCSI_In_DBx__DB2__LCD_EN CYREG_PRT2_LCD_EN
|
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#define SCSI_In_DBx__DB2__MASK 0x40u
|
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#define SCSI_In_DBx__DB2__PC CYREG_PRT2_PC6
|
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#define SCSI_In_DBx__DB2__PORT 2u
|
|
#define SCSI_In_DBx__DB2__PRT CYREG_PRT2_PRT
|
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#define SCSI_In_DBx__DB2__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL
|
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#define SCSI_In_DBx__DB2__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN
|
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#define SCSI_In_DBx__DB2__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0
|
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#define SCSI_In_DBx__DB2__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1
|
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#define SCSI_In_DBx__DB2__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0
|
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#define SCSI_In_DBx__DB2__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1
|
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#define SCSI_In_DBx__DB2__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT
|
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#define SCSI_In_DBx__DB2__PS CYREG_PRT2_PS
|
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#define SCSI_In_DBx__DB2__SHIFT 6
|
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#define SCSI_In_DBx__DB2__SLW CYREG_PRT2_SLW
|
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#define SCSI_In_DBx__DB3__AG CYREG_PRT2_AG
|
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#define SCSI_In_DBx__DB3__AMUX CYREG_PRT2_AMUX
|
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#define SCSI_In_DBx__DB3__BIE CYREG_PRT2_BIE
|
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#define SCSI_In_DBx__DB3__BIT_MASK CYREG_PRT2_BIT_MASK
|
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#define SCSI_In_DBx__DB3__BYP CYREG_PRT2_BYP
|
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#define SCSI_In_DBx__DB3__CTL CYREG_PRT2_CTL
|
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#define SCSI_In_DBx__DB3__DM0 CYREG_PRT2_DM0
|
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#define SCSI_In_DBx__DB3__DM1 CYREG_PRT2_DM1
|
|
#define SCSI_In_DBx__DB3__DM2 CYREG_PRT2_DM2
|
|
#define SCSI_In_DBx__DB3__DR CYREG_PRT2_DR
|
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#define SCSI_In_DBx__DB3__INP_DIS CYREG_PRT2_INP_DIS
|
|
#define SCSI_In_DBx__DB3__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG
|
|
#define SCSI_In_DBx__DB3__LCD_EN CYREG_PRT2_LCD_EN
|
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#define SCSI_In_DBx__DB3__MASK 0x20u
|
|
#define SCSI_In_DBx__DB3__PC CYREG_PRT2_PC5
|
|
#define SCSI_In_DBx__DB3__PORT 2u
|
|
#define SCSI_In_DBx__DB3__PRT CYREG_PRT2_PRT
|
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#define SCSI_In_DBx__DB3__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL
|
|
#define SCSI_In_DBx__DB3__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN
|
|
#define SCSI_In_DBx__DB3__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0
|
|
#define SCSI_In_DBx__DB3__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1
|
|
#define SCSI_In_DBx__DB3__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0
|
|
#define SCSI_In_DBx__DB3__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1
|
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#define SCSI_In_DBx__DB3__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT
|
|
#define SCSI_In_DBx__DB3__PS CYREG_PRT2_PS
|
|
#define SCSI_In_DBx__DB3__SHIFT 5
|
|
#define SCSI_In_DBx__DB3__SLW CYREG_PRT2_SLW
|
|
#define SCSI_In_DBx__DB4__AG CYREG_PRT2_AG
|
|
#define SCSI_In_DBx__DB4__AMUX CYREG_PRT2_AMUX
|
|
#define SCSI_In_DBx__DB4__BIE CYREG_PRT2_BIE
|
|
#define SCSI_In_DBx__DB4__BIT_MASK CYREG_PRT2_BIT_MASK
|
|
#define SCSI_In_DBx__DB4__BYP CYREG_PRT2_BYP
|
|
#define SCSI_In_DBx__DB4__CTL CYREG_PRT2_CTL
|
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#define SCSI_In_DBx__DB4__DM0 CYREG_PRT2_DM0
|
|
#define SCSI_In_DBx__DB4__DM1 CYREG_PRT2_DM1
|
|
#define SCSI_In_DBx__DB4__DM2 CYREG_PRT2_DM2
|
|
#define SCSI_In_DBx__DB4__DR CYREG_PRT2_DR
|
|
#define SCSI_In_DBx__DB4__INP_DIS CYREG_PRT2_INP_DIS
|
|
#define SCSI_In_DBx__DB4__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG
|
|
#define SCSI_In_DBx__DB4__LCD_EN CYREG_PRT2_LCD_EN
|
|
#define SCSI_In_DBx__DB4__MASK 0x10u
|
|
#define SCSI_In_DBx__DB4__PC CYREG_PRT2_PC4
|
|
#define SCSI_In_DBx__DB4__PORT 2u
|
|
#define SCSI_In_DBx__DB4__PRT CYREG_PRT2_PRT
|
|
#define SCSI_In_DBx__DB4__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL
|
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#define SCSI_In_DBx__DB4__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN
|
|
#define SCSI_In_DBx__DB4__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0
|
|
#define SCSI_In_DBx__DB4__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1
|
|
#define SCSI_In_DBx__DB4__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0
|
|
#define SCSI_In_DBx__DB4__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1
|
|
#define SCSI_In_DBx__DB4__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT
|
|
#define SCSI_In_DBx__DB4__PS CYREG_PRT2_PS
|
|
#define SCSI_In_DBx__DB4__SHIFT 4
|
|
#define SCSI_In_DBx__DB4__SLW CYREG_PRT2_SLW
|
|
#define SCSI_In_DBx__DB5__AG CYREG_PRT2_AG
|
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#define SCSI_In_DBx__DB5__AMUX CYREG_PRT2_AMUX
|
|
#define SCSI_In_DBx__DB5__BIE CYREG_PRT2_BIE
|
|
#define SCSI_In_DBx__DB5__BIT_MASK CYREG_PRT2_BIT_MASK
|
|
#define SCSI_In_DBx__DB5__BYP CYREG_PRT2_BYP
|
|
#define SCSI_In_DBx__DB5__CTL CYREG_PRT2_CTL
|
|
#define SCSI_In_DBx__DB5__DM0 CYREG_PRT2_DM0
|
|
#define SCSI_In_DBx__DB5__DM1 CYREG_PRT2_DM1
|
|
#define SCSI_In_DBx__DB5__DM2 CYREG_PRT2_DM2
|
|
#define SCSI_In_DBx__DB5__DR CYREG_PRT2_DR
|
|
#define SCSI_In_DBx__DB5__INP_DIS CYREG_PRT2_INP_DIS
|
|
#define SCSI_In_DBx__DB5__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG
|
|
#define SCSI_In_DBx__DB5__LCD_EN CYREG_PRT2_LCD_EN
|
|
#define SCSI_In_DBx__DB5__MASK 0x08u
|
|
#define SCSI_In_DBx__DB5__PC CYREG_PRT2_PC3
|
|
#define SCSI_In_DBx__DB5__PORT 2u
|
|
#define SCSI_In_DBx__DB5__PRT CYREG_PRT2_PRT
|
|
#define SCSI_In_DBx__DB5__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL
|
|
#define SCSI_In_DBx__DB5__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN
|
|
#define SCSI_In_DBx__DB5__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0
|
|
#define SCSI_In_DBx__DB5__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1
|
|
#define SCSI_In_DBx__DB5__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0
|
|
#define SCSI_In_DBx__DB5__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1
|
|
#define SCSI_In_DBx__DB5__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT
|
|
#define SCSI_In_DBx__DB5__PS CYREG_PRT2_PS
|
|
#define SCSI_In_DBx__DB5__SHIFT 3
|
|
#define SCSI_In_DBx__DB5__SLW CYREG_PRT2_SLW
|
|
#define SCSI_In_DBx__DB6__AG CYREG_PRT2_AG
|
|
#define SCSI_In_DBx__DB6__AMUX CYREG_PRT2_AMUX
|
|
#define SCSI_In_DBx__DB6__BIE CYREG_PRT2_BIE
|
|
#define SCSI_In_DBx__DB6__BIT_MASK CYREG_PRT2_BIT_MASK
|
|
#define SCSI_In_DBx__DB6__BYP CYREG_PRT2_BYP
|
|
#define SCSI_In_DBx__DB6__CTL CYREG_PRT2_CTL
|
|
#define SCSI_In_DBx__DB6__DM0 CYREG_PRT2_DM0
|
|
#define SCSI_In_DBx__DB6__DM1 CYREG_PRT2_DM1
|
|
#define SCSI_In_DBx__DB6__DM2 CYREG_PRT2_DM2
|
|
#define SCSI_In_DBx__DB6__DR CYREG_PRT2_DR
|
|
#define SCSI_In_DBx__DB6__INP_DIS CYREG_PRT2_INP_DIS
|
|
#define SCSI_In_DBx__DB6__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG
|
|
#define SCSI_In_DBx__DB6__LCD_EN CYREG_PRT2_LCD_EN
|
|
#define SCSI_In_DBx__DB6__MASK 0x04u
|
|
#define SCSI_In_DBx__DB6__PC CYREG_PRT2_PC2
|
|
#define SCSI_In_DBx__DB6__PORT 2u
|
|
#define SCSI_In_DBx__DB6__PRT CYREG_PRT2_PRT
|
|
#define SCSI_In_DBx__DB6__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL
|
|
#define SCSI_In_DBx__DB6__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN
|
|
#define SCSI_In_DBx__DB6__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0
|
|
#define SCSI_In_DBx__DB6__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1
|
|
#define SCSI_In_DBx__DB6__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0
|
|
#define SCSI_In_DBx__DB6__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1
|
|
#define SCSI_In_DBx__DB6__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT
|
|
#define SCSI_In_DBx__DB6__PS CYREG_PRT2_PS
|
|
#define SCSI_In_DBx__DB6__SHIFT 2
|
|
#define SCSI_In_DBx__DB6__SLW CYREG_PRT2_SLW
|
|
#define SCSI_In_DBx__DB7__AG CYREG_PRT2_AG
|
|
#define SCSI_In_DBx__DB7__AMUX CYREG_PRT2_AMUX
|
|
#define SCSI_In_DBx__DB7__BIE CYREG_PRT2_BIE
|
|
#define SCSI_In_DBx__DB7__BIT_MASK CYREG_PRT2_BIT_MASK
|
|
#define SCSI_In_DBx__DB7__BYP CYREG_PRT2_BYP
|
|
#define SCSI_In_DBx__DB7__CTL CYREG_PRT2_CTL
|
|
#define SCSI_In_DBx__DB7__DM0 CYREG_PRT2_DM0
|
|
#define SCSI_In_DBx__DB7__DM1 CYREG_PRT2_DM1
|
|
#define SCSI_In_DBx__DB7__DM2 CYREG_PRT2_DM2
|
|
#define SCSI_In_DBx__DB7__DR CYREG_PRT2_DR
|
|
#define SCSI_In_DBx__DB7__INP_DIS CYREG_PRT2_INP_DIS
|
|
#define SCSI_In_DBx__DB7__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG
|
|
#define SCSI_In_DBx__DB7__LCD_EN CYREG_PRT2_LCD_EN
|
|
#define SCSI_In_DBx__DB7__MASK 0x02u
|
|
#define SCSI_In_DBx__DB7__PC CYREG_PRT2_PC1
|
|
#define SCSI_In_DBx__DB7__PORT 2u
|
|
#define SCSI_In_DBx__DB7__PRT CYREG_PRT2_PRT
|
|
#define SCSI_In_DBx__DB7__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL
|
|
#define SCSI_In_DBx__DB7__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN
|
|
#define SCSI_In_DBx__DB7__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0
|
|
#define SCSI_In_DBx__DB7__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1
|
|
#define SCSI_In_DBx__DB7__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0
|
|
#define SCSI_In_DBx__DB7__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1
|
|
#define SCSI_In_DBx__DB7__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT
|
|
#define SCSI_In_DBx__DB7__PS CYREG_PRT2_PS
|
|
#define SCSI_In_DBx__DB7__SHIFT 1
|
|
#define SCSI_In_DBx__DB7__SLW CYREG_PRT2_SLW
|
|
|
|
/* SCSI_RX_DMA */
|
|
#define SCSI_RX_DMA__DRQ_CTL CYREG_IDMUX_DRQ_CTL0
|
|
#define SCSI_RX_DMA__DRQ_NUMBER 0u
|
|
#define SCSI_RX_DMA__NUMBEROF_TDS 0u
|
|
#define SCSI_RX_DMA__PRIORITY 2u
|
|
#define SCSI_RX_DMA__TERMIN_EN 0u
|
|
#define SCSI_RX_DMA__TERMIN_SEL 0u
|
|
#define SCSI_RX_DMA__TERMOUT0_EN 1u
|
|
#define SCSI_RX_DMA__TERMOUT0_SEL 0u
|
|
#define SCSI_RX_DMA__TERMOUT1_EN 0u
|
|
#define SCSI_RX_DMA__TERMOUT1_SEL 0u
|
|
|
|
/* SCSI_TX_DMA */
|
|
#define SCSI_TX_DMA__DRQ_CTL CYREG_IDMUX_DRQ_CTL0
|
|
#define SCSI_TX_DMA__DRQ_NUMBER 1u
|
|
#define SCSI_TX_DMA__NUMBEROF_TDS 0u
|
|
#define SCSI_TX_DMA__PRIORITY 2u
|
|
#define SCSI_TX_DMA__TERMIN_EN 0u
|
|
#define SCSI_TX_DMA__TERMIN_SEL 0u
|
|
#define SCSI_TX_DMA__TERMOUT0_EN 1u
|
|
#define SCSI_TX_DMA__TERMOUT0_SEL 1u
|
|
#define SCSI_TX_DMA__TERMOUT1_EN 0u
|
|
#define SCSI_TX_DMA__TERMOUT1_SEL 0u
|
|
|
|
/* SD_Data_Clk */
|
|
#define SD_Data_Clk__CFG0 CYREG_CLKDIST_DCFG0_CFG0
|
|
#define SD_Data_Clk__CFG1 CYREG_CLKDIST_DCFG0_CFG1
|
|
#define SD_Data_Clk__CFG2 CYREG_CLKDIST_DCFG0_CFG2
|
|
#define SD_Data_Clk__CFG2_SRC_SEL_MASK 0x07u
|
|
#define SD_Data_Clk__INDEX 0x00u
|
|
#define SD_Data_Clk__PM_ACT_CFG CYREG_PM_ACT_CFG2
|
|
#define SD_Data_Clk__PM_ACT_MSK 0x01u
|
|
#define SD_Data_Clk__PM_STBY_CFG CYREG_PM_STBY_CFG2
|
|
#define SD_Data_Clk__PM_STBY_MSK 0x01u
|
|
|
|
/* timer_clock */
|
|
#define timer_clock__CFG0 CYREG_CLKDIST_DCFG2_CFG0
|
|
#define timer_clock__CFG1 CYREG_CLKDIST_DCFG2_CFG1
|
|
#define timer_clock__CFG2 CYREG_CLKDIST_DCFG2_CFG2
|
|
#define timer_clock__CFG2_SRC_SEL_MASK 0x07u
|
|
#define timer_clock__INDEX 0x02u
|
|
#define timer_clock__PM_ACT_CFG CYREG_PM_ACT_CFG2
|
|
#define timer_clock__PM_ACT_MSK 0x04u
|
|
#define timer_clock__PM_STBY_CFG CYREG_PM_STBY_CFG2
|
|
#define timer_clock__PM_STBY_MSK 0x04u
|
|
|
|
/* scsiTarget */
|
|
#define scsiTarget_StatusReg__0__MASK 0x01u
|
|
#define scsiTarget_StatusReg__0__POS 0
|
|
#define scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB11_12_ACTL
|
|
#define scsiTarget_StatusReg__16BIT_STATUS_REG CYREG_B0_UDB11_12_ST
|
|
#define scsiTarget_StatusReg__1__MASK 0x02u
|
|
#define scsiTarget_StatusReg__1__POS 1
|
|
#define scsiTarget_StatusReg__2__MASK 0x04u
|
|
#define scsiTarget_StatusReg__2__POS 2
|
|
#define scsiTarget_StatusReg__3__MASK 0x08u
|
|
#define scsiTarget_StatusReg__3__POS 3
|
|
#define scsiTarget_StatusReg__4__MASK 0x10u
|
|
#define scsiTarget_StatusReg__4__POS 4
|
|
#define scsiTarget_StatusReg__MASK 0x1Fu
|
|
#define scsiTarget_StatusReg__MASK_REG CYREG_B0_UDB11_MSK
|
|
#define scsiTarget_StatusReg__MASK_ST_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL
|
|
#define scsiTarget_StatusReg__PER_ST_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL
|
|
#define scsiTarget_StatusReg__STATUS_AUX_CTL_REG CYREG_B0_UDB11_ACTL
|
|
#define scsiTarget_StatusReg__STATUS_CNT_REG CYREG_B0_UDB11_ST_CTL
|
|
#define scsiTarget_StatusReg__STATUS_CONTROL_REG CYREG_B0_UDB11_ST_CTL
|
|
#define scsiTarget_StatusReg__STATUS_REG CYREG_B0_UDB11_ST
|
|
#define scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB04_05_ACTL
|
|
#define scsiTarget_datapath_PI__16BIT_STATUS_REG CYREG_B0_UDB04_05_ST
|
|
#define scsiTarget_datapath_PI__MASK_REG CYREG_B0_UDB04_MSK
|
|
#define scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG CYREG_B0_UDB04_MSK_ACTL
|
|
#define scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG CYREG_B0_UDB04_MSK_ACTL
|
|
#define scsiTarget_datapath_PI__STATUS_AUX_CTL_REG CYREG_B0_UDB04_ACTL
|
|
#define scsiTarget_datapath_PI__STATUS_CNT_REG CYREG_B0_UDB04_ST_CTL
|
|
#define scsiTarget_datapath_PI__STATUS_CONTROL_REG CYREG_B0_UDB04_ST_CTL
|
|
#define scsiTarget_datapath_PI__STATUS_REG CYREG_B0_UDB04_ST
|
|
#define scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB04_05_ACTL
|
|
#define scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB04_05_CTL
|
|
#define scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB04_05_CTL
|
|
#define scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB04_05_CTL
|
|
#define scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG CYREG_B0_UDB04_05_CTL
|
|
#define scsiTarget_datapath_PO__16BIT_MASK_MASK_REG CYREG_B0_UDB04_05_MSK
|
|
#define scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG CYREG_B0_UDB04_05_MSK
|
|
#define scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG CYREG_B0_UDB04_05_MSK
|
|
#define scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB04_05_MSK
|
|
#define scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG CYREG_B0_UDB04_ACTL
|
|
#define scsiTarget_datapath_PO__CONTROL_REG CYREG_B0_UDB04_CTL
|
|
#define scsiTarget_datapath_PO__CONTROL_ST_REG CYREG_B0_UDB04_ST_CTL
|
|
#define scsiTarget_datapath_PO__COUNT_REG CYREG_B0_UDB04_CTL
|
|
#define scsiTarget_datapath_PO__COUNT_ST_REG CYREG_B0_UDB04_ST_CTL
|
|
#define scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB04_MSK_ACTL
|
|
#define scsiTarget_datapath_PO__PERIOD_REG CYREG_B0_UDB04_MSK
|
|
#define scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG CYREG_B0_UDB04_MSK_ACTL
|
|
#define scsiTarget_datapath__16BIT_A0_REG CYREG_B0_UDB04_05_A0
|
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#define scsiTarget_datapath__16BIT_A1_REG CYREG_B0_UDB04_05_A1
|
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#define scsiTarget_datapath__16BIT_D0_REG CYREG_B0_UDB04_05_D0
|
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#define scsiTarget_datapath__16BIT_D1_REG CYREG_B0_UDB04_05_D1
|
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#define scsiTarget_datapath__16BIT_DP_AUX_CTL_REG CYREG_B0_UDB04_05_ACTL
|
|
#define scsiTarget_datapath__16BIT_F0_REG CYREG_B0_UDB04_05_F0
|
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#define scsiTarget_datapath__16BIT_F1_REG CYREG_B0_UDB04_05_F1
|
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#define scsiTarget_datapath__A0_A1_REG CYREG_B0_UDB04_A0_A1
|
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#define scsiTarget_datapath__A0_REG CYREG_B0_UDB04_A0
|
|
#define scsiTarget_datapath__A1_REG CYREG_B0_UDB04_A1
|
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#define scsiTarget_datapath__D0_D1_REG CYREG_B0_UDB04_D0_D1
|
|
#define scsiTarget_datapath__D0_REG CYREG_B0_UDB04_D0
|
|
#define scsiTarget_datapath__D1_REG CYREG_B0_UDB04_D1
|
|
#define scsiTarget_datapath__DP_AUX_CTL_REG CYREG_B0_UDB04_ACTL
|
|
#define scsiTarget_datapath__F0_F1_REG CYREG_B0_UDB04_F0_F1
|
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#define scsiTarget_datapath__F0_REG CYREG_B0_UDB04_F0
|
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#define scsiTarget_datapath__F1_REG CYREG_B0_UDB04_F1
|
|
#define scsiTarget_datapath__MSK_DP_AUX_CTL_REG CYREG_B0_UDB04_MSK_ACTL
|
|
#define scsiTarget_datapath__PER_DP_AUX_CTL_REG CYREG_B0_UDB04_MSK_ACTL
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|
|
/* USBFS_ep_0 */
|
|
#define USBFS_ep_0__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
|
|
#define USBFS_ep_0__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
|
|
#define USBFS_ep_0__INTC_MASK 0x1000000u
|
|
#define USBFS_ep_0__INTC_NUMBER 24u
|
|
#define USBFS_ep_0__INTC_PRIOR_NUM 7u
|
|
#define USBFS_ep_0__INTC_PRIOR_REG CYREG_NVIC_PRI_24
|
|
#define USBFS_ep_0__INTC_SET_EN_REG CYREG_NVIC_SETENA0
|
|
#define USBFS_ep_0__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
|
|
|
|
/* USBFS_ep_1 */
|
|
#define USBFS_ep_1__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
|
|
#define USBFS_ep_1__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
|
|
#define USBFS_ep_1__INTC_MASK 0x20u
|
|
#define USBFS_ep_1__INTC_NUMBER 5u
|
|
#define USBFS_ep_1__INTC_PRIOR_NUM 7u
|
|
#define USBFS_ep_1__INTC_PRIOR_REG CYREG_NVIC_PRI_5
|
|
#define USBFS_ep_1__INTC_SET_EN_REG CYREG_NVIC_SETENA0
|
|
#define USBFS_ep_1__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
|
|
|
|
/* USBFS_ep_2 */
|
|
#define USBFS_ep_2__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
|
|
#define USBFS_ep_2__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
|
|
#define USBFS_ep_2__INTC_MASK 0x40u
|
|
#define USBFS_ep_2__INTC_NUMBER 6u
|
|
#define USBFS_ep_2__INTC_PRIOR_NUM 7u
|
|
#define USBFS_ep_2__INTC_PRIOR_REG CYREG_NVIC_PRI_6
|
|
#define USBFS_ep_2__INTC_SET_EN_REG CYREG_NVIC_SETENA0
|
|
#define USBFS_ep_2__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
|
|
|
|
/* USBFS_ep_3 */
|
|
#define USBFS_ep_3__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
|
|
#define USBFS_ep_3__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
|
|
#define USBFS_ep_3__INTC_MASK 0x80u
|
|
#define USBFS_ep_3__INTC_NUMBER 7u
|
|
#define USBFS_ep_3__INTC_PRIOR_NUM 7u
|
|
#define USBFS_ep_3__INTC_PRIOR_REG CYREG_NVIC_PRI_7
|
|
#define USBFS_ep_3__INTC_SET_EN_REG CYREG_NVIC_SETENA0
|
|
#define USBFS_ep_3__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
|
|
|
|
/* USBFS_ep_4 */
|
|
#define USBFS_ep_4__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
|
|
#define USBFS_ep_4__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
|
|
#define USBFS_ep_4__INTC_MASK 0x100u
|
|
#define USBFS_ep_4__INTC_NUMBER 8u
|
|
#define USBFS_ep_4__INTC_PRIOR_NUM 7u
|
|
#define USBFS_ep_4__INTC_PRIOR_REG CYREG_NVIC_PRI_8
|
|
#define USBFS_ep_4__INTC_SET_EN_REG CYREG_NVIC_SETENA0
|
|
#define USBFS_ep_4__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
|
|
|
|
/* SD_RX_DMA */
|
|
#define SD_RX_DMA__DRQ_CTL CYREG_IDMUX_DRQ_CTL0
|
|
#define SD_RX_DMA__DRQ_NUMBER 2u
|
|
#define SD_RX_DMA__NUMBEROF_TDS 0u
|
|
#define SD_RX_DMA__PRIORITY 1u
|
|
#define SD_RX_DMA__TERMIN_EN 0u
|
|
#define SD_RX_DMA__TERMIN_SEL 0u
|
|
#define SD_RX_DMA__TERMOUT0_EN 1u
|
|
#define SD_RX_DMA__TERMOUT0_SEL 2u
|
|
#define SD_RX_DMA__TERMOUT1_EN 0u
|
|
#define SD_RX_DMA__TERMOUT1_SEL 0u
|
|
|
|
/* SD_TX_DMA */
|
|
#define SD_TX_DMA__DRQ_CTL CYREG_IDMUX_DRQ_CTL0
|
|
#define SD_TX_DMA__DRQ_NUMBER 3u
|
|
#define SD_TX_DMA__NUMBEROF_TDS 0u
|
|
#define SD_TX_DMA__PRIORITY 2u
|
|
#define SD_TX_DMA__TERMIN_EN 0u
|
|
#define SD_TX_DMA__TERMIN_SEL 0u
|
|
#define SD_TX_DMA__TERMOUT0_EN 1u
|
|
#define SD_TX_DMA__TERMOUT0_SEL 3u
|
|
#define SD_TX_DMA__TERMOUT1_EN 0u
|
|
#define SD_TX_DMA__TERMOUT1_SEL 0u
|
|
|
|
/* USBFS_USB */
|
|
#define USBFS_USB__ARB_CFG CYREG_USB_ARB_CFG
|
|
#define USBFS_USB__ARB_EP1_CFG CYREG_USB_ARB_EP1_CFG
|
|
#define USBFS_USB__ARB_EP1_INT_EN CYREG_USB_ARB_EP1_INT_EN
|
|
#define USBFS_USB__ARB_EP1_SR CYREG_USB_ARB_EP1_SR
|
|
#define USBFS_USB__ARB_EP2_CFG CYREG_USB_ARB_EP2_CFG
|
|
#define USBFS_USB__ARB_EP2_INT_EN CYREG_USB_ARB_EP2_INT_EN
|
|
#define USBFS_USB__ARB_EP2_SR CYREG_USB_ARB_EP2_SR
|
|
#define USBFS_USB__ARB_EP3_CFG CYREG_USB_ARB_EP3_CFG
|
|
#define USBFS_USB__ARB_EP3_INT_EN CYREG_USB_ARB_EP3_INT_EN
|
|
#define USBFS_USB__ARB_EP3_SR CYREG_USB_ARB_EP3_SR
|
|
#define USBFS_USB__ARB_EP4_CFG CYREG_USB_ARB_EP4_CFG
|
|
#define USBFS_USB__ARB_EP4_INT_EN CYREG_USB_ARB_EP4_INT_EN
|
|
#define USBFS_USB__ARB_EP4_SR CYREG_USB_ARB_EP4_SR
|
|
#define USBFS_USB__ARB_EP5_CFG CYREG_USB_ARB_EP5_CFG
|
|
#define USBFS_USB__ARB_EP5_INT_EN CYREG_USB_ARB_EP5_INT_EN
|
|
#define USBFS_USB__ARB_EP5_SR CYREG_USB_ARB_EP5_SR
|
|
#define USBFS_USB__ARB_EP6_CFG CYREG_USB_ARB_EP6_CFG
|
|
#define USBFS_USB__ARB_EP6_INT_EN CYREG_USB_ARB_EP6_INT_EN
|
|
#define USBFS_USB__ARB_EP6_SR CYREG_USB_ARB_EP6_SR
|
|
#define USBFS_USB__ARB_EP7_CFG CYREG_USB_ARB_EP7_CFG
|
|
#define USBFS_USB__ARB_EP7_INT_EN CYREG_USB_ARB_EP7_INT_EN
|
|
#define USBFS_USB__ARB_EP7_SR CYREG_USB_ARB_EP7_SR
|
|
#define USBFS_USB__ARB_EP8_CFG CYREG_USB_ARB_EP8_CFG
|
|
#define USBFS_USB__ARB_EP8_INT_EN CYREG_USB_ARB_EP8_INT_EN
|
|
#define USBFS_USB__ARB_EP8_SR CYREG_USB_ARB_EP8_SR
|
|
#define USBFS_USB__ARB_INT_EN CYREG_USB_ARB_INT_EN
|
|
#define USBFS_USB__ARB_INT_SR CYREG_USB_ARB_INT_SR
|
|
#define USBFS_USB__ARB_RW1_DR CYREG_USB_ARB_RW1_DR
|
|
#define USBFS_USB__ARB_RW1_RA CYREG_USB_ARB_RW1_RA
|
|
#define USBFS_USB__ARB_RW1_RA_MSB CYREG_USB_ARB_RW1_RA_MSB
|
|
#define USBFS_USB__ARB_RW1_WA CYREG_USB_ARB_RW1_WA
|
|
#define USBFS_USB__ARB_RW1_WA_MSB CYREG_USB_ARB_RW1_WA_MSB
|
|
#define USBFS_USB__ARB_RW2_DR CYREG_USB_ARB_RW2_DR
|
|
#define USBFS_USB__ARB_RW2_RA CYREG_USB_ARB_RW2_RA
|
|
#define USBFS_USB__ARB_RW2_RA_MSB CYREG_USB_ARB_RW2_RA_MSB
|
|
#define USBFS_USB__ARB_RW2_WA CYREG_USB_ARB_RW2_WA
|
|
#define USBFS_USB__ARB_RW2_WA_MSB CYREG_USB_ARB_RW2_WA_MSB
|
|
#define USBFS_USB__ARB_RW3_DR CYREG_USB_ARB_RW3_DR
|
|
#define USBFS_USB__ARB_RW3_RA CYREG_USB_ARB_RW3_RA
|
|
#define USBFS_USB__ARB_RW3_RA_MSB CYREG_USB_ARB_RW3_RA_MSB
|
|
#define USBFS_USB__ARB_RW3_WA CYREG_USB_ARB_RW3_WA
|
|
#define USBFS_USB__ARB_RW3_WA_MSB CYREG_USB_ARB_RW3_WA_MSB
|
|
#define USBFS_USB__ARB_RW4_DR CYREG_USB_ARB_RW4_DR
|
|
#define USBFS_USB__ARB_RW4_RA CYREG_USB_ARB_RW4_RA
|
|
#define USBFS_USB__ARB_RW4_RA_MSB CYREG_USB_ARB_RW4_RA_MSB
|
|
#define USBFS_USB__ARB_RW4_WA CYREG_USB_ARB_RW4_WA
|
|
#define USBFS_USB__ARB_RW4_WA_MSB CYREG_USB_ARB_RW4_WA_MSB
|
|
#define USBFS_USB__ARB_RW5_DR CYREG_USB_ARB_RW5_DR
|
|
#define USBFS_USB__ARB_RW5_RA CYREG_USB_ARB_RW5_RA
|
|
#define USBFS_USB__ARB_RW5_RA_MSB CYREG_USB_ARB_RW5_RA_MSB
|
|
#define USBFS_USB__ARB_RW5_WA CYREG_USB_ARB_RW5_WA
|
|
#define USBFS_USB__ARB_RW5_WA_MSB CYREG_USB_ARB_RW5_WA_MSB
|
|
#define USBFS_USB__ARB_RW6_DR CYREG_USB_ARB_RW6_DR
|
|
#define USBFS_USB__ARB_RW6_RA CYREG_USB_ARB_RW6_RA
|
|
#define USBFS_USB__ARB_RW6_RA_MSB CYREG_USB_ARB_RW6_RA_MSB
|
|
#define USBFS_USB__ARB_RW6_WA CYREG_USB_ARB_RW6_WA
|
|
#define USBFS_USB__ARB_RW6_WA_MSB CYREG_USB_ARB_RW6_WA_MSB
|
|
#define USBFS_USB__ARB_RW7_DR CYREG_USB_ARB_RW7_DR
|
|
#define USBFS_USB__ARB_RW7_RA CYREG_USB_ARB_RW7_RA
|
|
#define USBFS_USB__ARB_RW7_RA_MSB CYREG_USB_ARB_RW7_RA_MSB
|
|
#define USBFS_USB__ARB_RW7_WA CYREG_USB_ARB_RW7_WA
|
|
#define USBFS_USB__ARB_RW7_WA_MSB CYREG_USB_ARB_RW7_WA_MSB
|
|
#define USBFS_USB__ARB_RW8_DR CYREG_USB_ARB_RW8_DR
|
|
#define USBFS_USB__ARB_RW8_RA CYREG_USB_ARB_RW8_RA
|
|
#define USBFS_USB__ARB_RW8_RA_MSB CYREG_USB_ARB_RW8_RA_MSB
|
|
#define USBFS_USB__ARB_RW8_WA CYREG_USB_ARB_RW8_WA
|
|
#define USBFS_USB__ARB_RW8_WA_MSB CYREG_USB_ARB_RW8_WA_MSB
|
|
#define USBFS_USB__BUF_SIZE CYREG_USB_BUF_SIZE
|
|
#define USBFS_USB__BUS_RST_CNT CYREG_USB_BUS_RST_CNT
|
|
#define USBFS_USB__CR0 CYREG_USB_CR0
|
|
#define USBFS_USB__CR1 CYREG_USB_CR1
|
|
#define USBFS_USB__CWA CYREG_USB_CWA
|
|
#define USBFS_USB__CWA_MSB CYREG_USB_CWA_MSB
|
|
#define USBFS_USB__DMA_THRES CYREG_USB_DMA_THRES
|
|
#define USBFS_USB__DMA_THRES_MSB CYREG_USB_DMA_THRES_MSB
|
|
#define USBFS_USB__DYN_RECONFIG CYREG_USB_DYN_RECONFIG
|
|
#define USBFS_USB__EP0_CNT CYREG_USB_EP0_CNT
|
|
#define USBFS_USB__EP0_CR CYREG_USB_EP0_CR
|
|
#define USBFS_USB__EP0_DR0 CYREG_USB_EP0_DR0
|
|
#define USBFS_USB__EP0_DR1 CYREG_USB_EP0_DR1
|
|
#define USBFS_USB__EP0_DR2 CYREG_USB_EP0_DR2
|
|
#define USBFS_USB__EP0_DR3 CYREG_USB_EP0_DR3
|
|
#define USBFS_USB__EP0_DR4 CYREG_USB_EP0_DR4
|
|
#define USBFS_USB__EP0_DR5 CYREG_USB_EP0_DR5
|
|
#define USBFS_USB__EP0_DR6 CYREG_USB_EP0_DR6
|
|
#define USBFS_USB__EP0_DR7 CYREG_USB_EP0_DR7
|
|
#define USBFS_USB__EP_ACTIVE CYREG_USB_EP_ACTIVE
|
|
#define USBFS_USB__EP_TYPE CYREG_USB_EP_TYPE
|
|
#define USBFS_USB__MEM_DATA CYREG_USB_MEM_DATA_MBASE
|
|
#define USBFS_USB__PM_ACT_CFG CYREG_PM_ACT_CFG5
|
|
#define USBFS_USB__PM_ACT_MSK 0x01u
|
|
#define USBFS_USB__PM_STBY_CFG CYREG_PM_STBY_CFG5
|
|
#define USBFS_USB__PM_STBY_MSK 0x01u
|
|
#define USBFS_USB__SIE_EP1_CNT0 CYREG_USB_SIE_EP1_CNT0
|
|
#define USBFS_USB__SIE_EP1_CNT1 CYREG_USB_SIE_EP1_CNT1
|
|
#define USBFS_USB__SIE_EP1_CR0 CYREG_USB_SIE_EP1_CR0
|
|
#define USBFS_USB__SIE_EP2_CNT0 CYREG_USB_SIE_EP2_CNT0
|
|
#define USBFS_USB__SIE_EP2_CNT1 CYREG_USB_SIE_EP2_CNT1
|
|
#define USBFS_USB__SIE_EP2_CR0 CYREG_USB_SIE_EP2_CR0
|
|
#define USBFS_USB__SIE_EP3_CNT0 CYREG_USB_SIE_EP3_CNT0
|
|
#define USBFS_USB__SIE_EP3_CNT1 CYREG_USB_SIE_EP3_CNT1
|
|
#define USBFS_USB__SIE_EP3_CR0 CYREG_USB_SIE_EP3_CR0
|
|
#define USBFS_USB__SIE_EP4_CNT0 CYREG_USB_SIE_EP4_CNT0
|
|
#define USBFS_USB__SIE_EP4_CNT1 CYREG_USB_SIE_EP4_CNT1
|
|
#define USBFS_USB__SIE_EP4_CR0 CYREG_USB_SIE_EP4_CR0
|
|
#define USBFS_USB__SIE_EP5_CNT0 CYREG_USB_SIE_EP5_CNT0
|
|
#define USBFS_USB__SIE_EP5_CNT1 CYREG_USB_SIE_EP5_CNT1
|
|
#define USBFS_USB__SIE_EP5_CR0 CYREG_USB_SIE_EP5_CR0
|
|
#define USBFS_USB__SIE_EP6_CNT0 CYREG_USB_SIE_EP6_CNT0
|
|
#define USBFS_USB__SIE_EP6_CNT1 CYREG_USB_SIE_EP6_CNT1
|
|
#define USBFS_USB__SIE_EP6_CR0 CYREG_USB_SIE_EP6_CR0
|
|
#define USBFS_USB__SIE_EP7_CNT0 CYREG_USB_SIE_EP7_CNT0
|
|
#define USBFS_USB__SIE_EP7_CNT1 CYREG_USB_SIE_EP7_CNT1
|
|
#define USBFS_USB__SIE_EP7_CR0 CYREG_USB_SIE_EP7_CR0
|
|
#define USBFS_USB__SIE_EP8_CNT0 CYREG_USB_SIE_EP8_CNT0
|
|
#define USBFS_USB__SIE_EP8_CNT1 CYREG_USB_SIE_EP8_CNT1
|
|
#define USBFS_USB__SIE_EP8_CR0 CYREG_USB_SIE_EP8_CR0
|
|
#define USBFS_USB__SIE_EP_INT_EN CYREG_USB_SIE_EP_INT_EN
|
|
#define USBFS_USB__SIE_EP_INT_SR CYREG_USB_SIE_EP_INT_SR
|
|
#define USBFS_USB__SOF0 CYREG_USB_SOF0
|
|
#define USBFS_USB__SOF1 CYREG_USB_SOF1
|
|
#define USBFS_USB__USBIO_CR0 CYREG_USB_USBIO_CR0
|
|
#define USBFS_USB__USBIO_CR1 CYREG_USB_USBIO_CR1
|
|
#define USBFS_USB__USB_CLK_EN CYREG_USB_USB_CLK_EN
|
|
|
|
/* SCSI_ATN */
|
|
#define SCSI_ATN__0__MASK 0x20u
|
|
#define SCSI_ATN__0__PC CYREG_PRT12_PC5
|
|
#define SCSI_ATN__0__PORT 12u
|
|
#define SCSI_ATN__0__SHIFT 5
|
|
#define SCSI_ATN__AG CYREG_PRT12_AG
|
|
#define SCSI_ATN__BIE CYREG_PRT12_BIE
|
|
#define SCSI_ATN__BIT_MASK CYREG_PRT12_BIT_MASK
|
|
#define SCSI_ATN__BYP CYREG_PRT12_BYP
|
|
#define SCSI_ATN__DM0 CYREG_PRT12_DM0
|
|
#define SCSI_ATN__DM1 CYREG_PRT12_DM1
|
|
#define SCSI_ATN__DM2 CYREG_PRT12_DM2
|
|
#define SCSI_ATN__DR CYREG_PRT12_DR
|
|
#define SCSI_ATN__INP_DIS CYREG_PRT12_INP_DIS
|
|
#define SCSI_ATN__INT__MASK 0x20u
|
|
#define SCSI_ATN__INT__PC CYREG_PRT12_PC5
|
|
#define SCSI_ATN__INT__PORT 12u
|
|
#define SCSI_ATN__INT__SHIFT 5
|
|
#define SCSI_ATN__MASK 0x20u
|
|
#define SCSI_ATN__PORT 12u
|
|
#define SCSI_ATN__PRT CYREG_PRT12_PRT
|
|
#define SCSI_ATN__PRTDSI__DBL_SYNC_IN CYREG_PRT12_DBL_SYNC_IN
|
|
#define SCSI_ATN__PRTDSI__OE_SEL0 CYREG_PRT12_OE_SEL0
|
|
#define SCSI_ATN__PRTDSI__OE_SEL1 CYREG_PRT12_OE_SEL1
|
|
#define SCSI_ATN__PRTDSI__OUT_SEL0 CYREG_PRT12_OUT_SEL0
|
|
#define SCSI_ATN__PRTDSI__OUT_SEL1 CYREG_PRT12_OUT_SEL1
|
|
#define SCSI_ATN__PRTDSI__SYNC_OUT CYREG_PRT12_SYNC_OUT
|
|
#define SCSI_ATN__PS CYREG_PRT12_PS
|
|
#define SCSI_ATN__SHIFT 5
|
|
#define SCSI_ATN__SIO_CFG CYREG_PRT12_SIO_CFG
|
|
#define SCSI_ATN__SIO_DIFF CYREG_PRT12_SIO_DIFF
|
|
#define SCSI_ATN__SIO_HYST_EN CYREG_PRT12_SIO_HYST_EN
|
|
#define SCSI_ATN__SIO_REG_HIFREQ CYREG_PRT12_SIO_REG_HIFREQ
|
|
#define SCSI_ATN__SLW CYREG_PRT12_SLW
|
|
|
|
/* SCSI_CLK */
|
|
#define SCSI_CLK__CFG0 CYREG_CLKDIST_DCFG1_CFG0
|
|
#define SCSI_CLK__CFG1 CYREG_CLKDIST_DCFG1_CFG1
|
|
#define SCSI_CLK__CFG2 CYREG_CLKDIST_DCFG1_CFG2
|
|
#define SCSI_CLK__CFG2_SRC_SEL_MASK 0x07u
|
|
#define SCSI_CLK__INDEX 0x01u
|
|
#define SCSI_CLK__PM_ACT_CFG CYREG_PM_ACT_CFG2
|
|
#define SCSI_CLK__PM_ACT_MSK 0x02u
|
|
#define SCSI_CLK__PM_STBY_CFG CYREG_PM_STBY_CFG2
|
|
#define SCSI_CLK__PM_STBY_MSK 0x02u
|
|
|
|
/* SCSI_Out */
|
|
#define SCSI_Out__0__AG CYREG_PRT4_AG
|
|
#define SCSI_Out__0__AMUX CYREG_PRT4_AMUX
|
|
#define SCSI_Out__0__BIE CYREG_PRT4_BIE
|
|
#define SCSI_Out__0__BIT_MASK CYREG_PRT4_BIT_MASK
|
|
#define SCSI_Out__0__BYP CYREG_PRT4_BYP
|
|
#define SCSI_Out__0__CTL CYREG_PRT4_CTL
|
|
#define SCSI_Out__0__DM0 CYREG_PRT4_DM0
|
|
#define SCSI_Out__0__DM1 CYREG_PRT4_DM1
|
|
#define SCSI_Out__0__DM2 CYREG_PRT4_DM2
|
|
#define SCSI_Out__0__DR CYREG_PRT4_DR
|
|
#define SCSI_Out__0__INP_DIS CYREG_PRT4_INP_DIS
|
|
#define SCSI_Out__0__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG
|
|
#define SCSI_Out__0__LCD_EN CYREG_PRT4_LCD_EN
|
|
#define SCSI_Out__0__MASK 0x08u
|
|
#define SCSI_Out__0__PC CYREG_PRT4_PC3
|
|
#define SCSI_Out__0__PORT 4u
|
|
#define SCSI_Out__0__PRT CYREG_PRT4_PRT
|
|
#define SCSI_Out__0__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL
|
|
#define SCSI_Out__0__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN
|
|
#define SCSI_Out__0__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0
|
|
#define SCSI_Out__0__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1
|
|
#define SCSI_Out__0__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0
|
|
#define SCSI_Out__0__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1
|
|
#define SCSI_Out__0__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT
|
|
#define SCSI_Out__0__PS CYREG_PRT4_PS
|
|
#define SCSI_Out__0__SHIFT 3
|
|
#define SCSI_Out__0__SLW CYREG_PRT4_SLW
|
|
#define SCSI_Out__1__AG CYREG_PRT4_AG
|
|
#define SCSI_Out__1__AMUX CYREG_PRT4_AMUX
|
|
#define SCSI_Out__1__BIE CYREG_PRT4_BIE
|
|
#define SCSI_Out__1__BIT_MASK CYREG_PRT4_BIT_MASK
|
|
#define SCSI_Out__1__BYP CYREG_PRT4_BYP
|
|
#define SCSI_Out__1__CTL CYREG_PRT4_CTL
|
|
#define SCSI_Out__1__DM0 CYREG_PRT4_DM0
|
|
#define SCSI_Out__1__DM1 CYREG_PRT4_DM1
|
|
#define SCSI_Out__1__DM2 CYREG_PRT4_DM2
|
|
#define SCSI_Out__1__DR CYREG_PRT4_DR
|
|
#define SCSI_Out__1__INP_DIS CYREG_PRT4_INP_DIS
|
|
#define SCSI_Out__1__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG
|
|
#define SCSI_Out__1__LCD_EN CYREG_PRT4_LCD_EN
|
|
#define SCSI_Out__1__MASK 0x04u
|
|
#define SCSI_Out__1__PC CYREG_PRT4_PC2
|
|
#define SCSI_Out__1__PORT 4u
|
|
#define SCSI_Out__1__PRT CYREG_PRT4_PRT
|
|
#define SCSI_Out__1__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL
|
|
#define SCSI_Out__1__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN
|
|
#define SCSI_Out__1__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0
|
|
#define SCSI_Out__1__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1
|
|
#define SCSI_Out__1__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0
|
|
#define SCSI_Out__1__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1
|
|
#define SCSI_Out__1__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT
|
|
#define SCSI_Out__1__PS CYREG_PRT4_PS
|
|
#define SCSI_Out__1__SHIFT 2
|
|
#define SCSI_Out__1__SLW CYREG_PRT4_SLW
|
|
#define SCSI_Out__2__AG CYREG_PRT0_AG
|
|
#define SCSI_Out__2__AMUX CYREG_PRT0_AMUX
|
|
#define SCSI_Out__2__BIE CYREG_PRT0_BIE
|
|
#define SCSI_Out__2__BIT_MASK CYREG_PRT0_BIT_MASK
|
|
#define SCSI_Out__2__BYP CYREG_PRT0_BYP
|
|
#define SCSI_Out__2__CTL CYREG_PRT0_CTL
|
|
#define SCSI_Out__2__DM0 CYREG_PRT0_DM0
|
|
#define SCSI_Out__2__DM1 CYREG_PRT0_DM1
|
|
#define SCSI_Out__2__DM2 CYREG_PRT0_DM2
|
|
#define SCSI_Out__2__DR CYREG_PRT0_DR
|
|
#define SCSI_Out__2__INP_DIS CYREG_PRT0_INP_DIS
|
|
#define SCSI_Out__2__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG
|
|
#define SCSI_Out__2__LCD_EN CYREG_PRT0_LCD_EN
|
|
#define SCSI_Out__2__MASK 0x80u
|
|
#define SCSI_Out__2__PC CYREG_PRT0_PC7
|
|
#define SCSI_Out__2__PORT 0u
|
|
#define SCSI_Out__2__PRT CYREG_PRT0_PRT
|
|
#define SCSI_Out__2__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL
|
|
#define SCSI_Out__2__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN
|
|
#define SCSI_Out__2__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0
|
|
#define SCSI_Out__2__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1
|
|
#define SCSI_Out__2__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0
|
|
#define SCSI_Out__2__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1
|
|
#define SCSI_Out__2__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT
|
|
#define SCSI_Out__2__PS CYREG_PRT0_PS
|
|
#define SCSI_Out__2__SHIFT 7
|
|
#define SCSI_Out__2__SLW CYREG_PRT0_SLW
|
|
#define SCSI_Out__3__AG CYREG_PRT0_AG
|
|
#define SCSI_Out__3__AMUX CYREG_PRT0_AMUX
|
|
#define SCSI_Out__3__BIE CYREG_PRT0_BIE
|
|
#define SCSI_Out__3__BIT_MASK CYREG_PRT0_BIT_MASK
|
|
#define SCSI_Out__3__BYP CYREG_PRT0_BYP
|
|
#define SCSI_Out__3__CTL CYREG_PRT0_CTL
|
|
#define SCSI_Out__3__DM0 CYREG_PRT0_DM0
|
|
#define SCSI_Out__3__DM1 CYREG_PRT0_DM1
|
|
#define SCSI_Out__3__DM2 CYREG_PRT0_DM2
|
|
#define SCSI_Out__3__DR CYREG_PRT0_DR
|
|
#define SCSI_Out__3__INP_DIS CYREG_PRT0_INP_DIS
|
|
#define SCSI_Out__3__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG
|
|
#define SCSI_Out__3__LCD_EN CYREG_PRT0_LCD_EN
|
|
#define SCSI_Out__3__MASK 0x40u
|
|
#define SCSI_Out__3__PC CYREG_PRT0_PC6
|
|
#define SCSI_Out__3__PORT 0u
|
|
#define SCSI_Out__3__PRT CYREG_PRT0_PRT
|
|
#define SCSI_Out__3__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL
|
|
#define SCSI_Out__3__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN
|
|
#define SCSI_Out__3__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0
|
|
#define SCSI_Out__3__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1
|
|
#define SCSI_Out__3__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0
|
|
#define SCSI_Out__3__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1
|
|
#define SCSI_Out__3__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT
|
|
#define SCSI_Out__3__PS CYREG_PRT0_PS
|
|
#define SCSI_Out__3__SHIFT 6
|
|
#define SCSI_Out__3__SLW CYREG_PRT0_SLW
|
|
#define SCSI_Out__4__AG CYREG_PRT0_AG
|
|
#define SCSI_Out__4__AMUX CYREG_PRT0_AMUX
|
|
#define SCSI_Out__4__BIE CYREG_PRT0_BIE
|
|
#define SCSI_Out__4__BIT_MASK CYREG_PRT0_BIT_MASK
|
|
#define SCSI_Out__4__BYP CYREG_PRT0_BYP
|
|
#define SCSI_Out__4__CTL CYREG_PRT0_CTL
|
|
#define SCSI_Out__4__DM0 CYREG_PRT0_DM0
|
|
#define SCSI_Out__4__DM1 CYREG_PRT0_DM1
|
|
#define SCSI_Out__4__DM2 CYREG_PRT0_DM2
|
|
#define SCSI_Out__4__DR CYREG_PRT0_DR
|
|
#define SCSI_Out__4__INP_DIS CYREG_PRT0_INP_DIS
|
|
#define SCSI_Out__4__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG
|
|
#define SCSI_Out__4__LCD_EN CYREG_PRT0_LCD_EN
|
|
#define SCSI_Out__4__MASK 0x20u
|
|
#define SCSI_Out__4__PC CYREG_PRT0_PC5
|
|
#define SCSI_Out__4__PORT 0u
|
|
#define SCSI_Out__4__PRT CYREG_PRT0_PRT
|
|
#define SCSI_Out__4__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL
|
|
#define SCSI_Out__4__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN
|
|
#define SCSI_Out__4__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0
|
|
#define SCSI_Out__4__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1
|
|
#define SCSI_Out__4__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0
|
|
#define SCSI_Out__4__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1
|
|
#define SCSI_Out__4__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT
|
|
#define SCSI_Out__4__PS CYREG_PRT0_PS
|
|
#define SCSI_Out__4__SHIFT 5
|
|
#define SCSI_Out__4__SLW CYREG_PRT0_SLW
|
|
#define SCSI_Out__5__AG CYREG_PRT0_AG
|
|
#define SCSI_Out__5__AMUX CYREG_PRT0_AMUX
|
|
#define SCSI_Out__5__BIE CYREG_PRT0_BIE
|
|
#define SCSI_Out__5__BIT_MASK CYREG_PRT0_BIT_MASK
|
|
#define SCSI_Out__5__BYP CYREG_PRT0_BYP
|
|
#define SCSI_Out__5__CTL CYREG_PRT0_CTL
|
|
#define SCSI_Out__5__DM0 CYREG_PRT0_DM0
|
|
#define SCSI_Out__5__DM1 CYREG_PRT0_DM1
|
|
#define SCSI_Out__5__DM2 CYREG_PRT0_DM2
|
|
#define SCSI_Out__5__DR CYREG_PRT0_DR
|
|
#define SCSI_Out__5__INP_DIS CYREG_PRT0_INP_DIS
|
|
#define SCSI_Out__5__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG
|
|
#define SCSI_Out__5__LCD_EN CYREG_PRT0_LCD_EN
|
|
#define SCSI_Out__5__MASK 0x10u
|
|
#define SCSI_Out__5__PC CYREG_PRT0_PC4
|
|
#define SCSI_Out__5__PORT 0u
|
|
#define SCSI_Out__5__PRT CYREG_PRT0_PRT
|
|
#define SCSI_Out__5__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL
|
|
#define SCSI_Out__5__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN
|
|
#define SCSI_Out__5__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0
|
|
#define SCSI_Out__5__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1
|
|
#define SCSI_Out__5__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0
|
|
#define SCSI_Out__5__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1
|
|
#define SCSI_Out__5__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT
|
|
#define SCSI_Out__5__PS CYREG_PRT0_PS
|
|
#define SCSI_Out__5__SHIFT 4
|
|
#define SCSI_Out__5__SLW CYREG_PRT0_SLW
|
|
#define SCSI_Out__6__AG CYREG_PRT0_AG
|
|
#define SCSI_Out__6__AMUX CYREG_PRT0_AMUX
|
|
#define SCSI_Out__6__BIE CYREG_PRT0_BIE
|
|
#define SCSI_Out__6__BIT_MASK CYREG_PRT0_BIT_MASK
|
|
#define SCSI_Out__6__BYP CYREG_PRT0_BYP
|
|
#define SCSI_Out__6__CTL CYREG_PRT0_CTL
|
|
#define SCSI_Out__6__DM0 CYREG_PRT0_DM0
|
|
#define SCSI_Out__6__DM1 CYREG_PRT0_DM1
|
|
#define SCSI_Out__6__DM2 CYREG_PRT0_DM2
|
|
#define SCSI_Out__6__DR CYREG_PRT0_DR
|
|
#define SCSI_Out__6__INP_DIS CYREG_PRT0_INP_DIS
|
|
#define SCSI_Out__6__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG
|
|
#define SCSI_Out__6__LCD_EN CYREG_PRT0_LCD_EN
|
|
#define SCSI_Out__6__MASK 0x08u
|
|
#define SCSI_Out__6__PC CYREG_PRT0_PC3
|
|
#define SCSI_Out__6__PORT 0u
|
|
#define SCSI_Out__6__PRT CYREG_PRT0_PRT
|
|
#define SCSI_Out__6__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL
|
|
#define SCSI_Out__6__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN
|
|
#define SCSI_Out__6__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0
|
|
#define SCSI_Out__6__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1
|
|
#define SCSI_Out__6__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0
|
|
#define SCSI_Out__6__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1
|
|
#define SCSI_Out__6__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT
|
|
#define SCSI_Out__6__PS CYREG_PRT0_PS
|
|
#define SCSI_Out__6__SHIFT 3
|
|
#define SCSI_Out__6__SLW CYREG_PRT0_SLW
|
|
#define SCSI_Out__7__AG CYREG_PRT0_AG
|
|
#define SCSI_Out__7__AMUX CYREG_PRT0_AMUX
|
|
#define SCSI_Out__7__BIE CYREG_PRT0_BIE
|
|
#define SCSI_Out__7__BIT_MASK CYREG_PRT0_BIT_MASK
|
|
#define SCSI_Out__7__BYP CYREG_PRT0_BYP
|
|
#define SCSI_Out__7__CTL CYREG_PRT0_CTL
|
|
#define SCSI_Out__7__DM0 CYREG_PRT0_DM0
|
|
#define SCSI_Out__7__DM1 CYREG_PRT0_DM1
|
|
#define SCSI_Out__7__DM2 CYREG_PRT0_DM2
|
|
#define SCSI_Out__7__DR CYREG_PRT0_DR
|
|
#define SCSI_Out__7__INP_DIS CYREG_PRT0_INP_DIS
|
|
#define SCSI_Out__7__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG
|
|
#define SCSI_Out__7__LCD_EN CYREG_PRT0_LCD_EN
|
|
#define SCSI_Out__7__MASK 0x04u
|
|
#define SCSI_Out__7__PC CYREG_PRT0_PC2
|
|
#define SCSI_Out__7__PORT 0u
|
|
#define SCSI_Out__7__PRT CYREG_PRT0_PRT
|
|
#define SCSI_Out__7__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL
|
|
#define SCSI_Out__7__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN
|
|
#define SCSI_Out__7__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0
|
|
#define SCSI_Out__7__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1
|
|
#define SCSI_Out__7__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0
|
|
#define SCSI_Out__7__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1
|
|
#define SCSI_Out__7__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT
|
|
#define SCSI_Out__7__PS CYREG_PRT0_PS
|
|
#define SCSI_Out__7__SHIFT 2
|
|
#define SCSI_Out__7__SLW CYREG_PRT0_SLW
|
|
#define SCSI_Out__8__AG CYREG_PRT0_AG
|
|
#define SCSI_Out__8__AMUX CYREG_PRT0_AMUX
|
|
#define SCSI_Out__8__BIE CYREG_PRT0_BIE
|
|
#define SCSI_Out__8__BIT_MASK CYREG_PRT0_BIT_MASK
|
|
#define SCSI_Out__8__BYP CYREG_PRT0_BYP
|
|
#define SCSI_Out__8__CTL CYREG_PRT0_CTL
|
|
#define SCSI_Out__8__DM0 CYREG_PRT0_DM0
|
|
#define SCSI_Out__8__DM1 CYREG_PRT0_DM1
|
|
#define SCSI_Out__8__DM2 CYREG_PRT0_DM2
|
|
#define SCSI_Out__8__DR CYREG_PRT0_DR
|
|
#define SCSI_Out__8__INP_DIS CYREG_PRT0_INP_DIS
|
|
#define SCSI_Out__8__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG
|
|
#define SCSI_Out__8__LCD_EN CYREG_PRT0_LCD_EN
|
|
#define SCSI_Out__8__MASK 0x02u
|
|
#define SCSI_Out__8__PC CYREG_PRT0_PC1
|
|
#define SCSI_Out__8__PORT 0u
|
|
#define SCSI_Out__8__PRT CYREG_PRT0_PRT
|
|
#define SCSI_Out__8__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL
|
|
#define SCSI_Out__8__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN
|
|
#define SCSI_Out__8__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0
|
|
#define SCSI_Out__8__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1
|
|
#define SCSI_Out__8__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0
|
|
#define SCSI_Out__8__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1
|
|
#define SCSI_Out__8__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT
|
|
#define SCSI_Out__8__PS CYREG_PRT0_PS
|
|
#define SCSI_Out__8__SHIFT 1
|
|
#define SCSI_Out__8__SLW CYREG_PRT0_SLW
|
|
#define SCSI_Out__9__AG CYREG_PRT0_AG
|
|
#define SCSI_Out__9__AMUX CYREG_PRT0_AMUX
|
|
#define SCSI_Out__9__BIE CYREG_PRT0_BIE
|
|
#define SCSI_Out__9__BIT_MASK CYREG_PRT0_BIT_MASK
|
|
#define SCSI_Out__9__BYP CYREG_PRT0_BYP
|
|
#define SCSI_Out__9__CTL CYREG_PRT0_CTL
|
|
#define SCSI_Out__9__DM0 CYREG_PRT0_DM0
|
|
#define SCSI_Out__9__DM1 CYREG_PRT0_DM1
|
|
#define SCSI_Out__9__DM2 CYREG_PRT0_DM2
|
|
#define SCSI_Out__9__DR CYREG_PRT0_DR
|
|
#define SCSI_Out__9__INP_DIS CYREG_PRT0_INP_DIS
|
|
#define SCSI_Out__9__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG
|
|
#define SCSI_Out__9__LCD_EN CYREG_PRT0_LCD_EN
|
|
#define SCSI_Out__9__MASK 0x01u
|
|
#define SCSI_Out__9__PC CYREG_PRT0_PC0
|
|
#define SCSI_Out__9__PORT 0u
|
|
#define SCSI_Out__9__PRT CYREG_PRT0_PRT
|
|
#define SCSI_Out__9__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL
|
|
#define SCSI_Out__9__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN
|
|
#define SCSI_Out__9__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0
|
|
#define SCSI_Out__9__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1
|
|
#define SCSI_Out__9__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0
|
|
#define SCSI_Out__9__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1
|
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#define SCSI_Out__9__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT
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#define SCSI_Out__9__PS CYREG_PRT0_PS
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#define SCSI_Out__9__SHIFT 0
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#define SCSI_Out__9__SLW CYREG_PRT0_SLW
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#define SCSI_Out__ACK__AG CYREG_PRT0_AG
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#define SCSI_Out__ACK__AMUX CYREG_PRT0_AMUX
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#define SCSI_Out__ACK__BIE CYREG_PRT0_BIE
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#define SCSI_Out__ACK__BIT_MASK CYREG_PRT0_BIT_MASK
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#define SCSI_Out__ACK__BYP CYREG_PRT0_BYP
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#define SCSI_Out__ACK__CTL CYREG_PRT0_CTL
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#define SCSI_Out__ACK__DM0 CYREG_PRT0_DM0
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#define SCSI_Out__ACK__DM1 CYREG_PRT0_DM1
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#define SCSI_Out__ACK__DM2 CYREG_PRT0_DM2
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#define SCSI_Out__ACK__DR CYREG_PRT0_DR
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#define SCSI_Out__ACK__INP_DIS CYREG_PRT0_INP_DIS
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#define SCSI_Out__ACK__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG
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#define SCSI_Out__ACK__LCD_EN CYREG_PRT0_LCD_EN
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#define SCSI_Out__ACK__MASK 0x40u
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#define SCSI_Out__ACK__PC CYREG_PRT0_PC6
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#define SCSI_Out__ACK__PORT 0u
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#define SCSI_Out__ACK__PRT CYREG_PRT0_PRT
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#define SCSI_Out__ACK__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL
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#define SCSI_Out__ACK__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN
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#define SCSI_Out__ACK__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0
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#define SCSI_Out__ACK__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1
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#define SCSI_Out__ACK__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0
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#define SCSI_Out__ACK__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1
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#define SCSI_Out__ACK__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT
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#define SCSI_Out__ACK__PS CYREG_PRT0_PS
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#define SCSI_Out__ACK__SHIFT 6
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#define SCSI_Out__ACK__SLW CYREG_PRT0_SLW
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#define SCSI_Out__ATN__AG CYREG_PRT4_AG
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#define SCSI_Out__ATN__AMUX CYREG_PRT4_AMUX
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#define SCSI_Out__ATN__BIE CYREG_PRT4_BIE
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#define SCSI_Out__ATN__BIT_MASK CYREG_PRT4_BIT_MASK
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#define SCSI_Out__ATN__BYP CYREG_PRT4_BYP
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#define SCSI_Out__ATN__CTL CYREG_PRT4_CTL
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#define SCSI_Out__ATN__DM0 CYREG_PRT4_DM0
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#define SCSI_Out__ATN__DM1 CYREG_PRT4_DM1
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#define SCSI_Out__ATN__DM2 CYREG_PRT4_DM2
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#define SCSI_Out__ATN__DR CYREG_PRT4_DR
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#define SCSI_Out__ATN__INP_DIS CYREG_PRT4_INP_DIS
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#define SCSI_Out__ATN__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG
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#define SCSI_Out__ATN__LCD_EN CYREG_PRT4_LCD_EN
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#define SCSI_Out__ATN__MASK 0x04u
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#define SCSI_Out__ATN__PC CYREG_PRT4_PC2
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#define SCSI_Out__ATN__PORT 4u
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#define SCSI_Out__ATN__PRT CYREG_PRT4_PRT
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#define SCSI_Out__ATN__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL
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#define SCSI_Out__ATN__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN
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#define SCSI_Out__ATN__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0
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#define SCSI_Out__ATN__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1
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#define SCSI_Out__ATN__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0
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#define SCSI_Out__ATN__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1
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#define SCSI_Out__ATN__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT
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#define SCSI_Out__ATN__PS CYREG_PRT4_PS
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#define SCSI_Out__ATN__SHIFT 2
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#define SCSI_Out__ATN__SLW CYREG_PRT4_SLW
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#define SCSI_Out__BSY__AG CYREG_PRT0_AG
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#define SCSI_Out__BSY__AMUX CYREG_PRT0_AMUX
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#define SCSI_Out__BSY__BIE CYREG_PRT0_BIE
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#define SCSI_Out__BSY__BIT_MASK CYREG_PRT0_BIT_MASK
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#define SCSI_Out__BSY__BYP CYREG_PRT0_BYP
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#define SCSI_Out__BSY__CTL CYREG_PRT0_CTL
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#define SCSI_Out__BSY__DM0 CYREG_PRT0_DM0
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#define SCSI_Out__BSY__DM1 CYREG_PRT0_DM1
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#define SCSI_Out__BSY__DM2 CYREG_PRT0_DM2
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#define SCSI_Out__BSY__DR CYREG_PRT0_DR
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#define SCSI_Out__BSY__INP_DIS CYREG_PRT0_INP_DIS
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#define SCSI_Out__BSY__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG
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#define SCSI_Out__BSY__LCD_EN CYREG_PRT0_LCD_EN
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#define SCSI_Out__BSY__MASK 0x80u
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#define SCSI_Out__BSY__PC CYREG_PRT0_PC7
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#define SCSI_Out__BSY__PORT 0u
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#define SCSI_Out__BSY__PRT CYREG_PRT0_PRT
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#define SCSI_Out__BSY__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL
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#define SCSI_Out__BSY__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN
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#define SCSI_Out__BSY__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0
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#define SCSI_Out__BSY__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1
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#define SCSI_Out__BSY__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0
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#define SCSI_Out__BSY__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1
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#define SCSI_Out__BSY__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT
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#define SCSI_Out__BSY__PS CYREG_PRT0_PS
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#define SCSI_Out__BSY__SHIFT 7
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#define SCSI_Out__BSY__SLW CYREG_PRT0_SLW
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#define SCSI_Out__CD_raw__AG CYREG_PRT0_AG
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#define SCSI_Out__CD_raw__AMUX CYREG_PRT0_AMUX
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#define SCSI_Out__CD_raw__BIE CYREG_PRT0_BIE
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#define SCSI_Out__CD_raw__BIT_MASK CYREG_PRT0_BIT_MASK
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#define SCSI_Out__CD_raw__BYP CYREG_PRT0_BYP
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#define SCSI_Out__CD_raw__CTL CYREG_PRT0_CTL
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#define SCSI_Out__CD_raw__DM0 CYREG_PRT0_DM0
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#define SCSI_Out__CD_raw__DM1 CYREG_PRT0_DM1
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#define SCSI_Out__CD_raw__DM2 CYREG_PRT0_DM2
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#define SCSI_Out__CD_raw__DR CYREG_PRT0_DR
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#define SCSI_Out__CD_raw__INP_DIS CYREG_PRT0_INP_DIS
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#define SCSI_Out__CD_raw__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG
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#define SCSI_Out__CD_raw__LCD_EN CYREG_PRT0_LCD_EN
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#define SCSI_Out__CD_raw__MASK 0x04u
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#define SCSI_Out__CD_raw__PC CYREG_PRT0_PC2
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#define SCSI_Out__CD_raw__PORT 0u
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#define SCSI_Out__CD_raw__PRT CYREG_PRT0_PRT
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#define SCSI_Out__CD_raw__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL
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#define SCSI_Out__CD_raw__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN
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#define SCSI_Out__CD_raw__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0
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#define SCSI_Out__CD_raw__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1
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#define SCSI_Out__CD_raw__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0
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#define SCSI_Out__CD_raw__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1
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#define SCSI_Out__CD_raw__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT
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#define SCSI_Out__CD_raw__PS CYREG_PRT0_PS
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#define SCSI_Out__CD_raw__SHIFT 2
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#define SCSI_Out__CD_raw__SLW CYREG_PRT0_SLW
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#define SCSI_Out__DBP_raw__AG CYREG_PRT4_AG
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#define SCSI_Out__DBP_raw__AMUX CYREG_PRT4_AMUX
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#define SCSI_Out__DBP_raw__BIE CYREG_PRT4_BIE
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#define SCSI_Out__DBP_raw__BIT_MASK CYREG_PRT4_BIT_MASK
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#define SCSI_Out__DBP_raw__BYP CYREG_PRT4_BYP
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#define SCSI_Out__DBP_raw__CTL CYREG_PRT4_CTL
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#define SCSI_Out__DBP_raw__DM0 CYREG_PRT4_DM0
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#define SCSI_Out__DBP_raw__DM1 CYREG_PRT4_DM1
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#define SCSI_Out__DBP_raw__DM2 CYREG_PRT4_DM2
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#define SCSI_Out__DBP_raw__DR CYREG_PRT4_DR
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#define SCSI_Out__DBP_raw__INP_DIS CYREG_PRT4_INP_DIS
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#define SCSI_Out__DBP_raw__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG
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#define SCSI_Out__DBP_raw__LCD_EN CYREG_PRT4_LCD_EN
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#define SCSI_Out__DBP_raw__MASK 0x08u
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#define SCSI_Out__DBP_raw__PC CYREG_PRT4_PC3
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#define SCSI_Out__DBP_raw__PORT 4u
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#define SCSI_Out__DBP_raw__PRT CYREG_PRT4_PRT
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#define SCSI_Out__DBP_raw__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL
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#define SCSI_Out__DBP_raw__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN
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#define SCSI_Out__DBP_raw__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0
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#define SCSI_Out__DBP_raw__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1
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#define SCSI_Out__DBP_raw__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0
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#define SCSI_Out__DBP_raw__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1
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#define SCSI_Out__DBP_raw__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT
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#define SCSI_Out__DBP_raw__PS CYREG_PRT4_PS
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#define SCSI_Out__DBP_raw__SHIFT 3
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#define SCSI_Out__DBP_raw__SLW CYREG_PRT4_SLW
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#define SCSI_Out__IO_raw__AG CYREG_PRT0_AG
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#define SCSI_Out__IO_raw__AMUX CYREG_PRT0_AMUX
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#define SCSI_Out__IO_raw__BIE CYREG_PRT0_BIE
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#define SCSI_Out__IO_raw__BIT_MASK CYREG_PRT0_BIT_MASK
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#define SCSI_Out__IO_raw__BYP CYREG_PRT0_BYP
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#define SCSI_Out__IO_raw__CTL CYREG_PRT0_CTL
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#define SCSI_Out__IO_raw__DM0 CYREG_PRT0_DM0
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#define SCSI_Out__IO_raw__DM1 CYREG_PRT0_DM1
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#define SCSI_Out__IO_raw__DM2 CYREG_PRT0_DM2
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#define SCSI_Out__IO_raw__DR CYREG_PRT0_DR
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#define SCSI_Out__IO_raw__INP_DIS CYREG_PRT0_INP_DIS
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#define SCSI_Out__IO_raw__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG
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#define SCSI_Out__IO_raw__LCD_EN CYREG_PRT0_LCD_EN
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#define SCSI_Out__IO_raw__MASK 0x01u
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#define SCSI_Out__IO_raw__PC CYREG_PRT0_PC0
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#define SCSI_Out__IO_raw__PORT 0u
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#define SCSI_Out__IO_raw__PRT CYREG_PRT0_PRT
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#define SCSI_Out__IO_raw__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL
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#define SCSI_Out__IO_raw__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN
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#define SCSI_Out__IO_raw__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0
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#define SCSI_Out__IO_raw__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1
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#define SCSI_Out__IO_raw__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0
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#define SCSI_Out__IO_raw__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1
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#define SCSI_Out__IO_raw__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT
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#define SCSI_Out__IO_raw__PS CYREG_PRT0_PS
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#define SCSI_Out__IO_raw__SHIFT 0
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#define SCSI_Out__IO_raw__SLW CYREG_PRT0_SLW
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#define SCSI_Out__MSG_raw__AG CYREG_PRT0_AG
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#define SCSI_Out__MSG_raw__AMUX CYREG_PRT0_AMUX
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#define SCSI_Out__MSG_raw__BIE CYREG_PRT0_BIE
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#define SCSI_Out__MSG_raw__BIT_MASK CYREG_PRT0_BIT_MASK
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#define SCSI_Out__MSG_raw__BYP CYREG_PRT0_BYP
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#define SCSI_Out__MSG_raw__CTL CYREG_PRT0_CTL
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#define SCSI_Out__MSG_raw__DM0 CYREG_PRT0_DM0
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#define SCSI_Out__MSG_raw__DM1 CYREG_PRT0_DM1
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#define SCSI_Out__MSG_raw__DM2 CYREG_PRT0_DM2
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#define SCSI_Out__MSG_raw__DR CYREG_PRT0_DR
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#define SCSI_Out__MSG_raw__INP_DIS CYREG_PRT0_INP_DIS
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#define SCSI_Out__MSG_raw__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG
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#define SCSI_Out__MSG_raw__LCD_EN CYREG_PRT0_LCD_EN
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#define SCSI_Out__MSG_raw__MASK 0x10u
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#define SCSI_Out__MSG_raw__PC CYREG_PRT0_PC4
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#define SCSI_Out__MSG_raw__PORT 0u
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#define SCSI_Out__MSG_raw__PRT CYREG_PRT0_PRT
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#define SCSI_Out__MSG_raw__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL
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#define SCSI_Out__MSG_raw__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN
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#define SCSI_Out__MSG_raw__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0
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#define SCSI_Out__MSG_raw__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1
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#define SCSI_Out__MSG_raw__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0
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#define SCSI_Out__MSG_raw__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1
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#define SCSI_Out__MSG_raw__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT
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#define SCSI_Out__MSG_raw__PS CYREG_PRT0_PS
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#define SCSI_Out__MSG_raw__SHIFT 4
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#define SCSI_Out__MSG_raw__SLW CYREG_PRT0_SLW
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#define SCSI_Out__REQ__AG CYREG_PRT0_AG
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#define SCSI_Out__REQ__AMUX CYREG_PRT0_AMUX
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#define SCSI_Out__REQ__BIE CYREG_PRT0_BIE
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#define SCSI_Out__REQ__BIT_MASK CYREG_PRT0_BIT_MASK
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#define SCSI_Out__REQ__BYP CYREG_PRT0_BYP
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#define SCSI_Out__REQ__CTL CYREG_PRT0_CTL
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#define SCSI_Out__REQ__DM0 CYREG_PRT0_DM0
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#define SCSI_Out__REQ__DM1 CYREG_PRT0_DM1
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#define SCSI_Out__REQ__DM2 CYREG_PRT0_DM2
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#define SCSI_Out__REQ__DR CYREG_PRT0_DR
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#define SCSI_Out__REQ__INP_DIS CYREG_PRT0_INP_DIS
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#define SCSI_Out__REQ__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG
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#define SCSI_Out__REQ__LCD_EN CYREG_PRT0_LCD_EN
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#define SCSI_Out__REQ__MASK 0x02u
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#define SCSI_Out__REQ__PC CYREG_PRT0_PC1
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#define SCSI_Out__REQ__PORT 0u
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#define SCSI_Out__REQ__PRT CYREG_PRT0_PRT
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#define SCSI_Out__REQ__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL
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#define SCSI_Out__REQ__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN
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#define SCSI_Out__REQ__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0
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#define SCSI_Out__REQ__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1
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#define SCSI_Out__REQ__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0
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#define SCSI_Out__REQ__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1
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#define SCSI_Out__REQ__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT
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#define SCSI_Out__REQ__PS CYREG_PRT0_PS
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#define SCSI_Out__REQ__SHIFT 1
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#define SCSI_Out__REQ__SLW CYREG_PRT0_SLW
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#define SCSI_Out__RST__AG CYREG_PRT0_AG
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#define SCSI_Out__RST__AMUX CYREG_PRT0_AMUX
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#define SCSI_Out__RST__BIE CYREG_PRT0_BIE
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#define SCSI_Out__RST__BIT_MASK CYREG_PRT0_BIT_MASK
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#define SCSI_Out__RST__BYP CYREG_PRT0_BYP
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#define SCSI_Out__RST__CTL CYREG_PRT0_CTL
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#define SCSI_Out__RST__DM0 CYREG_PRT0_DM0
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#define SCSI_Out__RST__DM1 CYREG_PRT0_DM1
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#define SCSI_Out__RST__DM2 CYREG_PRT0_DM2
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#define SCSI_Out__RST__DR CYREG_PRT0_DR
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#define SCSI_Out__RST__INP_DIS CYREG_PRT0_INP_DIS
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#define SCSI_Out__RST__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG
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#define SCSI_Out__RST__LCD_EN CYREG_PRT0_LCD_EN
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#define SCSI_Out__RST__MASK 0x20u
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#define SCSI_Out__RST__PC CYREG_PRT0_PC5
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#define SCSI_Out__RST__PORT 0u
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#define SCSI_Out__RST__PRT CYREG_PRT0_PRT
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#define SCSI_Out__RST__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL
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#define SCSI_Out__RST__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN
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#define SCSI_Out__RST__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0
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#define SCSI_Out__RST__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1
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#define SCSI_Out__RST__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0
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#define SCSI_Out__RST__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1
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#define SCSI_Out__RST__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT
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#define SCSI_Out__RST__PS CYREG_PRT0_PS
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#define SCSI_Out__RST__SHIFT 5
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#define SCSI_Out__RST__SLW CYREG_PRT0_SLW
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#define SCSI_Out__SEL__AG CYREG_PRT0_AG
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#define SCSI_Out__SEL__AMUX CYREG_PRT0_AMUX
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#define SCSI_Out__SEL__BIE CYREG_PRT0_BIE
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#define SCSI_Out__SEL__BIT_MASK CYREG_PRT0_BIT_MASK
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#define SCSI_Out__SEL__BYP CYREG_PRT0_BYP
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#define SCSI_Out__SEL__CTL CYREG_PRT0_CTL
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#define SCSI_Out__SEL__DM0 CYREG_PRT0_DM0
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#define SCSI_Out__SEL__DM1 CYREG_PRT0_DM1
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#define SCSI_Out__SEL__DM2 CYREG_PRT0_DM2
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#define SCSI_Out__SEL__DR CYREG_PRT0_DR
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#define SCSI_Out__SEL__INP_DIS CYREG_PRT0_INP_DIS
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#define SCSI_Out__SEL__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG
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#define SCSI_Out__SEL__LCD_EN CYREG_PRT0_LCD_EN
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#define SCSI_Out__SEL__MASK 0x08u
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#define SCSI_Out__SEL__PC CYREG_PRT0_PC3
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#define SCSI_Out__SEL__PORT 0u
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#define SCSI_Out__SEL__PRT CYREG_PRT0_PRT
|
|
#define SCSI_Out__SEL__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL
|
|
#define SCSI_Out__SEL__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN
|
|
#define SCSI_Out__SEL__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0
|
|
#define SCSI_Out__SEL__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1
|
|
#define SCSI_Out__SEL__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0
|
|
#define SCSI_Out__SEL__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1
|
|
#define SCSI_Out__SEL__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT
|
|
#define SCSI_Out__SEL__PS CYREG_PRT0_PS
|
|
#define SCSI_Out__SEL__SHIFT 3
|
|
#define SCSI_Out__SEL__SLW CYREG_PRT0_SLW
|
|
|
|
/* SCSI_RST */
|
|
#define SCSI_RST__0__MASK 0x40u
|
|
#define SCSI_RST__0__PC CYREG_PRT6_PC6
|
|
#define SCSI_RST__0__PORT 6u
|
|
#define SCSI_RST__0__SHIFT 6
|
|
#define SCSI_RST__AG CYREG_PRT6_AG
|
|
#define SCSI_RST__AMUX CYREG_PRT6_AMUX
|
|
#define SCSI_RST__BIE CYREG_PRT6_BIE
|
|
#define SCSI_RST__BIT_MASK CYREG_PRT6_BIT_MASK
|
|
#define SCSI_RST__BYP CYREG_PRT6_BYP
|
|
#define SCSI_RST__CTL CYREG_PRT6_CTL
|
|
#define SCSI_RST__DM0 CYREG_PRT6_DM0
|
|
#define SCSI_RST__DM1 CYREG_PRT6_DM1
|
|
#define SCSI_RST__DM2 CYREG_PRT6_DM2
|
|
#define SCSI_RST__DR CYREG_PRT6_DR
|
|
#define SCSI_RST__INP_DIS CYREG_PRT6_INP_DIS
|
|
#define SCSI_RST__INTSTAT CYREG_PICU6_INTSTAT
|
|
#define SCSI_RST__INT__MASK 0x40u
|
|
#define SCSI_RST__INT__PC CYREG_PRT6_PC6
|
|
#define SCSI_RST__INT__PORT 6u
|
|
#define SCSI_RST__INT__SHIFT 6
|
|
#define SCSI_RST__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG
|
|
#define SCSI_RST__LCD_EN CYREG_PRT6_LCD_EN
|
|
#define SCSI_RST__MASK 0x40u
|
|
#define SCSI_RST__PORT 6u
|
|
#define SCSI_RST__PRT CYREG_PRT6_PRT
|
|
#define SCSI_RST__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL
|
|
#define SCSI_RST__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN
|
|
#define SCSI_RST__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0
|
|
#define SCSI_RST__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1
|
|
#define SCSI_RST__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0
|
|
#define SCSI_RST__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1
|
|
#define SCSI_RST__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT
|
|
#define SCSI_RST__PS CYREG_PRT6_PS
|
|
#define SCSI_RST__SHIFT 6
|
|
#define SCSI_RST__SLW CYREG_PRT6_SLW
|
|
#define SCSI_RST__SNAP CYREG_PICU6_SNAP
|
|
|
|
/* USBFS_Dm */
|
|
#define USBFS_Dm__0__MASK 0x80u
|
|
#define USBFS_Dm__0__PC CYREG_IO_PC_PRT15_7_6_PC1
|
|
#define USBFS_Dm__0__PORT 15u
|
|
#define USBFS_Dm__0__SHIFT 7
|
|
#define USBFS_Dm__AG CYREG_PRT15_AG
|
|
#define USBFS_Dm__AMUX CYREG_PRT15_AMUX
|
|
#define USBFS_Dm__BIE CYREG_PRT15_BIE
|
|
#define USBFS_Dm__BIT_MASK CYREG_PRT15_BIT_MASK
|
|
#define USBFS_Dm__BYP CYREG_PRT15_BYP
|
|
#define USBFS_Dm__CTL CYREG_PRT15_CTL
|
|
#define USBFS_Dm__DM0 CYREG_PRT15_DM0
|
|
#define USBFS_Dm__DM1 CYREG_PRT15_DM1
|
|
#define USBFS_Dm__DM2 CYREG_PRT15_DM2
|
|
#define USBFS_Dm__DR CYREG_PRT15_DR
|
|
#define USBFS_Dm__INP_DIS CYREG_PRT15_INP_DIS
|
|
#define USBFS_Dm__LCD_COM_SEG CYREG_PRT15_LCD_COM_SEG
|
|
#define USBFS_Dm__LCD_EN CYREG_PRT15_LCD_EN
|
|
#define USBFS_Dm__MASK 0x80u
|
|
#define USBFS_Dm__PORT 15u
|
|
#define USBFS_Dm__PRT CYREG_PRT15_PRT
|
|
#define USBFS_Dm__PRTDSI__CAPS_SEL CYREG_PRT15_CAPS_SEL
|
|
#define USBFS_Dm__PRTDSI__DBL_SYNC_IN CYREG_PRT15_DBL_SYNC_IN
|
|
#define USBFS_Dm__PRTDSI__OE_SEL0 CYREG_PRT15_OE_SEL0
|
|
#define USBFS_Dm__PRTDSI__OE_SEL1 CYREG_PRT15_OE_SEL1
|
|
#define USBFS_Dm__PRTDSI__OUT_SEL0 CYREG_PRT15_OUT_SEL0
|
|
#define USBFS_Dm__PRTDSI__OUT_SEL1 CYREG_PRT15_OUT_SEL1
|
|
#define USBFS_Dm__PRTDSI__SYNC_OUT CYREG_PRT15_SYNC_OUT
|
|
#define USBFS_Dm__PS CYREG_PRT15_PS
|
|
#define USBFS_Dm__SHIFT 7
|
|
#define USBFS_Dm__SLW CYREG_PRT15_SLW
|
|
|
|
/* USBFS_Dp */
|
|
#define USBFS_Dp__0__MASK 0x40u
|
|
#define USBFS_Dp__0__PC CYREG_IO_PC_PRT15_7_6_PC0
|
|
#define USBFS_Dp__0__PORT 15u
|
|
#define USBFS_Dp__0__SHIFT 6
|
|
#define USBFS_Dp__AG CYREG_PRT15_AG
|
|
#define USBFS_Dp__AMUX CYREG_PRT15_AMUX
|
|
#define USBFS_Dp__BIE CYREG_PRT15_BIE
|
|
#define USBFS_Dp__BIT_MASK CYREG_PRT15_BIT_MASK
|
|
#define USBFS_Dp__BYP CYREG_PRT15_BYP
|
|
#define USBFS_Dp__CTL CYREG_PRT15_CTL
|
|
#define USBFS_Dp__DM0 CYREG_PRT15_DM0
|
|
#define USBFS_Dp__DM1 CYREG_PRT15_DM1
|
|
#define USBFS_Dp__DM2 CYREG_PRT15_DM2
|
|
#define USBFS_Dp__DR CYREG_PRT15_DR
|
|
#define USBFS_Dp__INP_DIS CYREG_PRT15_INP_DIS
|
|
#define USBFS_Dp__INTSTAT CYREG_PICU15_INTSTAT
|
|
#define USBFS_Dp__LCD_COM_SEG CYREG_PRT15_LCD_COM_SEG
|
|
#define USBFS_Dp__LCD_EN CYREG_PRT15_LCD_EN
|
|
#define USBFS_Dp__MASK 0x40u
|
|
#define USBFS_Dp__PORT 15u
|
|
#define USBFS_Dp__PRT CYREG_PRT15_PRT
|
|
#define USBFS_Dp__PRTDSI__CAPS_SEL CYREG_PRT15_CAPS_SEL
|
|
#define USBFS_Dp__PRTDSI__DBL_SYNC_IN CYREG_PRT15_DBL_SYNC_IN
|
|
#define USBFS_Dp__PRTDSI__OE_SEL0 CYREG_PRT15_OE_SEL0
|
|
#define USBFS_Dp__PRTDSI__OE_SEL1 CYREG_PRT15_OE_SEL1
|
|
#define USBFS_Dp__PRTDSI__OUT_SEL0 CYREG_PRT15_OUT_SEL0
|
|
#define USBFS_Dp__PRTDSI__OUT_SEL1 CYREG_PRT15_OUT_SEL1
|
|
#define USBFS_Dp__PRTDSI__SYNC_OUT CYREG_PRT15_SYNC_OUT
|
|
#define USBFS_Dp__PS CYREG_PRT15_PS
|
|
#define USBFS_Dp__SHIFT 6
|
|
#define USBFS_Dp__SLW CYREG_PRT15_SLW
|
|
#define USBFS_Dp__SNAP CYREG_PICU_15_SNAP_15
|
|
|
|
/* SCSI_In */
|
|
#define SCSI_In__0__AG CYREG_PRT2_AG
|
|
#define SCSI_In__0__AMUX CYREG_PRT2_AMUX
|
|
#define SCSI_In__0__BIE CYREG_PRT2_BIE
|
|
#define SCSI_In__0__BIT_MASK CYREG_PRT2_BIT_MASK
|
|
#define SCSI_In__0__BYP CYREG_PRT2_BYP
|
|
#define SCSI_In__0__CTL CYREG_PRT2_CTL
|
|
#define SCSI_In__0__DM0 CYREG_PRT2_DM0
|
|
#define SCSI_In__0__DM1 CYREG_PRT2_DM1
|
|
#define SCSI_In__0__DM2 CYREG_PRT2_DM2
|
|
#define SCSI_In__0__DR CYREG_PRT2_DR
|
|
#define SCSI_In__0__INP_DIS CYREG_PRT2_INP_DIS
|
|
#define SCSI_In__0__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG
|
|
#define SCSI_In__0__LCD_EN CYREG_PRT2_LCD_EN
|
|
#define SCSI_In__0__MASK 0x01u
|
|
#define SCSI_In__0__PC CYREG_PRT2_PC0
|
|
#define SCSI_In__0__PORT 2u
|
|
#define SCSI_In__0__PRT CYREG_PRT2_PRT
|
|
#define SCSI_In__0__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL
|
|
#define SCSI_In__0__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN
|
|
#define SCSI_In__0__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0
|
|
#define SCSI_In__0__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1
|
|
#define SCSI_In__0__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0
|
|
#define SCSI_In__0__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1
|
|
#define SCSI_In__0__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT
|
|
#define SCSI_In__0__PS CYREG_PRT2_PS
|
|
#define SCSI_In__0__SHIFT 0
|
|
#define SCSI_In__0__SLW CYREG_PRT2_SLW
|
|
#define SCSI_In__1__AG CYREG_PRT6_AG
|
|
#define SCSI_In__1__AMUX CYREG_PRT6_AMUX
|
|
#define SCSI_In__1__BIE CYREG_PRT6_BIE
|
|
#define SCSI_In__1__BIT_MASK CYREG_PRT6_BIT_MASK
|
|
#define SCSI_In__1__BYP CYREG_PRT6_BYP
|
|
#define SCSI_In__1__CTL CYREG_PRT6_CTL
|
|
#define SCSI_In__1__DM0 CYREG_PRT6_DM0
|
|
#define SCSI_In__1__DM1 CYREG_PRT6_DM1
|
|
#define SCSI_In__1__DM2 CYREG_PRT6_DM2
|
|
#define SCSI_In__1__DR CYREG_PRT6_DR
|
|
#define SCSI_In__1__INP_DIS CYREG_PRT6_INP_DIS
|
|
#define SCSI_In__1__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG
|
|
#define SCSI_In__1__LCD_EN CYREG_PRT6_LCD_EN
|
|
#define SCSI_In__1__MASK 0x10u
|
|
#define SCSI_In__1__PC CYREG_PRT6_PC4
|
|
#define SCSI_In__1__PORT 6u
|
|
#define SCSI_In__1__PRT CYREG_PRT6_PRT
|
|
#define SCSI_In__1__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL
|
|
#define SCSI_In__1__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN
|
|
#define SCSI_In__1__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0
|
|
#define SCSI_In__1__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1
|
|
#define SCSI_In__1__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0
|
|
#define SCSI_In__1__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1
|
|
#define SCSI_In__1__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT
|
|
#define SCSI_In__1__PS CYREG_PRT6_PS
|
|
#define SCSI_In__1__SHIFT 4
|
|
#define SCSI_In__1__SLW CYREG_PRT6_SLW
|
|
#define SCSI_In__2__AG CYREG_PRT6_AG
|
|
#define SCSI_In__2__AMUX CYREG_PRT6_AMUX
|
|
#define SCSI_In__2__BIE CYREG_PRT6_BIE
|
|
#define SCSI_In__2__BIT_MASK CYREG_PRT6_BIT_MASK
|
|
#define SCSI_In__2__BYP CYREG_PRT6_BYP
|
|
#define SCSI_In__2__CTL CYREG_PRT6_CTL
|
|
#define SCSI_In__2__DM0 CYREG_PRT6_DM0
|
|
#define SCSI_In__2__DM1 CYREG_PRT6_DM1
|
|
#define SCSI_In__2__DM2 CYREG_PRT6_DM2
|
|
#define SCSI_In__2__DR CYREG_PRT6_DR
|
|
#define SCSI_In__2__INP_DIS CYREG_PRT6_INP_DIS
|
|
#define SCSI_In__2__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG
|
|
#define SCSI_In__2__LCD_EN CYREG_PRT6_LCD_EN
|
|
#define SCSI_In__2__MASK 0x20u
|
|
#define SCSI_In__2__PC CYREG_PRT6_PC5
|
|
#define SCSI_In__2__PORT 6u
|
|
#define SCSI_In__2__PRT CYREG_PRT6_PRT
|
|
#define SCSI_In__2__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL
|
|
#define SCSI_In__2__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN
|
|
#define SCSI_In__2__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0
|
|
#define SCSI_In__2__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1
|
|
#define SCSI_In__2__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0
|
|
#define SCSI_In__2__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1
|
|
#define SCSI_In__2__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT
|
|
#define SCSI_In__2__PS CYREG_PRT6_PS
|
|
#define SCSI_In__2__SHIFT 5
|
|
#define SCSI_In__2__SLW CYREG_PRT6_SLW
|
|
#define SCSI_In__3__AG CYREG_PRT6_AG
|
|
#define SCSI_In__3__AMUX CYREG_PRT6_AMUX
|
|
#define SCSI_In__3__BIE CYREG_PRT6_BIE
|
|
#define SCSI_In__3__BIT_MASK CYREG_PRT6_BIT_MASK
|
|
#define SCSI_In__3__BYP CYREG_PRT6_BYP
|
|
#define SCSI_In__3__CTL CYREG_PRT6_CTL
|
|
#define SCSI_In__3__DM0 CYREG_PRT6_DM0
|
|
#define SCSI_In__3__DM1 CYREG_PRT6_DM1
|
|
#define SCSI_In__3__DM2 CYREG_PRT6_DM2
|
|
#define SCSI_In__3__DR CYREG_PRT6_DR
|
|
#define SCSI_In__3__INP_DIS CYREG_PRT6_INP_DIS
|
|
#define SCSI_In__3__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG
|
|
#define SCSI_In__3__LCD_EN CYREG_PRT6_LCD_EN
|
|
#define SCSI_In__3__MASK 0x80u
|
|
#define SCSI_In__3__PC CYREG_PRT6_PC7
|
|
#define SCSI_In__3__PORT 6u
|
|
#define SCSI_In__3__PRT CYREG_PRT6_PRT
|
|
#define SCSI_In__3__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL
|
|
#define SCSI_In__3__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN
|
|
#define SCSI_In__3__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0
|
|
#define SCSI_In__3__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1
|
|
#define SCSI_In__3__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0
|
|
#define SCSI_In__3__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1
|
|
#define SCSI_In__3__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT
|
|
#define SCSI_In__3__PS CYREG_PRT6_PS
|
|
#define SCSI_In__3__SHIFT 7
|
|
#define SCSI_In__3__SLW CYREG_PRT6_SLW
|
|
#define SCSI_In__4__AG CYREG_PRT5_AG
|
|
#define SCSI_In__4__AMUX CYREG_PRT5_AMUX
|
|
#define SCSI_In__4__BIE CYREG_PRT5_BIE
|
|
#define SCSI_In__4__BIT_MASK CYREG_PRT5_BIT_MASK
|
|
#define SCSI_In__4__BYP CYREG_PRT5_BYP
|
|
#define SCSI_In__4__CTL CYREG_PRT5_CTL
|
|
#define SCSI_In__4__DM0 CYREG_PRT5_DM0
|
|
#define SCSI_In__4__DM1 CYREG_PRT5_DM1
|
|
#define SCSI_In__4__DM2 CYREG_PRT5_DM2
|
|
#define SCSI_In__4__DR CYREG_PRT5_DR
|
|
#define SCSI_In__4__INP_DIS CYREG_PRT5_INP_DIS
|
|
#define SCSI_In__4__LCD_COM_SEG CYREG_PRT5_LCD_COM_SEG
|
|
#define SCSI_In__4__LCD_EN CYREG_PRT5_LCD_EN
|
|
#define SCSI_In__4__MASK 0x01u
|
|
#define SCSI_In__4__PC CYREG_PRT5_PC0
|
|
#define SCSI_In__4__PORT 5u
|
|
#define SCSI_In__4__PRT CYREG_PRT5_PRT
|
|
#define SCSI_In__4__PRTDSI__CAPS_SEL CYREG_PRT5_CAPS_SEL
|
|
#define SCSI_In__4__PRTDSI__DBL_SYNC_IN CYREG_PRT5_DBL_SYNC_IN
|
|
#define SCSI_In__4__PRTDSI__OE_SEL0 CYREG_PRT5_OE_SEL0
|
|
#define SCSI_In__4__PRTDSI__OE_SEL1 CYREG_PRT5_OE_SEL1
|
|
#define SCSI_In__4__PRTDSI__OUT_SEL0 CYREG_PRT5_OUT_SEL0
|
|
#define SCSI_In__4__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1
|
|
#define SCSI_In__4__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT
|
|
#define SCSI_In__4__PS CYREG_PRT5_PS
|
|
#define SCSI_In__4__SHIFT 0
|
|
#define SCSI_In__4__SLW CYREG_PRT5_SLW
|
|
#define SCSI_In__5__AG CYREG_PRT5_AG
|
|
#define SCSI_In__5__AMUX CYREG_PRT5_AMUX
|
|
#define SCSI_In__5__BIE CYREG_PRT5_BIE
|
|
#define SCSI_In__5__BIT_MASK CYREG_PRT5_BIT_MASK
|
|
#define SCSI_In__5__BYP CYREG_PRT5_BYP
|
|
#define SCSI_In__5__CTL CYREG_PRT5_CTL
|
|
#define SCSI_In__5__DM0 CYREG_PRT5_DM0
|
|
#define SCSI_In__5__DM1 CYREG_PRT5_DM1
|
|
#define SCSI_In__5__DM2 CYREG_PRT5_DM2
|
|
#define SCSI_In__5__DR CYREG_PRT5_DR
|
|
#define SCSI_In__5__INP_DIS CYREG_PRT5_INP_DIS
|
|
#define SCSI_In__5__LCD_COM_SEG CYREG_PRT5_LCD_COM_SEG
|
|
#define SCSI_In__5__LCD_EN CYREG_PRT5_LCD_EN
|
|
#define SCSI_In__5__MASK 0x02u
|
|
#define SCSI_In__5__PC CYREG_PRT5_PC1
|
|
#define SCSI_In__5__PORT 5u
|
|
#define SCSI_In__5__PRT CYREG_PRT5_PRT
|
|
#define SCSI_In__5__PRTDSI__CAPS_SEL CYREG_PRT5_CAPS_SEL
|
|
#define SCSI_In__5__PRTDSI__DBL_SYNC_IN CYREG_PRT5_DBL_SYNC_IN
|
|
#define SCSI_In__5__PRTDSI__OE_SEL0 CYREG_PRT5_OE_SEL0
|
|
#define SCSI_In__5__PRTDSI__OE_SEL1 CYREG_PRT5_OE_SEL1
|
|
#define SCSI_In__5__PRTDSI__OUT_SEL0 CYREG_PRT5_OUT_SEL0
|
|
#define SCSI_In__5__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1
|
|
#define SCSI_In__5__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT
|
|
#define SCSI_In__5__PS CYREG_PRT5_PS
|
|
#define SCSI_In__5__SHIFT 1
|
|
#define SCSI_In__5__SLW CYREG_PRT5_SLW
|
|
#define SCSI_In__6__AG CYREG_PRT5_AG
|
|
#define SCSI_In__6__AMUX CYREG_PRT5_AMUX
|
|
#define SCSI_In__6__BIE CYREG_PRT5_BIE
|
|
#define SCSI_In__6__BIT_MASK CYREG_PRT5_BIT_MASK
|
|
#define SCSI_In__6__BYP CYREG_PRT5_BYP
|
|
#define SCSI_In__6__CTL CYREG_PRT5_CTL
|
|
#define SCSI_In__6__DM0 CYREG_PRT5_DM0
|
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#define SCSI_In__6__DM1 CYREG_PRT5_DM1
|
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#define SCSI_In__6__DM2 CYREG_PRT5_DM2
|
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#define SCSI_In__6__DR CYREG_PRT5_DR
|
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#define SCSI_In__6__INP_DIS CYREG_PRT5_INP_DIS
|
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#define SCSI_In__6__LCD_COM_SEG CYREG_PRT5_LCD_COM_SEG
|
|
#define SCSI_In__6__LCD_EN CYREG_PRT5_LCD_EN
|
|
#define SCSI_In__6__MASK 0x04u
|
|
#define SCSI_In__6__PC CYREG_PRT5_PC2
|
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#define SCSI_In__6__PORT 5u
|
|
#define SCSI_In__6__PRT CYREG_PRT5_PRT
|
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#define SCSI_In__6__PRTDSI__CAPS_SEL CYREG_PRT5_CAPS_SEL
|
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#define SCSI_In__6__PRTDSI__DBL_SYNC_IN CYREG_PRT5_DBL_SYNC_IN
|
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#define SCSI_In__6__PRTDSI__OE_SEL0 CYREG_PRT5_OE_SEL0
|
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#define SCSI_In__6__PRTDSI__OE_SEL1 CYREG_PRT5_OE_SEL1
|
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#define SCSI_In__6__PRTDSI__OUT_SEL0 CYREG_PRT5_OUT_SEL0
|
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#define SCSI_In__6__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1
|
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#define SCSI_In__6__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT
|
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#define SCSI_In__6__PS CYREG_PRT5_PS
|
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#define SCSI_In__6__SHIFT 2
|
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#define SCSI_In__6__SLW CYREG_PRT5_SLW
|
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#define SCSI_In__7__AG CYREG_PRT5_AG
|
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#define SCSI_In__7__AMUX CYREG_PRT5_AMUX
|
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#define SCSI_In__7__BIE CYREG_PRT5_BIE
|
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#define SCSI_In__7__BIT_MASK CYREG_PRT5_BIT_MASK
|
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#define SCSI_In__7__BYP CYREG_PRT5_BYP
|
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#define SCSI_In__7__CTL CYREG_PRT5_CTL
|
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#define SCSI_In__7__DM0 CYREG_PRT5_DM0
|
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#define SCSI_In__7__DM1 CYREG_PRT5_DM1
|
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#define SCSI_In__7__DM2 CYREG_PRT5_DM2
|
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#define SCSI_In__7__DR CYREG_PRT5_DR
|
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#define SCSI_In__7__INP_DIS CYREG_PRT5_INP_DIS
|
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#define SCSI_In__7__LCD_COM_SEG CYREG_PRT5_LCD_COM_SEG
|
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#define SCSI_In__7__LCD_EN CYREG_PRT5_LCD_EN
|
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#define SCSI_In__7__MASK 0x08u
|
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#define SCSI_In__7__PC CYREG_PRT5_PC3
|
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#define SCSI_In__7__PORT 5u
|
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#define SCSI_In__7__PRT CYREG_PRT5_PRT
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#define SCSI_In__7__PRTDSI__CAPS_SEL CYREG_PRT5_CAPS_SEL
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#define SCSI_In__7__PRTDSI__DBL_SYNC_IN CYREG_PRT5_DBL_SYNC_IN
|
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#define SCSI_In__7__PRTDSI__OE_SEL0 CYREG_PRT5_OE_SEL0
|
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#define SCSI_In__7__PRTDSI__OE_SEL1 CYREG_PRT5_OE_SEL1
|
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#define SCSI_In__7__PRTDSI__OUT_SEL0 CYREG_PRT5_OUT_SEL0
|
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#define SCSI_In__7__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1
|
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#define SCSI_In__7__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT
|
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#define SCSI_In__7__PS CYREG_PRT5_PS
|
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#define SCSI_In__7__SHIFT 3
|
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#define SCSI_In__7__SLW CYREG_PRT5_SLW
|
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#define SCSI_In__ACK__AG CYREG_PRT6_AG
|
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#define SCSI_In__ACK__AMUX CYREG_PRT6_AMUX
|
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#define SCSI_In__ACK__BIE CYREG_PRT6_BIE
|
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#define SCSI_In__ACK__BIT_MASK CYREG_PRT6_BIT_MASK
|
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#define SCSI_In__ACK__BYP CYREG_PRT6_BYP
|
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#define SCSI_In__ACK__CTL CYREG_PRT6_CTL
|
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#define SCSI_In__ACK__DM0 CYREG_PRT6_DM0
|
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#define SCSI_In__ACK__DM1 CYREG_PRT6_DM1
|
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#define SCSI_In__ACK__DM2 CYREG_PRT6_DM2
|
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#define SCSI_In__ACK__DR CYREG_PRT6_DR
|
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#define SCSI_In__ACK__INP_DIS CYREG_PRT6_INP_DIS
|
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#define SCSI_In__ACK__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG
|
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#define SCSI_In__ACK__LCD_EN CYREG_PRT6_LCD_EN
|
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#define SCSI_In__ACK__MASK 0x20u
|
|
#define SCSI_In__ACK__PC CYREG_PRT6_PC5
|
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#define SCSI_In__ACK__PORT 6u
|
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#define SCSI_In__ACK__PRT CYREG_PRT6_PRT
|
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#define SCSI_In__ACK__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL
|
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#define SCSI_In__ACK__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN
|
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#define SCSI_In__ACK__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0
|
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#define SCSI_In__ACK__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1
|
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#define SCSI_In__ACK__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0
|
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#define SCSI_In__ACK__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1
|
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#define SCSI_In__ACK__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT
|
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#define SCSI_In__ACK__PS CYREG_PRT6_PS
|
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#define SCSI_In__ACK__SHIFT 5
|
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#define SCSI_In__ACK__SLW CYREG_PRT6_SLW
|
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#define SCSI_In__BSY__AG CYREG_PRT6_AG
|
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#define SCSI_In__BSY__AMUX CYREG_PRT6_AMUX
|
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#define SCSI_In__BSY__BIE CYREG_PRT6_BIE
|
|
#define SCSI_In__BSY__BIT_MASK CYREG_PRT6_BIT_MASK
|
|
#define SCSI_In__BSY__BYP CYREG_PRT6_BYP
|
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#define SCSI_In__BSY__CTL CYREG_PRT6_CTL
|
|
#define SCSI_In__BSY__DM0 CYREG_PRT6_DM0
|
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#define SCSI_In__BSY__DM1 CYREG_PRT6_DM1
|
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#define SCSI_In__BSY__DM2 CYREG_PRT6_DM2
|
|
#define SCSI_In__BSY__DR CYREG_PRT6_DR
|
|
#define SCSI_In__BSY__INP_DIS CYREG_PRT6_INP_DIS
|
|
#define SCSI_In__BSY__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG
|
|
#define SCSI_In__BSY__LCD_EN CYREG_PRT6_LCD_EN
|
|
#define SCSI_In__BSY__MASK 0x10u
|
|
#define SCSI_In__BSY__PC CYREG_PRT6_PC4
|
|
#define SCSI_In__BSY__PORT 6u
|
|
#define SCSI_In__BSY__PRT CYREG_PRT6_PRT
|
|
#define SCSI_In__BSY__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL
|
|
#define SCSI_In__BSY__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN
|
|
#define SCSI_In__BSY__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0
|
|
#define SCSI_In__BSY__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1
|
|
#define SCSI_In__BSY__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0
|
|
#define SCSI_In__BSY__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1
|
|
#define SCSI_In__BSY__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT
|
|
#define SCSI_In__BSY__PS CYREG_PRT6_PS
|
|
#define SCSI_In__BSY__SHIFT 4
|
|
#define SCSI_In__BSY__SLW CYREG_PRT6_SLW
|
|
#define SCSI_In__CD__AG CYREG_PRT5_AG
|
|
#define SCSI_In__CD__AMUX CYREG_PRT5_AMUX
|
|
#define SCSI_In__CD__BIE CYREG_PRT5_BIE
|
|
#define SCSI_In__CD__BIT_MASK CYREG_PRT5_BIT_MASK
|
|
#define SCSI_In__CD__BYP CYREG_PRT5_BYP
|
|
#define SCSI_In__CD__CTL CYREG_PRT5_CTL
|
|
#define SCSI_In__CD__DM0 CYREG_PRT5_DM0
|
|
#define SCSI_In__CD__DM1 CYREG_PRT5_DM1
|
|
#define SCSI_In__CD__DM2 CYREG_PRT5_DM2
|
|
#define SCSI_In__CD__DR CYREG_PRT5_DR
|
|
#define SCSI_In__CD__INP_DIS CYREG_PRT5_INP_DIS
|
|
#define SCSI_In__CD__LCD_COM_SEG CYREG_PRT5_LCD_COM_SEG
|
|
#define SCSI_In__CD__LCD_EN CYREG_PRT5_LCD_EN
|
|
#define SCSI_In__CD__MASK 0x02u
|
|
#define SCSI_In__CD__PC CYREG_PRT5_PC1
|
|
#define SCSI_In__CD__PORT 5u
|
|
#define SCSI_In__CD__PRT CYREG_PRT5_PRT
|
|
#define SCSI_In__CD__PRTDSI__CAPS_SEL CYREG_PRT5_CAPS_SEL
|
|
#define SCSI_In__CD__PRTDSI__DBL_SYNC_IN CYREG_PRT5_DBL_SYNC_IN
|
|
#define SCSI_In__CD__PRTDSI__OE_SEL0 CYREG_PRT5_OE_SEL0
|
|
#define SCSI_In__CD__PRTDSI__OE_SEL1 CYREG_PRT5_OE_SEL1
|
|
#define SCSI_In__CD__PRTDSI__OUT_SEL0 CYREG_PRT5_OUT_SEL0
|
|
#define SCSI_In__CD__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1
|
|
#define SCSI_In__CD__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT
|
|
#define SCSI_In__CD__PS CYREG_PRT5_PS
|
|
#define SCSI_In__CD__SHIFT 1
|
|
#define SCSI_In__CD__SLW CYREG_PRT5_SLW
|
|
#define SCSI_In__DBP__AG CYREG_PRT2_AG
|
|
#define SCSI_In__DBP__AMUX CYREG_PRT2_AMUX
|
|
#define SCSI_In__DBP__BIE CYREG_PRT2_BIE
|
|
#define SCSI_In__DBP__BIT_MASK CYREG_PRT2_BIT_MASK
|
|
#define SCSI_In__DBP__BYP CYREG_PRT2_BYP
|
|
#define SCSI_In__DBP__CTL CYREG_PRT2_CTL
|
|
#define SCSI_In__DBP__DM0 CYREG_PRT2_DM0
|
|
#define SCSI_In__DBP__DM1 CYREG_PRT2_DM1
|
|
#define SCSI_In__DBP__DM2 CYREG_PRT2_DM2
|
|
#define SCSI_In__DBP__DR CYREG_PRT2_DR
|
|
#define SCSI_In__DBP__INP_DIS CYREG_PRT2_INP_DIS
|
|
#define SCSI_In__DBP__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG
|
|
#define SCSI_In__DBP__LCD_EN CYREG_PRT2_LCD_EN
|
|
#define SCSI_In__DBP__MASK 0x01u
|
|
#define SCSI_In__DBP__PC CYREG_PRT2_PC0
|
|
#define SCSI_In__DBP__PORT 2u
|
|
#define SCSI_In__DBP__PRT CYREG_PRT2_PRT
|
|
#define SCSI_In__DBP__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL
|
|
#define SCSI_In__DBP__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN
|
|
#define SCSI_In__DBP__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0
|
|
#define SCSI_In__DBP__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1
|
|
#define SCSI_In__DBP__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0
|
|
#define SCSI_In__DBP__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1
|
|
#define SCSI_In__DBP__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT
|
|
#define SCSI_In__DBP__PS CYREG_PRT2_PS
|
|
#define SCSI_In__DBP__SHIFT 0
|
|
#define SCSI_In__DBP__SLW CYREG_PRT2_SLW
|
|
#define SCSI_In__IO__AG CYREG_PRT5_AG
|
|
#define SCSI_In__IO__AMUX CYREG_PRT5_AMUX
|
|
#define SCSI_In__IO__BIE CYREG_PRT5_BIE
|
|
#define SCSI_In__IO__BIT_MASK CYREG_PRT5_BIT_MASK
|
|
#define SCSI_In__IO__BYP CYREG_PRT5_BYP
|
|
#define SCSI_In__IO__CTL CYREG_PRT5_CTL
|
|
#define SCSI_In__IO__DM0 CYREG_PRT5_DM0
|
|
#define SCSI_In__IO__DM1 CYREG_PRT5_DM1
|
|
#define SCSI_In__IO__DM2 CYREG_PRT5_DM2
|
|
#define SCSI_In__IO__DR CYREG_PRT5_DR
|
|
#define SCSI_In__IO__INP_DIS CYREG_PRT5_INP_DIS
|
|
#define SCSI_In__IO__LCD_COM_SEG CYREG_PRT5_LCD_COM_SEG
|
|
#define SCSI_In__IO__LCD_EN CYREG_PRT5_LCD_EN
|
|
#define SCSI_In__IO__MASK 0x08u
|
|
#define SCSI_In__IO__PC CYREG_PRT5_PC3
|
|
#define SCSI_In__IO__PORT 5u
|
|
#define SCSI_In__IO__PRT CYREG_PRT5_PRT
|
|
#define SCSI_In__IO__PRTDSI__CAPS_SEL CYREG_PRT5_CAPS_SEL
|
|
#define SCSI_In__IO__PRTDSI__DBL_SYNC_IN CYREG_PRT5_DBL_SYNC_IN
|
|
#define SCSI_In__IO__PRTDSI__OE_SEL0 CYREG_PRT5_OE_SEL0
|
|
#define SCSI_In__IO__PRTDSI__OE_SEL1 CYREG_PRT5_OE_SEL1
|
|
#define SCSI_In__IO__PRTDSI__OUT_SEL0 CYREG_PRT5_OUT_SEL0
|
|
#define SCSI_In__IO__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1
|
|
#define SCSI_In__IO__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT
|
|
#define SCSI_In__IO__PS CYREG_PRT5_PS
|
|
#define SCSI_In__IO__SHIFT 3
|
|
#define SCSI_In__IO__SLW CYREG_PRT5_SLW
|
|
#define SCSI_In__MSG__AG CYREG_PRT6_AG
|
|
#define SCSI_In__MSG__AMUX CYREG_PRT6_AMUX
|
|
#define SCSI_In__MSG__BIE CYREG_PRT6_BIE
|
|
#define SCSI_In__MSG__BIT_MASK CYREG_PRT6_BIT_MASK
|
|
#define SCSI_In__MSG__BYP CYREG_PRT6_BYP
|
|
#define SCSI_In__MSG__CTL CYREG_PRT6_CTL
|
|
#define SCSI_In__MSG__DM0 CYREG_PRT6_DM0
|
|
#define SCSI_In__MSG__DM1 CYREG_PRT6_DM1
|
|
#define SCSI_In__MSG__DM2 CYREG_PRT6_DM2
|
|
#define SCSI_In__MSG__DR CYREG_PRT6_DR
|
|
#define SCSI_In__MSG__INP_DIS CYREG_PRT6_INP_DIS
|
|
#define SCSI_In__MSG__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG
|
|
#define SCSI_In__MSG__LCD_EN CYREG_PRT6_LCD_EN
|
|
#define SCSI_In__MSG__MASK 0x80u
|
|
#define SCSI_In__MSG__PC CYREG_PRT6_PC7
|
|
#define SCSI_In__MSG__PORT 6u
|
|
#define SCSI_In__MSG__PRT CYREG_PRT6_PRT
|
|
#define SCSI_In__MSG__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL
|
|
#define SCSI_In__MSG__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN
|
|
#define SCSI_In__MSG__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0
|
|
#define SCSI_In__MSG__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1
|
|
#define SCSI_In__MSG__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0
|
|
#define SCSI_In__MSG__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1
|
|
#define SCSI_In__MSG__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT
|
|
#define SCSI_In__MSG__PS CYREG_PRT6_PS
|
|
#define SCSI_In__MSG__SHIFT 7
|
|
#define SCSI_In__MSG__SLW CYREG_PRT6_SLW
|
|
#define SCSI_In__REQ__AG CYREG_PRT5_AG
|
|
#define SCSI_In__REQ__AMUX CYREG_PRT5_AMUX
|
|
#define SCSI_In__REQ__BIE CYREG_PRT5_BIE
|
|
#define SCSI_In__REQ__BIT_MASK CYREG_PRT5_BIT_MASK
|
|
#define SCSI_In__REQ__BYP CYREG_PRT5_BYP
|
|
#define SCSI_In__REQ__CTL CYREG_PRT5_CTL
|
|
#define SCSI_In__REQ__DM0 CYREG_PRT5_DM0
|
|
#define SCSI_In__REQ__DM1 CYREG_PRT5_DM1
|
|
#define SCSI_In__REQ__DM2 CYREG_PRT5_DM2
|
|
#define SCSI_In__REQ__DR CYREG_PRT5_DR
|
|
#define SCSI_In__REQ__INP_DIS CYREG_PRT5_INP_DIS
|
|
#define SCSI_In__REQ__LCD_COM_SEG CYREG_PRT5_LCD_COM_SEG
|
|
#define SCSI_In__REQ__LCD_EN CYREG_PRT5_LCD_EN
|
|
#define SCSI_In__REQ__MASK 0x04u
|
|
#define SCSI_In__REQ__PC CYREG_PRT5_PC2
|
|
#define SCSI_In__REQ__PORT 5u
|
|
#define SCSI_In__REQ__PRT CYREG_PRT5_PRT
|
|
#define SCSI_In__REQ__PRTDSI__CAPS_SEL CYREG_PRT5_CAPS_SEL
|
|
#define SCSI_In__REQ__PRTDSI__DBL_SYNC_IN CYREG_PRT5_DBL_SYNC_IN
|
|
#define SCSI_In__REQ__PRTDSI__OE_SEL0 CYREG_PRT5_OE_SEL0
|
|
#define SCSI_In__REQ__PRTDSI__OE_SEL1 CYREG_PRT5_OE_SEL1
|
|
#define SCSI_In__REQ__PRTDSI__OUT_SEL0 CYREG_PRT5_OUT_SEL0
|
|
#define SCSI_In__REQ__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1
|
|
#define SCSI_In__REQ__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT
|
|
#define SCSI_In__REQ__PS CYREG_PRT5_PS
|
|
#define SCSI_In__REQ__SHIFT 2
|
|
#define SCSI_In__REQ__SLW CYREG_PRT5_SLW
|
|
#define SCSI_In__SEL__AG CYREG_PRT5_AG
|
|
#define SCSI_In__SEL__AMUX CYREG_PRT5_AMUX
|
|
#define SCSI_In__SEL__BIE CYREG_PRT5_BIE
|
|
#define SCSI_In__SEL__BIT_MASK CYREG_PRT5_BIT_MASK
|
|
#define SCSI_In__SEL__BYP CYREG_PRT5_BYP
|
|
#define SCSI_In__SEL__CTL CYREG_PRT5_CTL
|
|
#define SCSI_In__SEL__DM0 CYREG_PRT5_DM0
|
|
#define SCSI_In__SEL__DM1 CYREG_PRT5_DM1
|
|
#define SCSI_In__SEL__DM2 CYREG_PRT5_DM2
|
|
#define SCSI_In__SEL__DR CYREG_PRT5_DR
|
|
#define SCSI_In__SEL__INP_DIS CYREG_PRT5_INP_DIS
|
|
#define SCSI_In__SEL__LCD_COM_SEG CYREG_PRT5_LCD_COM_SEG
|
|
#define SCSI_In__SEL__LCD_EN CYREG_PRT5_LCD_EN
|
|
#define SCSI_In__SEL__MASK 0x01u
|
|
#define SCSI_In__SEL__PC CYREG_PRT5_PC0
|
|
#define SCSI_In__SEL__PORT 5u
|
|
#define SCSI_In__SEL__PRT CYREG_PRT5_PRT
|
|
#define SCSI_In__SEL__PRTDSI__CAPS_SEL CYREG_PRT5_CAPS_SEL
|
|
#define SCSI_In__SEL__PRTDSI__DBL_SYNC_IN CYREG_PRT5_DBL_SYNC_IN
|
|
#define SCSI_In__SEL__PRTDSI__OE_SEL0 CYREG_PRT5_OE_SEL0
|
|
#define SCSI_In__SEL__PRTDSI__OE_SEL1 CYREG_PRT5_OE_SEL1
|
|
#define SCSI_In__SEL__PRTDSI__OUT_SEL0 CYREG_PRT5_OUT_SEL0
|
|
#define SCSI_In__SEL__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1
|
|
#define SCSI_In__SEL__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT
|
|
#define SCSI_In__SEL__PS CYREG_PRT5_PS
|
|
#define SCSI_In__SEL__SHIFT 0
|
|
#define SCSI_In__SEL__SLW CYREG_PRT5_SLW
|
|
|
|
/* SD_DAT1 */
|
|
#define SD_DAT1__0__MASK 0x01u
|
|
#define SD_DAT1__0__PC CYREG_PRT3_PC0
|
|
#define SD_DAT1__0__PORT 3u
|
|
#define SD_DAT1__0__SHIFT 0
|
|
#define SD_DAT1__AG CYREG_PRT3_AG
|
|
#define SD_DAT1__AMUX CYREG_PRT3_AMUX
|
|
#define SD_DAT1__BIE CYREG_PRT3_BIE
|
|
#define SD_DAT1__BIT_MASK CYREG_PRT3_BIT_MASK
|
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#define SD_DAT1__BYP CYREG_PRT3_BYP
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#define SD_DAT1__CTL CYREG_PRT3_CTL
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#define SD_DAT1__DM0 CYREG_PRT3_DM0
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#define SD_DAT1__DM1 CYREG_PRT3_DM1
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#define SD_DAT1__DM2 CYREG_PRT3_DM2
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#define SD_DAT1__DR CYREG_PRT3_DR
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#define SD_DAT1__INP_DIS CYREG_PRT3_INP_DIS
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#define SD_DAT1__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG
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#define SD_DAT1__LCD_EN CYREG_PRT3_LCD_EN
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#define SD_DAT1__MASK 0x01u
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#define SD_DAT1__PORT 3u
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#define SD_DAT1__PRT CYREG_PRT3_PRT
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#define SD_DAT1__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL
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#define SD_DAT1__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN
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#define SD_DAT1__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0
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#define SD_DAT1__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1
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#define SD_DAT1__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0
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#define SD_DAT1__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1
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#define SD_DAT1__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT
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#define SD_DAT1__PS CYREG_PRT3_PS
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#define SD_DAT1__SHIFT 0
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#define SD_DAT1__SLW CYREG_PRT3_SLW
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/* SD_DAT2 */
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#define SD_DAT2__0__MASK 0x20u
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#define SD_DAT2__0__PC CYREG_PRT3_PC5
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#define SD_DAT2__0__PORT 3u
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#define SD_DAT2__0__SHIFT 5
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#define SD_DAT2__AG CYREG_PRT3_AG
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#define SD_DAT2__AMUX CYREG_PRT3_AMUX
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#define SD_DAT2__BIE CYREG_PRT3_BIE
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#define SD_DAT2__BIT_MASK CYREG_PRT3_BIT_MASK
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#define SD_DAT2__BYP CYREG_PRT3_BYP
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#define SD_DAT2__CTL CYREG_PRT3_CTL
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#define SD_DAT2__DM0 CYREG_PRT3_DM0
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#define SD_DAT2__DM1 CYREG_PRT3_DM1
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#define SD_DAT2__DM2 CYREG_PRT3_DM2
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#define SD_DAT2__DR CYREG_PRT3_DR
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#define SD_DAT2__INP_DIS CYREG_PRT3_INP_DIS
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#define SD_DAT2__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG
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#define SD_DAT2__LCD_EN CYREG_PRT3_LCD_EN
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#define SD_DAT2__MASK 0x20u
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#define SD_DAT2__PORT 3u
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#define SD_DAT2__PRT CYREG_PRT3_PRT
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#define SD_DAT2__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL
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#define SD_DAT2__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN
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#define SD_DAT2__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0
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#define SD_DAT2__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1
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#define SD_DAT2__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0
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#define SD_DAT2__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1
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#define SD_DAT2__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT
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#define SD_DAT2__PS CYREG_PRT3_PS
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#define SD_DAT2__SHIFT 5
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#define SD_DAT2__SLW CYREG_PRT3_SLW
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/* SD_MISO */
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#define SD_MISO__0__MASK 0x02u
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#define SD_MISO__0__PC CYREG_PRT3_PC1
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#define SD_MISO__0__PORT 3u
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#define SD_MISO__0__SHIFT 1
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#define SD_MISO__AG CYREG_PRT3_AG
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#define SD_MISO__AMUX CYREG_PRT3_AMUX
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#define SD_MISO__BIE CYREG_PRT3_BIE
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#define SD_MISO__BIT_MASK CYREG_PRT3_BIT_MASK
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#define SD_MISO__BYP CYREG_PRT3_BYP
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#define SD_MISO__CTL CYREG_PRT3_CTL
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#define SD_MISO__DM0 CYREG_PRT3_DM0
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#define SD_MISO__DM1 CYREG_PRT3_DM1
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#define SD_MISO__DM2 CYREG_PRT3_DM2
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#define SD_MISO__DR CYREG_PRT3_DR
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#define SD_MISO__INP_DIS CYREG_PRT3_INP_DIS
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#define SD_MISO__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG
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#define SD_MISO__LCD_EN CYREG_PRT3_LCD_EN
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#define SD_MISO__MASK 0x02u
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#define SD_MISO__PORT 3u
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#define SD_MISO__PRT CYREG_PRT3_PRT
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#define SD_MISO__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL
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#define SD_MISO__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN
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#define SD_MISO__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0
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#define SD_MISO__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1
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#define SD_MISO__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0
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#define SD_MISO__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1
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#define SD_MISO__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT
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#define SD_MISO__PS CYREG_PRT3_PS
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#define SD_MISO__SHIFT 1
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#define SD_MISO__SLW CYREG_PRT3_SLW
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/* SD_MOSI */
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#define SD_MOSI__0__MASK 0x08u
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#define SD_MOSI__0__PC CYREG_PRT3_PC3
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#define SD_MOSI__0__PORT 3u
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#define SD_MOSI__0__SHIFT 3
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#define SD_MOSI__AG CYREG_PRT3_AG
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#define SD_MOSI__AMUX CYREG_PRT3_AMUX
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#define SD_MOSI__BIE CYREG_PRT3_BIE
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#define SD_MOSI__BIT_MASK CYREG_PRT3_BIT_MASK
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#define SD_MOSI__BYP CYREG_PRT3_BYP
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#define SD_MOSI__CTL CYREG_PRT3_CTL
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#define SD_MOSI__DM0 CYREG_PRT3_DM0
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#define SD_MOSI__DM1 CYREG_PRT3_DM1
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#define SD_MOSI__DM2 CYREG_PRT3_DM2
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#define SD_MOSI__DR CYREG_PRT3_DR
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#define SD_MOSI__INP_DIS CYREG_PRT3_INP_DIS
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#define SD_MOSI__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG
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#define SD_MOSI__LCD_EN CYREG_PRT3_LCD_EN
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#define SD_MOSI__MASK 0x08u
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#define SD_MOSI__PORT 3u
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#define SD_MOSI__PRT CYREG_PRT3_PRT
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#define SD_MOSI__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL
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#define SD_MOSI__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN
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#define SD_MOSI__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0
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#define SD_MOSI__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1
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#define SD_MOSI__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0
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#define SD_MOSI__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1
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#define SD_MOSI__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT
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#define SD_MOSI__PS CYREG_PRT3_PS
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#define SD_MOSI__SHIFT 3
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#define SD_MOSI__SLW CYREG_PRT3_SLW
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/* SD_SCK */
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#define SD_SCK__0__MASK 0x04u
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#define SD_SCK__0__PC CYREG_PRT3_PC2
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#define SD_SCK__0__PORT 3u
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#define SD_SCK__0__SHIFT 2
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#define SD_SCK__AG CYREG_PRT3_AG
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#define SD_SCK__AMUX CYREG_PRT3_AMUX
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#define SD_SCK__BIE CYREG_PRT3_BIE
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#define SD_SCK__BIT_MASK CYREG_PRT3_BIT_MASK
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#define SD_SCK__BYP CYREG_PRT3_BYP
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#define SD_SCK__CTL CYREG_PRT3_CTL
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#define SD_SCK__DM0 CYREG_PRT3_DM0
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#define SD_SCK__DM1 CYREG_PRT3_DM1
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#define SD_SCK__DM2 CYREG_PRT3_DM2
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#define SD_SCK__DR CYREG_PRT3_DR
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#define SD_SCK__INP_DIS CYREG_PRT3_INP_DIS
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#define SD_SCK__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG
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#define SD_SCK__LCD_EN CYREG_PRT3_LCD_EN
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#define SD_SCK__MASK 0x04u
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#define SD_SCK__PORT 3u
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#define SD_SCK__PRT CYREG_PRT3_PRT
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#define SD_SCK__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL
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#define SD_SCK__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN
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#define SD_SCK__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0
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#define SD_SCK__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1
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#define SD_SCK__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0
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#define SD_SCK__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1
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#define SD_SCK__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT
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#define SD_SCK__PS CYREG_PRT3_PS
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#define SD_SCK__SHIFT 2
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#define SD_SCK__SLW CYREG_PRT3_SLW
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/* SD_CD */
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#define SD_CD__0__MASK 0x40u
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#define SD_CD__0__PC CYREG_PRT3_PC6
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#define SD_CD__0__PORT 3u
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#define SD_CD__0__SHIFT 6
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#define SD_CD__AG CYREG_PRT3_AG
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#define SD_CD__AMUX CYREG_PRT3_AMUX
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#define SD_CD__BIE CYREG_PRT3_BIE
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#define SD_CD__BIT_MASK CYREG_PRT3_BIT_MASK
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#define SD_CD__BYP CYREG_PRT3_BYP
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#define SD_CD__CTL CYREG_PRT3_CTL
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#define SD_CD__DM0 CYREG_PRT3_DM0
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#define SD_CD__DM1 CYREG_PRT3_DM1
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#define SD_CD__DM2 CYREG_PRT3_DM2
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#define SD_CD__DR CYREG_PRT3_DR
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#define SD_CD__INP_DIS CYREG_PRT3_INP_DIS
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#define SD_CD__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG
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#define SD_CD__LCD_EN CYREG_PRT3_LCD_EN
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#define SD_CD__MASK 0x40u
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#define SD_CD__PORT 3u
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#define SD_CD__PRT CYREG_PRT3_PRT
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#define SD_CD__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL
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#define SD_CD__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN
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#define SD_CD__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0
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#define SD_CD__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1
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#define SD_CD__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0
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#define SD_CD__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1
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#define SD_CD__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT
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#define SD_CD__PS CYREG_PRT3_PS
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#define SD_CD__SHIFT 6
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#define SD_CD__SLW CYREG_PRT3_SLW
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/* SD_CS */
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#define SD_CS__0__MASK 0x10u
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#define SD_CS__0__PC CYREG_PRT3_PC4
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#define SD_CS__0__PORT 3u
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#define SD_CS__0__SHIFT 4
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#define SD_CS__AG CYREG_PRT3_AG
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#define SD_CS__AMUX CYREG_PRT3_AMUX
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#define SD_CS__BIE CYREG_PRT3_BIE
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#define SD_CS__BIT_MASK CYREG_PRT3_BIT_MASK
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#define SD_CS__BYP CYREG_PRT3_BYP
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#define SD_CS__CTL CYREG_PRT3_CTL
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#define SD_CS__DM0 CYREG_PRT3_DM0
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#define SD_CS__DM1 CYREG_PRT3_DM1
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#define SD_CS__DM2 CYREG_PRT3_DM2
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#define SD_CS__DR CYREG_PRT3_DR
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#define SD_CS__INP_DIS CYREG_PRT3_INP_DIS
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#define SD_CS__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG
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#define SD_CS__LCD_EN CYREG_PRT3_LCD_EN
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#define SD_CS__MASK 0x10u
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#define SD_CS__PORT 3u
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#define SD_CS__PRT CYREG_PRT3_PRT
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#define SD_CS__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL
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#define SD_CS__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN
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#define SD_CS__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0
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#define SD_CS__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1
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#define SD_CS__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0
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#define SD_CS__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1
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#define SD_CS__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT
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#define SD_CS__PS CYREG_PRT3_PS
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#define SD_CS__SHIFT 4
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#define SD_CS__SLW CYREG_PRT3_SLW
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/* LED1 */
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#define LED1__0__MASK 0x08u
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#define LED1__0__PC CYREG_PRT12_PC3
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#define LED1__0__PORT 12u
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#define LED1__0__SHIFT 3
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#define LED1__AG CYREG_PRT12_AG
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#define LED1__BIE CYREG_PRT12_BIE
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#define LED1__BIT_MASK CYREG_PRT12_BIT_MASK
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#define LED1__BYP CYREG_PRT12_BYP
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#define LED1__DM0 CYREG_PRT12_DM0
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#define LED1__DM1 CYREG_PRT12_DM1
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#define LED1__DM2 CYREG_PRT12_DM2
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#define LED1__DR CYREG_PRT12_DR
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#define LED1__INP_DIS CYREG_PRT12_INP_DIS
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#define LED1__MASK 0x08u
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#define LED1__PORT 12u
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#define LED1__PRT CYREG_PRT12_PRT
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#define LED1__PRTDSI__DBL_SYNC_IN CYREG_PRT12_DBL_SYNC_IN
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#define LED1__PRTDSI__OE_SEL0 CYREG_PRT12_OE_SEL0
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#define LED1__PRTDSI__OE_SEL1 CYREG_PRT12_OE_SEL1
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#define LED1__PRTDSI__OUT_SEL0 CYREG_PRT12_OUT_SEL0
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#define LED1__PRTDSI__OUT_SEL1 CYREG_PRT12_OUT_SEL1
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#define LED1__PRTDSI__SYNC_OUT CYREG_PRT12_SYNC_OUT
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#define LED1__PS CYREG_PRT12_PS
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#define LED1__SHIFT 3
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#define LED1__SIO_CFG CYREG_PRT12_SIO_CFG
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#define LED1__SIO_DIFF CYREG_PRT12_SIO_DIFF
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#define LED1__SIO_HYST_EN CYREG_PRT12_SIO_HYST_EN
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#define LED1__SIO_REG_HIFREQ CYREG_PRT12_SIO_REG_HIFREQ
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#define LED1__SLW CYREG_PRT12_SLW
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/* Miscellaneous */
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/* -- WARNING: define names containing LEOPARD or PANTHER are deprecated and will be removed in a future release */
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#define CYDEV_DEBUGGING_DPS_SWD_SWV 6
|
|
#define CYDEV_CONFIG_UNUSED_IO_AllowButWarn 0
|
|
#define CYDEV_CONFIGURATION_MODE_COMPRESSED 0
|
|
#define CYDEV_CONFIG_FASTBOOT_ENABLED 1
|
|
#define CYDEV_CHIP_REV_PSOC5LP_PRODUCTION 0u
|
|
#define CYDEV_CHIP_REVISION_5B_PRODUCTION 0u
|
|
#define CYDEV_CHIP_MEMBER_5B 4u
|
|
#define CYDEV_CHIP_FAMILY_PSOC5 3u
|
|
#define CYDEV_CHIP_DIE_PSOC5LP 4u
|
|
#define CYDEV_CHIP_DIE_EXPECT CYDEV_CHIP_DIE_PSOC5LP
|
|
#define BCLK__BUS_CLK__HZ 50000000U
|
|
#define BCLK__BUS_CLK__KHZ 50000U
|
|
#define BCLK__BUS_CLK__MHZ 50U
|
|
#define CYDEV_CHIP_DIE_ACTUAL CYDEV_CHIP_DIE_EXPECT
|
|
#define CYDEV_CHIP_DIE_LEOPARD 1u
|
|
#define CYDEV_CHIP_DIE_PANTHER 3u
|
|
#define CYDEV_CHIP_DIE_PSOC4A 2u
|
|
#define CYDEV_CHIP_DIE_UNKNOWN 0u
|
|
#define CYDEV_CHIP_FAMILY_PSOC3 1u
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|
#define CYDEV_CHIP_FAMILY_PSOC4 2u
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|
#define CYDEV_CHIP_FAMILY_UNKNOWN 0u
|
|
#define CYDEV_CHIP_FAMILY_USED CYDEV_CHIP_FAMILY_PSOC5
|
|
#define CYDEV_CHIP_JTAG_ID 0x2E133069u
|
|
#define CYDEV_CHIP_MEMBER_3A 1u
|
|
#define CYDEV_CHIP_MEMBER_4A 2u
|
|
#define CYDEV_CHIP_MEMBER_5A 3u
|
|
#define CYDEV_CHIP_MEMBER_UNKNOWN 0u
|
|
#define CYDEV_CHIP_MEMBER_USED CYDEV_CHIP_MEMBER_5B
|
|
#define CYDEV_CHIP_REVISION_3A_ES1 0u
|
|
#define CYDEV_CHIP_REVISION_3A_ES2 1u
|
|
#define CYDEV_CHIP_REVISION_3A_ES3 3u
|
|
#define CYDEV_CHIP_REVISION_3A_PRODUCTION 3u
|
|
#define CYDEV_CHIP_REVISION_4A_ES0 17u
|
|
#define CYDEV_CHIP_REVISION_4A_PRODUCTION 17u
|
|
#define CYDEV_CHIP_REVISION_5A_ES0 0u
|
|
#define CYDEV_CHIP_REVISION_5A_ES1 1u
|
|
#define CYDEV_CHIP_REVISION_5A_PRODUCTION 1u
|
|
#define CYDEV_CHIP_REVISION_5B_ES0 0u
|
|
#define CYDEV_CHIP_REVISION_USED CYDEV_CHIP_REVISION_5B_PRODUCTION
|
|
#define CYDEV_CHIP_REV_EXPECT CYDEV_CHIP_REV_PSOC5LP_PRODUCTION
|
|
#define CYDEV_CHIP_REV_LEOPARD_ES1 0u
|
|
#define CYDEV_CHIP_REV_LEOPARD_ES2 1u
|
|
#define CYDEV_CHIP_REV_LEOPARD_ES3 3u
|
|
#define CYDEV_CHIP_REV_LEOPARD_PRODUCTION 3u
|
|
#define CYDEV_CHIP_REV_PANTHER_ES0 0u
|
|
#define CYDEV_CHIP_REV_PANTHER_ES1 1u
|
|
#define CYDEV_CHIP_REV_PANTHER_PRODUCTION 1u
|
|
#define CYDEV_CHIP_REV_PSOC4A_ES0 17u
|
|
#define CYDEV_CHIP_REV_PSOC4A_PRODUCTION 17u
|
|
#define CYDEV_CHIP_REV_PSOC5LP_ES0 0u
|
|
#define CYDEV_CONFIGURATION_COMPRESSED 1
|
|
#define CYDEV_CONFIGURATION_DMA 0
|
|
#define CYDEV_CONFIGURATION_ECC 0
|
|
#define CYDEV_CONFIGURATION_IMOENABLED CYDEV_CONFIG_FASTBOOT_ENABLED
|
|
#define CYDEV_CONFIGURATION_MODE CYDEV_CONFIGURATION_MODE_COMPRESSED
|
|
#define CYDEV_CONFIGURATION_MODE_DMA 2
|
|
#define CYDEV_CONFIGURATION_MODE_UNCOMPRESSED 1
|
|
#define CYDEV_CONFIG_UNUSED_IO CYDEV_CONFIG_UNUSED_IO_AllowButWarn
|
|
#define CYDEV_CONFIG_UNUSED_IO_AllowWithInfo 1
|
|
#define CYDEV_CONFIG_UNUSED_IO_Disallowed 2
|
|
#define CYDEV_DEBUGGING_DPS CYDEV_DEBUGGING_DPS_SWD_SWV
|
|
#define CYDEV_DEBUGGING_DPS_Disable 3
|
|
#define CYDEV_DEBUGGING_DPS_JTAG_4 1
|
|
#define CYDEV_DEBUGGING_DPS_JTAG_5 0
|
|
#define CYDEV_DEBUGGING_DPS_SWD 2
|
|
#define CYDEV_DEBUGGING_ENABLE 1
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#define CYDEV_DEBUGGING_XRES 0
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#define CYDEV_DEBUG_ENABLE_MASK 0x20u
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#define CYDEV_DEBUG_ENABLE_REGISTER CYREG_MLOGIC_DEBUG
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#define CYDEV_DMA_CHANNELS_AVAILABLE 24u
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#define CYDEV_ECC_ENABLE 0
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#define CYDEV_HEAP_SIZE 0x0400
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#define CYDEV_INSTRUCT_CACHE_ENABLED 1
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#define CYDEV_INTR_RISING 0x0000001Eu
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#define CYDEV_PROJ_TYPE 2
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#define CYDEV_PROJ_TYPE_BOOTLOADER 1
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#define CYDEV_PROJ_TYPE_LOADABLE 2
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#define CYDEV_PROJ_TYPE_MULTIAPPBOOTLOADER 3
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#define CYDEV_PROJ_TYPE_STANDARD 0
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#define CYDEV_PROTECTION_ENABLE 0
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#define CYDEV_STACK_SIZE 0x2000
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#define CYDEV_USB_CLK_OSC_LOCKING_ENABLED_AT_PWR_UP
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#define CYDEV_USE_BUNDLED_CMSIS 1
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#define CYDEV_VARIABLE_VDDA 0
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#define CYDEV_VDDA 5.0
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#define CYDEV_VDDA_MV 5000
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#define CYDEV_VDDD 5.0
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#define CYDEV_VDDD_MV 5000
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#define CYDEV_VDDIO0 5.0
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#define CYDEV_VDDIO0_MV 5000
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#define CYDEV_VDDIO1 5.0
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#define CYDEV_VDDIO1_MV 5000
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#define CYDEV_VDDIO2 5.0
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#define CYDEV_VDDIO2_MV 5000
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#define CYDEV_VDDIO3 3.3
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#define CYDEV_VDDIO3_MV 3300
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#define CYDEV_VIO0 5
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#define CYDEV_VIO0_MV 5000
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#define CYDEV_VIO1 5
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#define CYDEV_VIO1_MV 5000
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#define CYDEV_VIO2 5
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#define CYDEV_VIO2_MV 5000
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#define CYDEV_VIO3 3.3
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#define CYDEV_VIO3_MV 3300
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#define DMA_CHANNELS_USED__MASK0 0x0000000Fu
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#define CYDEV_BOOTLOADER_ENABLE 0
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#endif /* INCLUDED_CYFITTER_H */
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