125 lines
4.5 KiB
C
125 lines
4.5 KiB
C
/*******************************************************************************
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* File Name: SCSI_CLK.h
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* Version 2.10
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*
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* Description:
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* Provides the function and constant definitions for the clock component.
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*
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* Note:
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*
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********************************************************************************
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* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
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* You may use this file only in accordance with the license, terms, conditions,
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* disclaimers, and limitations in the end user license agreement accompanying
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* the software package with which this file was provided.
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*******************************************************************************/
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#if !defined(CY_CLOCK_SCSI_CLK_H)
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#define CY_CLOCK_SCSI_CLK_H
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#include <cytypes.h>
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#include <cyfitter.h>
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/***************************************
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* Conditional Compilation Parameters
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***************************************/
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/* Check to see if required defines such as CY_PSOC5LP are available */
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/* They are defined starting with cy_boot v3.0 */
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#if !defined (CY_PSOC5LP)
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#error Component cy_clock_v2_10 requires cy_boot v3.0 or later
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#endif /* (CY_PSOC5LP) */
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/***************************************
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* Function Prototypes
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***************************************/
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void SCSI_CLK_Start(void) ;
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void SCSI_CLK_Stop(void) ;
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#if(CY_PSOC3 || CY_PSOC5LP)
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void SCSI_CLK_StopBlock(void) ;
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#endif /* (CY_PSOC3 || CY_PSOC5LP) */
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void SCSI_CLK_StandbyPower(uint8 state) ;
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void SCSI_CLK_SetDividerRegister(uint16 clkDivider, uint8 restart)
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;
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uint16 SCSI_CLK_GetDividerRegister(void) ;
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void SCSI_CLK_SetModeRegister(uint8 modeBitMask) ;
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void SCSI_CLK_ClearModeRegister(uint8 modeBitMask) ;
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uint8 SCSI_CLK_GetModeRegister(void) ;
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void SCSI_CLK_SetSourceRegister(uint8 clkSource) ;
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uint8 SCSI_CLK_GetSourceRegister(void) ;
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#if defined(SCSI_CLK__CFG3)
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void SCSI_CLK_SetPhaseRegister(uint8 clkPhase) ;
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uint8 SCSI_CLK_GetPhaseRegister(void) ;
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#endif /* defined(SCSI_CLK__CFG3) */
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#define SCSI_CLK_Enable() SCSI_CLK_Start()
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#define SCSI_CLK_Disable() SCSI_CLK_Stop()
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#define SCSI_CLK_SetDivider(clkDivider) SCSI_CLK_SetDividerRegister(clkDivider, 1u)
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#define SCSI_CLK_SetDividerValue(clkDivider) SCSI_CLK_SetDividerRegister((clkDivider) - 1u, 1u)
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#define SCSI_CLK_SetMode(clkMode) SCSI_CLK_SetModeRegister(clkMode)
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#define SCSI_CLK_SetSource(clkSource) SCSI_CLK_SetSourceRegister(clkSource)
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#if defined(SCSI_CLK__CFG3)
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#define SCSI_CLK_SetPhase(clkPhase) SCSI_CLK_SetPhaseRegister(clkPhase)
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#define SCSI_CLK_SetPhaseValue(clkPhase) SCSI_CLK_SetPhaseRegister((clkPhase) + 1u)
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#endif /* defined(SCSI_CLK__CFG3) */
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/***************************************
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* Registers
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***************************************/
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/* Register to enable or disable the clock */
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#define SCSI_CLK_CLKEN (* (reg8 *) SCSI_CLK__PM_ACT_CFG)
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#define SCSI_CLK_CLKEN_PTR ((reg8 *) SCSI_CLK__PM_ACT_CFG)
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/* Register to enable or disable the clock */
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#define SCSI_CLK_CLKSTBY (* (reg8 *) SCSI_CLK__PM_STBY_CFG)
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#define SCSI_CLK_CLKSTBY_PTR ((reg8 *) SCSI_CLK__PM_STBY_CFG)
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/* Clock LSB divider configuration register. */
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#define SCSI_CLK_DIV_LSB (* (reg8 *) SCSI_CLK__CFG0)
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#define SCSI_CLK_DIV_LSB_PTR ((reg8 *) SCSI_CLK__CFG0)
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#define SCSI_CLK_DIV_PTR ((reg16 *) SCSI_CLK__CFG0)
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/* Clock MSB divider configuration register. */
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#define SCSI_CLK_DIV_MSB (* (reg8 *) SCSI_CLK__CFG1)
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#define SCSI_CLK_DIV_MSB_PTR ((reg8 *) SCSI_CLK__CFG1)
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/* Mode and source configuration register */
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#define SCSI_CLK_MOD_SRC (* (reg8 *) SCSI_CLK__CFG2)
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#define SCSI_CLK_MOD_SRC_PTR ((reg8 *) SCSI_CLK__CFG2)
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#if defined(SCSI_CLK__CFG3)
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/* Analog clock phase configuration register */
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#define SCSI_CLK_PHASE (* (reg8 *) SCSI_CLK__CFG3)
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#define SCSI_CLK_PHASE_PTR ((reg8 *) SCSI_CLK__CFG3)
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#endif /* defined(SCSI_CLK__CFG3) */
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/**************************************
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* Register Constants
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**************************************/
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/* Power manager register masks */
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#define SCSI_CLK_CLKEN_MASK SCSI_CLK__PM_ACT_MSK
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#define SCSI_CLK_CLKSTBY_MASK SCSI_CLK__PM_STBY_MSK
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/* CFG2 field masks */
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#define SCSI_CLK_SRC_SEL_MSK SCSI_CLK__CFG2_SRC_SEL_MASK
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#define SCSI_CLK_MODE_MASK (~(SCSI_CLK_SRC_SEL_MSK))
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#if defined(SCSI_CLK__CFG3)
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/* CFG3 phase mask */
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#define SCSI_CLK_PHASE_MASK SCSI_CLK__CFG3_PHASE_DLY_MASK
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#endif /* defined(SCSI_CLK__CFG3) */
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#endif /* CY_CLOCK_SCSI_CLK_H */
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/* [] END OF FILE */
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