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https://github.com/fhgwright/SCSI2SD.git
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125 lines
4.8 KiB
C
125 lines
4.8 KiB
C
/*******************************************************************************
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* File Name: SD_Data_Clk.h
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* Version 2.20
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*
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* Description:
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* Provides the function and constant definitions for the clock component.
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*
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* Note:
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*
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********************************************************************************
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* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
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* You may use this file only in accordance with the license, terms, conditions,
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* disclaimers, and limitations in the end user license agreement accompanying
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* the software package with which this file was provided.
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*******************************************************************************/
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#if !defined(CY_CLOCK_SD_Data_Clk_H)
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#define CY_CLOCK_SD_Data_Clk_H
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#include <cytypes.h>
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#include <cyfitter.h>
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/***************************************
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* Conditional Compilation Parameters
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***************************************/
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/* Check to see if required defines such as CY_PSOC5LP are available */
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/* They are defined starting with cy_boot v3.0 */
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#if !defined (CY_PSOC5LP)
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#error Component cy_clock_v2_20 requires cy_boot v3.0 or later
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#endif /* (CY_PSOC5LP) */
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/***************************************
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* Function Prototypes
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***************************************/
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void SD_Data_Clk_Start(void) ;
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void SD_Data_Clk_Stop(void) ;
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#if(CY_PSOC3 || CY_PSOC5LP)
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void SD_Data_Clk_StopBlock(void) ;
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#endif /* (CY_PSOC3 || CY_PSOC5LP) */
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void SD_Data_Clk_StandbyPower(uint8 state) ;
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void SD_Data_Clk_SetDividerRegister(uint16 clkDivider, uint8 restart)
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;
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uint16 SD_Data_Clk_GetDividerRegister(void) ;
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void SD_Data_Clk_SetModeRegister(uint8 modeBitMask) ;
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void SD_Data_Clk_ClearModeRegister(uint8 modeBitMask) ;
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uint8 SD_Data_Clk_GetModeRegister(void) ;
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void SD_Data_Clk_SetSourceRegister(uint8 clkSource) ;
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uint8 SD_Data_Clk_GetSourceRegister(void) ;
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#if defined(SD_Data_Clk__CFG3)
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void SD_Data_Clk_SetPhaseRegister(uint8 clkPhase) ;
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uint8 SD_Data_Clk_GetPhaseRegister(void) ;
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#endif /* defined(SD_Data_Clk__CFG3) */
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#define SD_Data_Clk_Enable() SD_Data_Clk_Start()
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#define SD_Data_Clk_Disable() SD_Data_Clk_Stop()
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#define SD_Data_Clk_SetDivider(clkDivider) SD_Data_Clk_SetDividerRegister(clkDivider, 1u)
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#define SD_Data_Clk_SetDividerValue(clkDivider) SD_Data_Clk_SetDividerRegister((clkDivider) - 1u, 1u)
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#define SD_Data_Clk_SetMode(clkMode) SD_Data_Clk_SetModeRegister(clkMode)
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#define SD_Data_Clk_SetSource(clkSource) SD_Data_Clk_SetSourceRegister(clkSource)
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#if defined(SD_Data_Clk__CFG3)
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#define SD_Data_Clk_SetPhase(clkPhase) SD_Data_Clk_SetPhaseRegister(clkPhase)
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#define SD_Data_Clk_SetPhaseValue(clkPhase) SD_Data_Clk_SetPhaseRegister((clkPhase) + 1u)
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#endif /* defined(SD_Data_Clk__CFG3) */
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/***************************************
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* Registers
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***************************************/
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/* Register to enable or disable the clock */
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#define SD_Data_Clk_CLKEN (* (reg8 *) SD_Data_Clk__PM_ACT_CFG)
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#define SD_Data_Clk_CLKEN_PTR ((reg8 *) SD_Data_Clk__PM_ACT_CFG)
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/* Register to enable or disable the clock */
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#define SD_Data_Clk_CLKSTBY (* (reg8 *) SD_Data_Clk__PM_STBY_CFG)
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#define SD_Data_Clk_CLKSTBY_PTR ((reg8 *) SD_Data_Clk__PM_STBY_CFG)
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/* Clock LSB divider configuration register. */
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#define SD_Data_Clk_DIV_LSB (* (reg8 *) SD_Data_Clk__CFG0)
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#define SD_Data_Clk_DIV_LSB_PTR ((reg8 *) SD_Data_Clk__CFG0)
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#define SD_Data_Clk_DIV_PTR ((reg16 *) SD_Data_Clk__CFG0)
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/* Clock MSB divider configuration register. */
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#define SD_Data_Clk_DIV_MSB (* (reg8 *) SD_Data_Clk__CFG1)
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#define SD_Data_Clk_DIV_MSB_PTR ((reg8 *) SD_Data_Clk__CFG1)
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/* Mode and source configuration register */
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#define SD_Data_Clk_MOD_SRC (* (reg8 *) SD_Data_Clk__CFG2)
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#define SD_Data_Clk_MOD_SRC_PTR ((reg8 *) SD_Data_Clk__CFG2)
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#if defined(SD_Data_Clk__CFG3)
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/* Analog clock phase configuration register */
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#define SD_Data_Clk_PHASE (* (reg8 *) SD_Data_Clk__CFG3)
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#define SD_Data_Clk_PHASE_PTR ((reg8 *) SD_Data_Clk__CFG3)
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#endif /* defined(SD_Data_Clk__CFG3) */
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/**************************************
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* Register Constants
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**************************************/
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/* Power manager register masks */
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#define SD_Data_Clk_CLKEN_MASK SD_Data_Clk__PM_ACT_MSK
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#define SD_Data_Clk_CLKSTBY_MASK SD_Data_Clk__PM_STBY_MSK
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/* CFG2 field masks */
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#define SD_Data_Clk_SRC_SEL_MSK SD_Data_Clk__CFG2_SRC_SEL_MASK
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#define SD_Data_Clk_MODE_MASK (~(SD_Data_Clk_SRC_SEL_MSK))
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#if defined(SD_Data_Clk__CFG3)
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/* CFG3 phase mask */
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#define SD_Data_Clk_PHASE_MASK SD_Data_Clk__CFG3_PHASE_DLY_MASK
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#endif /* defined(SD_Data_Clk__CFG3) */
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#endif /* CY_CLOCK_SD_Data_Clk_H */
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/* [] END OF FILE */
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