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https://github.com/techav-homebrew/SE-Exp30.git
synced 2025-01-14 01:29:56 +00:00
New Synchronous Logic
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techav
parent
e457b3fec4
commit
fb19cbd984
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Waveform.vwf
256
Waveform.vwf
@ -292,16 +292,6 @@ SIGNAL("nbufDlo2En")
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PARENT = "";
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}
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SIGNAL("ncpuAvec")
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{
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VALUE_TYPE = NINE_LEVEL_BIT;
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SIGNAL_TYPE = SINGLE_BIT;
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WIDTH = 1;
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LSB_INDEX = -1;
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DIRECTION = OUTPUT;
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PARENT = "";
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}
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SIGNAL("ncpuBG")
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{
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VALUE_TYPE = NINE_LEVEL_BIT;
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@ -342,26 +332,6 @@ SIGNAL("ncpuDS")
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PARENT = "";
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}
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SIGNAL("ncpuDsack0")
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{
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VALUE_TYPE = NINE_LEVEL_BIT;
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SIGNAL_TYPE = SINGLE_BIT;
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WIDTH = 1;
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LSB_INDEX = -1;
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DIRECTION = OUTPUT;
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PARENT = "";
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}
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SIGNAL("ncpuDsack1")
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{
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VALUE_TYPE = NINE_LEVEL_BIT;
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SIGNAL_TYPE = SINGLE_BIT;
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WIDTH = 1;
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LSB_INDEX = -1;
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DIRECTION = OUTPUT;
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PARENT = "";
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}
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SIGNAL("ncpuHalt")
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{
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VALUE_TYPE = NINE_LEVEL_BIT;
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@ -527,6 +497,56 @@ GROUP("cpuSize")
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MEMBERS = "cpuSize0", "cpuSize1";
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}
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SIGNAL("ncpuAvec")
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{
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VALUE_TYPE = NINE_LEVEL_BIT;
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SIGNAL_TYPE = SINGLE_BIT;
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WIDTH = 1;
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LSB_INDEX = -1;
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DIRECTION = OUTPUT;
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PARENT = "";
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}
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SIGNAL("ncpuDsack0")
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{
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VALUE_TYPE = NINE_LEVEL_BIT;
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SIGNAL_TYPE = SINGLE_BIT;
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WIDTH = 1;
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LSB_INDEX = -1;
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DIRECTION = BIDIR;
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PARENT = "";
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}
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SIGNAL("ncpuDsack1")
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{
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VALUE_TYPE = NINE_LEVEL_BIT;
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SIGNAL_TYPE = SINGLE_BIT;
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WIDTH = 1;
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LSB_INDEX = -1;
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DIRECTION = BIDIR;
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PARENT = "";
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}
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SIGNAL("ncpuAS")
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{
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VALUE_TYPE = NINE_LEVEL_BIT;
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SIGNAL_TYPE = SINGLE_BIT;
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WIDTH = 1;
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LSB_INDEX = -1;
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DIRECTION = INPUT;
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PARENT = "";
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}
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SIGNAL("npdsAs")
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{
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VALUE_TYPE = NINE_LEVEL_BIT;
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SIGNAL_TYPE = SINGLE_BIT;
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WIDTH = 1;
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LSB_INDEX = -1;
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DIRECTION = BIDIR;
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PARENT = "";
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}
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TRANSITION_LIST("cpuFC[2]")
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{
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NODE
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@ -568,9 +588,7 @@ TRANSITION_LIST("cpuA0")
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NODE
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{
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REPEAT = 1;
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LEVEL 0 FOR 310.0;
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LEVEL 1 FOR 190.0;
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LEVEL 0 FOR 9500.0;
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LEVEL 0 FOR 10000.0;
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}
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}
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@ -588,9 +606,7 @@ TRANSITION_LIST("cpuAddrHi[21]")
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NODE
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{
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REPEAT = 1;
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LEVEL 0 FOR 700.0;
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LEVEL 1 FOR 240.0;
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LEVEL 0 FOR 9060.0;
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LEVEL 0 FOR 10000.0;
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}
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}
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@ -599,9 +615,7 @@ TRANSITION_LIST("cpuAddrHi[22]")
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NODE
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{
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REPEAT = 1;
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LEVEL 0 FOR 700.0;
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LEVEL 1 FOR 240.0;
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LEVEL 0 FOR 9060.0;
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LEVEL 0 FOR 10000.0;
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}
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}
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@ -714,7 +728,7 @@ TRANSITION_LIST("cpuSize1")
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NODE
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{
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REPEAT = 1;
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LEVEL 1 FOR 10000.0;
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LEVEL 0 FOR 10000.0;
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}
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}
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@ -763,15 +777,6 @@ TRANSITION_LIST("nbufDlo2En")
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}
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}
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TRANSITION_LIST("ncpuAvec")
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{
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NODE
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{
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REPEAT = 1;
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LEVEL X FOR 10000.0;
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}
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}
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TRANSITION_LIST("ncpuBG")
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{
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NODE
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@ -804,31 +809,7 @@ TRANSITION_LIST("ncpuDS")
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NODE
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{
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REPEAT = 1;
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LEVEL 1 FOR 130.0;
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LEVEL 0 FOR 120.0;
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LEVEL 1 FOR 120.0;
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LEVEL 0 FOR 130.0;
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LEVEL 1 FOR 200.0;
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LEVEL 0 FOR 240.0;
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LEVEL 1 FOR 9060.0;
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}
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}
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TRANSITION_LIST("ncpuDsack0")
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{
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NODE
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{
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REPEAT = 1;
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LEVEL X FOR 10000.0;
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}
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}
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TRANSITION_LIST("ncpuDsack1")
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{
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NODE
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{
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REPEAT = 1;
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LEVEL X FOR 10000.0;
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LEVEL 1 FOR 10000.0;
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}
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}
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@ -901,13 +882,11 @@ TRANSITION_LIST("npdsDtack")
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NODE
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{
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REPEAT = 1;
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LEVEL 1 FOR 190.0;
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LEVEL 0 FOR 60.0;
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LEVEL 1 FOR 190.0;
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LEVEL 0 FOR 60.0;
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LEVEL 1 FOR 360.0;
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LEVEL 0 FOR 80.0;
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LEVEL 1 FOR 9060.0;
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LEVEL 1 FOR 630.0;
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LEVEL 0 FOR 440.0;
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LEVEL 1 FOR 290.0;
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LEVEL 0 FOR 410.0;
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LEVEL 1 FOR 8230.0;
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}
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}
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@ -985,6 +964,55 @@ TRANSITION_LIST("pdsClockE")
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}
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}
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TRANSITION_LIST("ncpuAvec")
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{
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NODE
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{
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REPEAT = 1;
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LEVEL X FOR 10000.0;
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}
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}
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TRANSITION_LIST("ncpuDsack0")
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{
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NODE
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{
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REPEAT = 1;
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LEVEL Z FOR 10000.0;
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}
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}
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TRANSITION_LIST("ncpuDsack1")
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{
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NODE
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{
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REPEAT = 1;
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LEVEL Z FOR 10000.0;
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}
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}
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TRANSITION_LIST("ncpuAS")
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{
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NODE
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{
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REPEAT = 1;
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LEVEL 1 FOR 40.0;
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LEVEL 0 FOR 870.0;
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LEVEL 1 FOR 20.0;
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LEVEL 0 FOR 740.0;
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LEVEL 1 FOR 8330.0;
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}
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}
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TRANSITION_LIST("npdsAs")
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{
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NODE
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{
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REPEAT = 1;
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LEVEL Z FOR 10000.0;
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}
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}
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DISPLAY_LINE
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{
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CHANNEL = "npdsReset";
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@ -1250,7 +1278,7 @@ DISPLAY_LINE
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DISPLAY_LINE
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{
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CHANNEL = "ncpuAvec";
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CHANNEL = "ncpuAS";
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EXPAND_STATUS = COLLAPSED;
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RADIX = Binary;
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TREE_INDEX = 27;
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@ -1259,7 +1287,7 @@ DISPLAY_LINE
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DISPLAY_LINE
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{
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CHANNEL = "ncpuBG";
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CHANNEL = "npdsAs";
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EXPAND_STATUS = COLLAPSED;
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RADIX = Binary;
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TREE_INDEX = 28;
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@ -1268,7 +1296,7 @@ DISPLAY_LINE
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DISPLAY_LINE
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{
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CHANNEL = "ncpuBerr";
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CHANNEL = "ncpuBG";
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EXPAND_STATUS = COLLAPSED;
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RADIX = Binary;
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TREE_INDEX = 29;
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@ -1277,7 +1305,7 @@ DISPLAY_LINE
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DISPLAY_LINE
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{
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CHANNEL = "ncpuCiin";
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CHANNEL = "ncpuBerr";
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EXPAND_STATUS = COLLAPSED;
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RADIX = Binary;
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TREE_INDEX = 30;
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@ -1286,7 +1314,7 @@ DISPLAY_LINE
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DISPLAY_LINE
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{
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CHANNEL = "ncpuDsack0";
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CHANNEL = "ncpuCiin";
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EXPAND_STATUS = COLLAPSED;
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RADIX = Binary;
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TREE_INDEX = 31;
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@ -1295,7 +1323,7 @@ DISPLAY_LINE
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DISPLAY_LINE
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{
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CHANNEL = "ncpuDsack1";
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CHANNEL = "ncpuAvec";
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EXPAND_STATUS = COLLAPSED;
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RADIX = Binary;
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TREE_INDEX = 32;
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@ -1304,7 +1332,7 @@ DISPLAY_LINE
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DISPLAY_LINE
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{
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CHANNEL = "npdsDtack";
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CHANNEL = "ncpuDsack0";
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EXPAND_STATUS = COLLAPSED;
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RADIX = Binary;
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TREE_INDEX = 33;
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@ -1313,7 +1341,7 @@ DISPLAY_LINE
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DISPLAY_LINE
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{
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CHANNEL = "npdsUds";
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CHANNEL = "ncpuDsack1";
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EXPAND_STATUS = COLLAPSED;
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RADIX = Binary;
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TREE_INDEX = 34;
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@ -1322,7 +1350,7 @@ DISPLAY_LINE
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DISPLAY_LINE
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{
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CHANNEL = "npdsLds";
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CHANNEL = "npdsDtack";
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EXPAND_STATUS = COLLAPSED;
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RADIX = Binary;
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TREE_INDEX = 35;
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@ -1331,7 +1359,7 @@ DISPLAY_LINE
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DISPLAY_LINE
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{
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CHANNEL = "npdsVma";
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CHANNEL = "npdsUds";
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EXPAND_STATUS = COLLAPSED;
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RADIX = Binary;
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TREE_INDEX = 36;
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@ -1340,7 +1368,7 @@ DISPLAY_LINE
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DISPLAY_LINE
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{
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CHANNEL = "npdsVpa";
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CHANNEL = "npdsLds";
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EXPAND_STATUS = COLLAPSED;
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RADIX = Binary;
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TREE_INDEX = 37;
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@ -1349,7 +1377,7 @@ DISPLAY_LINE
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DISPLAY_LINE
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{
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CHANNEL = "ncpuHalt";
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CHANNEL = "npdsVma";
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EXPAND_STATUS = COLLAPSED;
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RADIX = Binary;
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TREE_INDEX = 38;
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@ -1358,7 +1386,7 @@ DISPLAY_LINE
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DISPLAY_LINE
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{
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CHANNEL = "ncpuReset";
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CHANNEL = "npdsVpa";
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EXPAND_STATUS = COLLAPSED;
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RADIX = Binary;
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TREE_INDEX = 39;
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@ -1367,7 +1395,7 @@ DISPLAY_LINE
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DISPLAY_LINE
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{
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CHANNEL = "npdsBGack";
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CHANNEL = "ncpuHalt";
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EXPAND_STATUS = COLLAPSED;
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RADIX = Binary;
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TREE_INDEX = 40;
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@ -1376,7 +1404,7 @@ DISPLAY_LINE
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DISPLAY_LINE
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{
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CHANNEL = "npdsBg";
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CHANNEL = "ncpuReset";
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EXPAND_STATUS = COLLAPSED;
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RADIX = Binary;
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TREE_INDEX = 41;
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@ -1385,7 +1413,7 @@ DISPLAY_LINE
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DISPLAY_LINE
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{
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CHANNEL = "nfpuCe";
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CHANNEL = "npdsBGack";
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EXPAND_STATUS = COLLAPSED;
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RADIX = Binary;
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TREE_INDEX = 42;
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@ -1394,7 +1422,7 @@ DISPLAY_LINE
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DISPLAY_LINE
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{
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CHANNEL = "nfpuSense";
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CHANNEL = "npdsBg";
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EXPAND_STATUS = COLLAPSED;
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RADIX = Binary;
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TREE_INDEX = 43;
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@ -1403,7 +1431,7 @@ DISPLAY_LINE
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DISPLAY_LINE
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{
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CHANNEL = "npdsBr";
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CHANNEL = "nfpuCe";
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EXPAND_STATUS = COLLAPSED;
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RADIX = Binary;
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TREE_INDEX = 44;
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@ -1412,7 +1440,7 @@ DISPLAY_LINE
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DISPLAY_LINE
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{
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CHANNEL = "bufDDir";
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CHANNEL = "nfpuSense";
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EXPAND_STATUS = COLLAPSED;
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RADIX = Binary;
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TREE_INDEX = 45;
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@ -1421,7 +1449,7 @@ DISPLAY_LINE
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DISPLAY_LINE
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{
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CHANNEL = "nbufDhiEn";
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CHANNEL = "npdsBr";
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EXPAND_STATUS = COLLAPSED;
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RADIX = Binary;
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TREE_INDEX = 46;
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@ -1430,7 +1458,7 @@ DISPLAY_LINE
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DISPLAY_LINE
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{
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CHANNEL = "nbufDlo1En";
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CHANNEL = "bufDDir";
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EXPAND_STATUS = COLLAPSED;
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RADIX = Binary;
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TREE_INDEX = 47;
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@ -1439,7 +1467,7 @@ DISPLAY_LINE
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DISPLAY_LINE
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{
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CHANNEL = "nbufDlo2En";
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CHANNEL = "nbufDhiEn";
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EXPAND_STATUS = COLLAPSED;
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RADIX = Binary;
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TREE_INDEX = 48;
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@ -1448,7 +1476,7 @@ DISPLAY_LINE
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DISPLAY_LINE
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{
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CHANNEL = "nbufAEn";
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CHANNEL = "nbufDlo1En";
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EXPAND_STATUS = COLLAPSED;
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RADIX = Binary;
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TREE_INDEX = 49;
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@ -1457,13 +1485,31 @@ DISPLAY_LINE
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DISPLAY_LINE
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{
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CHANNEL = "nbufCEn";
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CHANNEL = "nbufDlo2En";
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EXPAND_STATUS = COLLAPSED;
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RADIX = Binary;
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TREE_INDEX = 50;
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TREE_LEVEL = 0;
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}
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DISPLAY_LINE
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{
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CHANNEL = "nbufAEn";
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EXPAND_STATUS = COLLAPSED;
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RADIX = Binary;
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TREE_INDEX = 51;
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TREE_LEVEL = 0;
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}
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DISPLAY_LINE
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{
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CHANNEL = "nbufCEn";
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EXPAND_STATUS = COLLAPSED;
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RADIX = Binary;
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TREE_INDEX = 52;
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TREE_LEVEL = 0;
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}
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TIME_BAR
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{
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TIME = 0;
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356
paste.sv
356
paste.sv
@ -13,8 +13,8 @@ module paste (
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inout wire ncpuHalt, // 68030 halt signal (tristate)
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input wire ncpuDS, // 68030 data strobe signal
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input wire ncpuAS, // 68030 address strobe signal
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output wire ncpuDsack0, // 68030 DS Ack 0 signal
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output wire ncpuDsack1, // 68030 DS Ack 1 signal
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inout wire ncpuDsack0, // 68030 DS Ack 0 signal
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inout wire ncpuDsack1, // 68030 DS Ack 1 signal
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input wire cpuSize0, // 68030 Size 0 signal
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input wire cpuSize1, // 68030 Size 1 signal
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input wire cpuA0, // 68030 Address 0 signal
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@ -51,142 +51,111 @@ module paste (
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// define state machine states
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parameter
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S0 = 2'h0,
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S1 = 2'h1,
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S2 = 2'h2;
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S0 = 0,
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S1 = 1,
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S2 = 2,
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S3 = 3,
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S4 = 4,
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S5 = 5,
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S6 = 6,
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S7 = 7,
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S8 = 8;
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// state machine state variables
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logic [1:0] vmagenState; // state machine for npdsVma generator
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logic [1:0] dsack68genState; // state machine for nDsack68 generator
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logic [1:0] dsackSEgenState; // state machine for nDsackSE generator
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logic [3:0] busState; // state machine for 68000 bus
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logic [1:0] termState; // state machine for 68030 bus termination
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logic [1:0] resetgenState; // state machine for nCpuReset generator
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logic [3:0] vmagenCount; // state counter for npdsVma generator
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wire nUD, nLD; // intermediate data strobe signals
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|
||||
// intermediate signals
|
||||
wire nDsack68; // 6800 bus termination signal
|
||||
wire nDsackSE; // SE bus termination signal
|
||||
wire nUD; // SE upper data byte select
|
||||
wire nLD; // SE lower data byte select
|
||||
reg nAS; // SE address strobe
|
||||
|
||||
// D-latch to synchronize nAS to 8MHz clock
|
||||
// 68000 bus state machine
|
||||
// synchronous to 8MHz 68000 clock
|
||||
always @(posedge pdsC8m or negedge npdsReset) begin
|
||||
if(npdsReset == 0) nAS <= 1;
|
||||
else nAS <= ncpuAS;
|
||||
end
|
||||
|
||||
// state machine for npdsVma generation
|
||||
always @(posedge pdsC8m or negedge npdsReset) begin
|
||||
// sync state machine clocked by 8MHz system clock with async reset
|
||||
if(npdsReset == 1'b0) begin
|
||||
vmagenState <= S0;
|
||||
vmagenCount <= 4'h0;
|
||||
end else begin
|
||||
case(vmagenState)
|
||||
if(npdsReset == 0) busState <= S0;
|
||||
else begin
|
||||
case(busState)
|
||||
S0 : begin
|
||||
// wait for 6800 bus cycle to begin
|
||||
// marked by assertion of npdsVpa and pdsClockE
|
||||
if (npdsVpa == 1'b0 && pdsClockE == 1'b1) begin
|
||||
vmagenState <= S1;
|
||||
end else begin
|
||||
vmagenState <= S0;
|
||||
end
|
||||
vmagenCount <= 4'h0;
|
||||
// idle state, wait for cpu to begin bus cycle
|
||||
if(ncpuAS == 0) busState <= S1;
|
||||
else busState <= S0;
|
||||
end
|
||||
S1 : begin
|
||||
// wait for deassertion of pdsClockE
|
||||
if (pdsClockE == 1'b0) begin
|
||||
vmagenState <= S2;
|
||||
end else begin
|
||||
vmagenState <= S1;
|
||||
end
|
||||
vmagenCount <= 4'h0;
|
||||
// 68000 bus cycle state 2/3
|
||||
// progress immediately
|
||||
busState <= S2;
|
||||
end
|
||||
S2 : begin
|
||||
// increment vmagenCount until == 4'hA
|
||||
if (vmagenCount == 4'hA) begin
|
||||
vmagenState <= S0;
|
||||
vmagenCount <= 4'h0;
|
||||
end else begin
|
||||
vmagenState <= S2;
|
||||
vmagenCount <= vmagenCount + 1'b1;
|
||||
end
|
||||
// 68000 bus cycle state 4/5
|
||||
// wait for PDS DTACK or PDS VPA
|
||||
if(npdsDtack == 0) busState <= S3;
|
||||
else if(npdsVpa == 0) busState <= S4;
|
||||
else busState <= S2;
|
||||
end
|
||||
S3 : begin
|
||||
// 68000 bus cycle state 6/7
|
||||
// end 68000 bus cycle
|
||||
// progress immediately
|
||||
busState <= S0;
|
||||
end
|
||||
S4 : begin
|
||||
// 6800 bus cycle state 1
|
||||
// wait for E clock = 0
|
||||
if(pdsClockE == 0) busState <= S5;
|
||||
else busState <= S4;
|
||||
end
|
||||
S5 : begin
|
||||
// 6800 bus cycle state 2
|
||||
// wait for E clock = 1
|
||||
if(pdsClockE == 1) busState <= S6;
|
||||
else busState <= S5;
|
||||
end
|
||||
S6 : begin
|
||||
// 6800 bus cycle state 3
|
||||
// progress immediately
|
||||
busState <= S7;
|
||||
end
|
||||
S7 : begin
|
||||
// 6800 bus cycle state 4
|
||||
// progress immediately
|
||||
busState <= S8;
|
||||
end
|
||||
S8 : begin
|
||||
// 6800 bus cycle state 5
|
||||
// progress immediately
|
||||
busState <= S0;
|
||||
end
|
||||
default: begin
|
||||
// how did we end up here? reset to S0
|
||||
vmagenState <= S0;
|
||||
vmagenCount <= 4'h0;
|
||||
// how did we end up here?
|
||||
busState <= S0;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
// state machine for nDsack68 generation
|
||||
// 68030 bus termination state machine
|
||||
// synchronous to CPU clock
|
||||
always @(posedge cpuClock or negedge npdsReset) begin
|
||||
// sync state machine clocked by primary CPU clock with async reset
|
||||
if(npdsReset == 1'b0) begin
|
||||
dsack68genState <= S0;
|
||||
end else begin
|
||||
case(dsack68genState)
|
||||
if(npdsReset == 0) termState <= S0;
|
||||
else begin
|
||||
case(termState)
|
||||
S0 : begin
|
||||
// wait for vmagenCount == 4'hA
|
||||
if (vmagenCount == 4'hA) begin
|
||||
dsack68genState <= S1;
|
||||
end else begin
|
||||
dsack68genState <= S0;
|
||||
end
|
||||
// idle, wait for busState
|
||||
if(busState == S3 && pdsC8m == 1) termState <= S1;
|
||||
else if(busState == S8 && pdsC8m == 1) termState <= S1;
|
||||
else termState <= S0;
|
||||
end
|
||||
S1 : begin
|
||||
// immediately progress to S2
|
||||
dsack68genState <= S2;
|
||||
// assert 68030 bus termination
|
||||
// progress immediately
|
||||
termState <= S2;
|
||||
end
|
||||
S2 : begin
|
||||
// wait for vmagenCount to reset to 0
|
||||
if (vmagenCount == 4'h0) begin
|
||||
dsack68genState <= S0;
|
||||
end else begin
|
||||
dsack68genState <= S2;
|
||||
end
|
||||
// wait for busState
|
||||
if(busState == S0) termState <= S0;
|
||||
else termState <= S2;
|
||||
end
|
||||
default: begin
|
||||
// shouldn't be here. reset to S0
|
||||
dsack68genState <= S0;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
// state machine for nDsackSE generation
|
||||
always @(posedge cpuClock or negedge npdsReset) begin
|
||||
// sync state machine clocked by primary CPU clock with async reset
|
||||
if(npdsReset == 1'b0) begin
|
||||
dsackSEgenState <= S0;
|
||||
end else begin
|
||||
case(dsackSEgenState)
|
||||
S0 : begin
|
||||
// wait for assertion of npdsDtack
|
||||
if(npdsDtack == 1'b0) begin
|
||||
dsackSEgenState <= S1;
|
||||
end else begin
|
||||
dsackSEgenState <= S0;
|
||||
end
|
||||
end
|
||||
S1 : begin
|
||||
// immediately proceed to S3
|
||||
dsackSEgenState <= S2;
|
||||
end
|
||||
S2 : begin
|
||||
// wait for deassertion of npdsDtack
|
||||
if (npdsDtack == 1'b1) begin
|
||||
dsackSEgenState <= S0;
|
||||
end else begin
|
||||
dsackSEgenState <= S2;
|
||||
end
|
||||
end
|
||||
default: begin
|
||||
// shouldn't be here. reset to S0
|
||||
dsackSEgenState <= S0;
|
||||
// how did we end up here?
|
||||
termState <= S0;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
@ -233,39 +202,30 @@ always @(posedge cpuClock or negedge npdsReset) begin
|
||||
end
|
||||
end
|
||||
|
||||
// and finally, our combinatorial logic
|
||||
// combinatorial logic
|
||||
assign nUD = ~(~cpuA0 || cpuRnW);
|
||||
assign nLD = ~(cpuA0 || ~cpuSize0 || cpuSize1 || cpuRnW);
|
||||
|
||||
always_comb begin
|
||||
// DSACK intermediary signals
|
||||
if(dsack68genState == S1) begin
|
||||
nDsack68 <= 1'b0;
|
||||
// CPU reset signals
|
||||
if(resetgenState != S2) begin
|
||||
ncpuReset <= 1'b0;
|
||||
ncpuHalt <= 1'b0;
|
||||
end else begin
|
||||
nDsack68 <= 1'b1;
|
||||
end
|
||||
if(dsackSEgenState == S1) begin
|
||||
nDsackSE <= 1'b0;
|
||||
end else begin
|
||||
nDsackSE <= 1'b1;
|
||||
ncpuReset <= 1'bz;
|
||||
ncpuHalt <= 1'bz;
|
||||
end
|
||||
|
||||
// Upper/Lower data strobes
|
||||
if(npdsBg == 1) begin
|
||||
npdsUds <= 1'bZ;
|
||||
npdsLds <= 1'bZ;
|
||||
// bus request & grant
|
||||
if(resetgenState == S0) begin
|
||||
npdsBr <= 1'bz;
|
||||
end else begin
|
||||
if(ncpuDS == 0 && nUD == 0) npdsUds <= 0;
|
||||
else npdsUds <= 1;
|
||||
if(ncpuDS == 0 && nLD == 0) npdsLds <= 0;
|
||||
else npdsLds <= 1;
|
||||
npdsBr <= 1'b0;
|
||||
end
|
||||
|
||||
// Address strobe
|
||||
if(npdsBg == 1) begin
|
||||
npdsAs <= 1'bZ;
|
||||
if(resetgenState == S2) begin
|
||||
npdsBGack <= 1'b0;
|
||||
end else begin
|
||||
npdsAs <= nAS;
|
||||
npdsBGack <= 1'bz;
|
||||
end
|
||||
|
||||
// buffer enable signals
|
||||
@ -299,69 +259,91 @@ always_comb begin
|
||||
nbufAEn <= 1'b1;
|
||||
nbufCEn <= 1'b1;
|
||||
end
|
||||
|
||||
|
||||
// data buffer direction
|
||||
bufDDir <= cpuRnW;
|
||||
|
||||
// autovector request
|
||||
if(cpuFC == 3'h7 && nDsack68 == 1'b0) begin
|
||||
ncpuAvec <= 1'b0;
|
||||
end else begin
|
||||
ncpuAvec <= 1'b1;
|
||||
// CPU cache inhibit
|
||||
if(cpuAddrHi >= 4'h6) begin
|
||||
ncpuCiin <= 1'b0;
|
||||
end else begin
|
||||
ncpuCiin <= 1'bz;
|
||||
end
|
||||
|
||||
// VMA signal
|
||||
if(vmagenCount >= 4'h3) begin
|
||||
npdsVma <= 1'b0;
|
||||
// Upper/Lower data strobes
|
||||
if(npdsBg == 1) begin
|
||||
npdsUds <= 1'bZ;
|
||||
npdsLds <= 1'bZ;
|
||||
end else begin
|
||||
npdsVma <= 1'bz;
|
||||
if(cpuRnW == 1 && busState == S1) begin
|
||||
npdsUds <= nUD;
|
||||
npdsLds <= nLD;
|
||||
end else if (busState == S2 || busState == S3 ||
|
||||
busState == S4 || busState == S5 ||
|
||||
busState == S6 || busState == S7 ||
|
||||
busState == S8) begin
|
||||
npdsUds <= nUD;
|
||||
npdsLds <= nLD;
|
||||
end else begin
|
||||
npdsUds <= 1;
|
||||
npdsLds <= 1;
|
||||
end
|
||||
end
|
||||
|
||||
// DS Ack signals
|
||||
// 8-bit: ncpuDsack1=1, ncpuDsack0=0
|
||||
// 16-bit: ncpuDsack1=0, ncpuDsack0=1
|
||||
// nDsack68 is always an 8-bit transfer
|
||||
// nDsackSE is a 16-bit transfer below address $50,0000
|
||||
// nDsackSE is an 8-bit transfer above address $50,0000, inclusive
|
||||
if(
|
||||
(
|
||||
nDsack68 == 0 ||
|
||||
(nDsackSE == 0 && cpuAddrHi >= 4'h5)
|
||||
)
|
||||
&& cpuFC < 3'h7 ) begin
|
||||
ncpuDsack0 <= 0;
|
||||
end else begin
|
||||
ncpuDsack0 <= 1;
|
||||
end
|
||||
if(nDsackSE == 0 && cpuAddrHi < 4'h5 && cpuFC < 3'h7) begin
|
||||
ncpuDsack1 <= 0;
|
||||
end else begin
|
||||
ncpuDsack1 <= 1;
|
||||
// Address strobe
|
||||
if(npdsBg == 1) npdsAs <= 1'bZ;
|
||||
else begin
|
||||
if(busState != S0) npdsAs <= 0;
|
||||
else npdsAs <= 1;
|
||||
end
|
||||
|
||||
// CPU reset signals
|
||||
if(resetgenState != S2) begin
|
||||
ncpuReset <= 1'b0;
|
||||
ncpuHalt <= 1'b0;
|
||||
end else begin
|
||||
ncpuReset <= 1'bz;
|
||||
ncpuHalt <= 1'bz;
|
||||
// 6800 bus VMA signal
|
||||
if(npdsBg == 1) npdsVma <= 1'bZ;
|
||||
else begin
|
||||
if(busState == S5 || busState == S6 ||
|
||||
busState == S7 || busState == S8) begin
|
||||
npdsVma <= 0;
|
||||
end else npdsVma <= 1;
|
||||
end
|
||||
|
||||
// bus request & grant
|
||||
if(resetgenState == S0) begin
|
||||
npdsBr <= 1'bz;
|
||||
// 68030 bus termination signals
|
||||
// FPU will terminate on its own
|
||||
if(termState == S1) begin
|
||||
if(cpuAddrHi < 4'h5 && cpuFC < 3'h7) begin
|
||||
// RAM/ROM access - 16-bit
|
||||
ncpuDsack0 <= 1'bZ;
|
||||
ncpuDsack1 <= 0;
|
||||
ncpuAvec <= 1'bZ;
|
||||
ncpuBerr <= 1'bZ;
|
||||
end else if(cpuAddrHi >= 4'h5 && cpuFC < 3'h7) begin
|
||||
// peripheral access - 8-bit
|
||||
ncpuDsack0 <= 0;
|
||||
ncpuDsack1 <= 1'bZ;
|
||||
ncpuAvec <= 1'bZ;
|
||||
ncpuBerr <= 1'bZ;
|
||||
end else if(cpuFC == 3'h7) begin
|
||||
// autovector interrupt
|
||||
ncpuAvec <= 0;
|
||||
ncpuDsack0 <= 1'bZ;
|
||||
ncpuDsack1 <= 1'bZ;
|
||||
ncpuBerr <= 1'bZ;
|
||||
end else begin
|
||||
// this is an odd case. how did it happen?
|
||||
// may as well throw an error
|
||||
ncpuBerr <= 0;
|
||||
ncpuDsack0 <= 1'bZ;
|
||||
ncpuDsack1 <= 1'bZ;
|
||||
ncpuAvec <= 1'bZ;
|
||||
end
|
||||
end else begin
|
||||
npdsBr <= 1'b0;
|
||||
end
|
||||
if(resetgenState == S2) begin
|
||||
npdsBGack <= 1'b0;
|
||||
end else begin
|
||||
npdsBGack <= 1'bz;
|
||||
ncpuBerr <= 1'bZ;
|
||||
ncpuDsack0 <= 1'bZ;
|
||||
ncpuDsack1 <= 1'bZ;
|
||||
ncpuAvec <= 1'bZ;
|
||||
end
|
||||
|
||||
// FPU chip enable & presence detect
|
||||
if(cpuAddrMid == 7'h11 && cpuFC == 3'h7) begin
|
||||
if(cpuAddrMid == 7'h11 && cpuFC == 3'h7 && ncpuAS) begin
|
||||
nfpuCe <= 1'b0;
|
||||
if(nfpuSense == 1'b1) begin
|
||||
// pulled high means FPU missing. assert bus error
|
||||
@ -373,12 +355,6 @@ always_comb begin
|
||||
nfpuCe <= 1'b1;
|
||||
ncpuBerr <= 1'bz;
|
||||
end
|
||||
|
||||
// CPU cache inhibit
|
||||
if(cpuAddrHi >= 4'h6) begin
|
||||
ncpuCiin <= 1'b0;
|
||||
end else begin
|
||||
ncpuCiin <= 1'bz;
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
Loading…
x
Reference in New Issue
Block a user