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SE-Exp30
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New Synchronous Logic

This commit is contained in:
techav 2021-07-04 00:59:51 -05:00
parent e457b3fec4
commit fb19cbd984
2 changed files with 317 additions and 295 deletions
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256
Waveform.vwf
View File

@ -292,16 +292,6 @@ SIGNAL("nbufDlo2En")
PARENT = "";
}
SIGNAL("ncpuAvec")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = OUTPUT;
PARENT = "";
}
SIGNAL("ncpuBG")
{
VALUE_TYPE = NINE_LEVEL_BIT;
@ -342,26 +332,6 @@ SIGNAL("ncpuDS")
PARENT = "";
}
SIGNAL("ncpuDsack0")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = OUTPUT;
PARENT = "";
}
SIGNAL("ncpuDsack1")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = OUTPUT;
PARENT = "";
}
SIGNAL("ncpuHalt")
{
VALUE_TYPE = NINE_LEVEL_BIT;
@ -527,6 +497,56 @@ GROUP("cpuSize")
MEMBERS = "cpuSize0", "cpuSize1";
}
SIGNAL("ncpuAvec")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = OUTPUT;
PARENT = "";
}
SIGNAL("ncpuDsack0")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = BIDIR;
PARENT = "";
}
SIGNAL("ncpuDsack1")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = BIDIR;
PARENT = "";
}
SIGNAL("ncpuAS")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "";
}
SIGNAL("npdsAs")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = BIDIR;
PARENT = "";
}
TRANSITION_LIST("cpuFC[2]")
{
NODE
@ -568,9 +588,7 @@ TRANSITION_LIST("cpuA0")
NODE
{
REPEAT = 1;
LEVEL 0 FOR 310.0;
LEVEL 1 FOR 190.0;
LEVEL 0 FOR 9500.0;
LEVEL 0 FOR 10000.0;
}
}
@ -588,9 +606,7 @@ TRANSITION_LIST("cpuAddrHi[21]")
NODE
{
REPEAT = 1;
LEVEL 0 FOR 700.0;
LEVEL 1 FOR 240.0;
LEVEL 0 FOR 9060.0;
LEVEL 0 FOR 10000.0;
}
}
@ -599,9 +615,7 @@ TRANSITION_LIST("cpuAddrHi[22]")
NODE
{
REPEAT = 1;
LEVEL 0 FOR 700.0;
LEVEL 1 FOR 240.0;
LEVEL 0 FOR 9060.0;
LEVEL 0 FOR 10000.0;
}
}
@ -714,7 +728,7 @@ TRANSITION_LIST("cpuSize1")
NODE
{
REPEAT = 1;
LEVEL 1 FOR 10000.0;
LEVEL 0 FOR 10000.0;
}
}
@ -763,15 +777,6 @@ TRANSITION_LIST("nbufDlo2En")
}
}
TRANSITION_LIST("ncpuAvec")
{
NODE
{
REPEAT = 1;
LEVEL X FOR 10000.0;
}
}
TRANSITION_LIST("ncpuBG")
{
NODE
@ -804,31 +809,7 @@ TRANSITION_LIST("ncpuDS")
NODE
{
REPEAT = 1;
LEVEL 1 FOR 130.0;
LEVEL 0 FOR 120.0;
LEVEL 1 FOR 120.0;
LEVEL 0 FOR 130.0;
LEVEL 1 FOR 200.0;
LEVEL 0 FOR 240.0;
LEVEL 1 FOR 9060.0;
}
}
TRANSITION_LIST("ncpuDsack0")
{
NODE
{
REPEAT = 1;
LEVEL X FOR 10000.0;
}
}
TRANSITION_LIST("ncpuDsack1")
{
NODE
{
REPEAT = 1;
LEVEL X FOR 10000.0;
LEVEL 1 FOR 10000.0;
}
}
@ -901,13 +882,11 @@ TRANSITION_LIST("npdsDtack")
NODE
{
REPEAT = 1;
LEVEL 1 FOR 190.0;
LEVEL 0 FOR 60.0;
LEVEL 1 FOR 190.0;
LEVEL 0 FOR 60.0;
LEVEL 1 FOR 360.0;
LEVEL 0 FOR 80.0;
LEVEL 1 FOR 9060.0;
LEVEL 1 FOR 630.0;
LEVEL 0 FOR 440.0;
LEVEL 1 FOR 290.0;
LEVEL 0 FOR 410.0;
LEVEL 1 FOR 8230.0;
}
}
@ -985,6 +964,55 @@ TRANSITION_LIST("pdsClockE")
}
}
TRANSITION_LIST("ncpuAvec")
{
NODE
{
REPEAT = 1;
LEVEL X FOR 10000.0;
}
}
TRANSITION_LIST("ncpuDsack0")
{
NODE
{
REPEAT = 1;
LEVEL Z FOR 10000.0;
}
}
TRANSITION_LIST("ncpuDsack1")
{
NODE
{
REPEAT = 1;
LEVEL Z FOR 10000.0;
}
}
TRANSITION_LIST("ncpuAS")
{
NODE
{
REPEAT = 1;
LEVEL 1 FOR 40.0;
LEVEL 0 FOR 870.0;
LEVEL 1 FOR 20.0;
LEVEL 0 FOR 740.0;
LEVEL 1 FOR 8330.0;
}
}
TRANSITION_LIST("npdsAs")
{
NODE
{
REPEAT = 1;
LEVEL Z FOR 10000.0;
}
}
DISPLAY_LINE
{
CHANNEL = "npdsReset";
@ -1250,7 +1278,7 @@ DISPLAY_LINE
DISPLAY_LINE
{
CHANNEL = "ncpuAvec";
CHANNEL = "ncpuAS";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 27;
@ -1259,7 +1287,7 @@ DISPLAY_LINE
DISPLAY_LINE
{
CHANNEL = "ncpuBG";
CHANNEL = "npdsAs";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 28;
@ -1268,7 +1296,7 @@ DISPLAY_LINE
DISPLAY_LINE
{
CHANNEL = "ncpuBerr";
CHANNEL = "ncpuBG";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 29;
@ -1277,7 +1305,7 @@ DISPLAY_LINE
DISPLAY_LINE
{
CHANNEL = "ncpuCiin";
CHANNEL = "ncpuBerr";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 30;
@ -1286,7 +1314,7 @@ DISPLAY_LINE
DISPLAY_LINE
{
CHANNEL = "ncpuDsack0";
CHANNEL = "ncpuCiin";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 31;
@ -1295,7 +1323,7 @@ DISPLAY_LINE
DISPLAY_LINE
{
CHANNEL = "ncpuDsack1";
CHANNEL = "ncpuAvec";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 32;
@ -1304,7 +1332,7 @@ DISPLAY_LINE
DISPLAY_LINE
{
CHANNEL = "npdsDtack";
CHANNEL = "ncpuDsack0";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 33;
@ -1313,7 +1341,7 @@ DISPLAY_LINE
DISPLAY_LINE
{
CHANNEL = "npdsUds";
CHANNEL = "ncpuDsack1";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 34;
@ -1322,7 +1350,7 @@ DISPLAY_LINE
DISPLAY_LINE
{
CHANNEL = "npdsLds";
CHANNEL = "npdsDtack";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 35;
@ -1331,7 +1359,7 @@ DISPLAY_LINE
DISPLAY_LINE
{
CHANNEL = "npdsVma";
CHANNEL = "npdsUds";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 36;
@ -1340,7 +1368,7 @@ DISPLAY_LINE
DISPLAY_LINE
{
CHANNEL = "npdsVpa";
CHANNEL = "npdsLds";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 37;
@ -1349,7 +1377,7 @@ DISPLAY_LINE
DISPLAY_LINE
{
CHANNEL = "ncpuHalt";
CHANNEL = "npdsVma";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 38;
@ -1358,7 +1386,7 @@ DISPLAY_LINE
DISPLAY_LINE
{
CHANNEL = "ncpuReset";
CHANNEL = "npdsVpa";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 39;
@ -1367,7 +1395,7 @@ DISPLAY_LINE
DISPLAY_LINE
{
CHANNEL = "npdsBGack";
CHANNEL = "ncpuHalt";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 40;
@ -1376,7 +1404,7 @@ DISPLAY_LINE
DISPLAY_LINE
{
CHANNEL = "npdsBg";
CHANNEL = "ncpuReset";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 41;
@ -1385,7 +1413,7 @@ DISPLAY_LINE
DISPLAY_LINE
{
CHANNEL = "nfpuCe";
CHANNEL = "npdsBGack";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 42;
@ -1394,7 +1422,7 @@ DISPLAY_LINE
DISPLAY_LINE
{
CHANNEL = "nfpuSense";
CHANNEL = "npdsBg";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 43;
@ -1403,7 +1431,7 @@ DISPLAY_LINE
DISPLAY_LINE
{
CHANNEL = "npdsBr";
CHANNEL = "nfpuCe";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 44;
@ -1412,7 +1440,7 @@ DISPLAY_LINE
DISPLAY_LINE
{
CHANNEL = "bufDDir";
CHANNEL = "nfpuSense";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 45;
@ -1421,7 +1449,7 @@ DISPLAY_LINE
DISPLAY_LINE
{
CHANNEL = "nbufDhiEn";
CHANNEL = "npdsBr";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 46;
@ -1430,7 +1458,7 @@ DISPLAY_LINE
DISPLAY_LINE
{
CHANNEL = "nbufDlo1En";
CHANNEL = "bufDDir";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 47;
@ -1439,7 +1467,7 @@ DISPLAY_LINE
DISPLAY_LINE
{
CHANNEL = "nbufDlo2En";
CHANNEL = "nbufDhiEn";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 48;
@ -1448,7 +1476,7 @@ DISPLAY_LINE
DISPLAY_LINE
{
CHANNEL = "nbufAEn";
CHANNEL = "nbufDlo1En";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 49;
@ -1457,13 +1485,31 @@ DISPLAY_LINE
DISPLAY_LINE
{
CHANNEL = "nbufCEn";
CHANNEL = "nbufDlo2En";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 50;
TREE_LEVEL = 0;
}
DISPLAY_LINE
{
CHANNEL = "nbufAEn";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 51;
TREE_LEVEL = 0;
}
DISPLAY_LINE
{
CHANNEL = "nbufCEn";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 52;
TREE_LEVEL = 0;
}
TIME_BAR
{
TIME = 0;

356
paste.sv
View File

@ -13,8 +13,8 @@ module paste (
inout wire ncpuHalt, // 68030 halt signal (tristate)
input wire ncpuDS, // 68030 data strobe signal
input wire ncpuAS, // 68030 address strobe signal
output wire ncpuDsack0, // 68030 DS Ack 0 signal
output wire ncpuDsack1, // 68030 DS Ack 1 signal
inout wire ncpuDsack0, // 68030 DS Ack 0 signal
inout wire ncpuDsack1, // 68030 DS Ack 1 signal
input wire cpuSize0, // 68030 Size 0 signal
input wire cpuSize1, // 68030 Size 1 signal
input wire cpuA0, // 68030 Address 0 signal
@ -51,142 +51,111 @@ module paste (
// define state machine states
parameter
S0 = 2'h0,
S1 = 2'h1,
S2 = 2'h2;
S0 = 0,
S1 = 1,
S2 = 2,
S3 = 3,
S4 = 4,
S5 = 5,
S6 = 6,
S7 = 7,
S8 = 8;
// state machine state variables
logic [1:0] vmagenState; // state machine for npdsVma generator
logic [1:0] dsack68genState; // state machine for nDsack68 generator
logic [1:0] dsackSEgenState; // state machine for nDsackSE generator
logic [3:0] busState; // state machine for 68000 bus
logic [1:0] termState; // state machine for 68030 bus termination
logic [1:0] resetgenState; // state machine for nCpuReset generator
logic [3:0] vmagenCount; // state counter for npdsVma generator
wire nUD, nLD; // intermediate data strobe signals
// intermediate signals
wire nDsack68; // 6800 bus termination signal
wire nDsackSE; // SE bus termination signal
wire nUD; // SE upper data byte select
wire nLD; // SE lower data byte select
reg nAS; // SE address strobe
// D-latch to synchronize nAS to 8MHz clock
// 68000 bus state machine
// synchronous to 8MHz 68000 clock
always @(posedge pdsC8m or negedge npdsReset) begin
if(npdsReset == 0) nAS <= 1;
else nAS <= ncpuAS;
end
// state machine for npdsVma generation
always @(posedge pdsC8m or negedge npdsReset) begin
// sync state machine clocked by 8MHz system clock with async reset
if(npdsReset == 1'b0) begin
vmagenState <= S0;
vmagenCount <= 4'h0;
end else begin
case(vmagenState)
if(npdsReset == 0) busState <= S0;
else begin
case(busState)
S0 : begin
// wait for 6800 bus cycle to begin
// marked by assertion of npdsVpa and pdsClockE
if (npdsVpa == 1'b0 && pdsClockE == 1'b1) begin
vmagenState <= S1;
end else begin
vmagenState <= S0;
end
vmagenCount <= 4'h0;
// idle state, wait for cpu to begin bus cycle
if(ncpuAS == 0) busState <= S1;
else busState <= S0;
end
S1 : begin
// wait for deassertion of pdsClockE
if (pdsClockE == 1'b0) begin
vmagenState <= S2;
end else begin
vmagenState <= S1;
end
vmagenCount <= 4'h0;
// 68000 bus cycle state 2/3
// progress immediately
busState <= S2;
end
S2 : begin
// increment vmagenCount until == 4'hA
if (vmagenCount == 4'hA) begin
vmagenState <= S0;
vmagenCount <= 4'h0;
end else begin
vmagenState <= S2;
vmagenCount <= vmagenCount + 1'b1;
end
// 68000 bus cycle state 4/5
// wait for PDS DTACK or PDS VPA
if(npdsDtack == 0) busState <= S3;
else if(npdsVpa == 0) busState <= S4;
else busState <= S2;
end
S3 : begin
// 68000 bus cycle state 6/7
// end 68000 bus cycle
// progress immediately
busState <= S0;
end
S4 : begin
// 6800 bus cycle state 1
// wait for E clock = 0
if(pdsClockE == 0) busState <= S5;
else busState <= S4;
end
S5 : begin
// 6800 bus cycle state 2
// wait for E clock = 1
if(pdsClockE == 1) busState <= S6;
else busState <= S5;
end
S6 : begin
// 6800 bus cycle state 3
// progress immediately
busState <= S7;
end
S7 : begin
// 6800 bus cycle state 4
// progress immediately
busState <= S8;
end
S8 : begin
// 6800 bus cycle state 5
// progress immediately
busState <= S0;
end
default: begin
// how did we end up here? reset to S0
vmagenState <= S0;
vmagenCount <= 4'h0;
// how did we end up here?
busState <= S0;
end
endcase
end
end
// state machine for nDsack68 generation
// 68030 bus termination state machine
// synchronous to CPU clock
always @(posedge cpuClock or negedge npdsReset) begin
// sync state machine clocked by primary CPU clock with async reset
if(npdsReset == 1'b0) begin
dsack68genState <= S0;
end else begin
case(dsack68genState)
if(npdsReset == 0) termState <= S0;
else begin
case(termState)
S0 : begin
// wait for vmagenCount == 4'hA
if (vmagenCount == 4'hA) begin
dsack68genState <= S1;
end else begin
dsack68genState <= S0;
end
// idle, wait for busState
if(busState == S3 && pdsC8m == 1) termState <= S1;
else if(busState == S8 && pdsC8m == 1) termState <= S1;
else termState <= S0;
end
S1 : begin
// immediately progress to S2
dsack68genState <= S2;
// assert 68030 bus termination
// progress immediately
termState <= S2;
end
S2 : begin
// wait for vmagenCount to reset to 0
if (vmagenCount == 4'h0) begin
dsack68genState <= S0;
end else begin
dsack68genState <= S2;
end
// wait for busState
if(busState == S0) termState <= S0;
else termState <= S2;
end
default: begin
// shouldn't be here. reset to S0
dsack68genState <= S0;
end
endcase
end
end
// state machine for nDsackSE generation
always @(posedge cpuClock or negedge npdsReset) begin
// sync state machine clocked by primary CPU clock with async reset
if(npdsReset == 1'b0) begin
dsackSEgenState <= S0;
end else begin
case(dsackSEgenState)
S0 : begin
// wait for assertion of npdsDtack
if(npdsDtack == 1'b0) begin
dsackSEgenState <= S1;
end else begin
dsackSEgenState <= S0;
end
end
S1 : begin
// immediately proceed to S3
dsackSEgenState <= S2;
end
S2 : begin
// wait for deassertion of npdsDtack
if (npdsDtack == 1'b1) begin
dsackSEgenState <= S0;
end else begin
dsackSEgenState <= S2;
end
end
default: begin
// shouldn't be here. reset to S0
dsackSEgenState <= S0;
// how did we end up here?
termState <= S0;
end
endcase
end
@ -233,39 +202,30 @@ always @(posedge cpuClock or negedge npdsReset) begin
end
end
// and finally, our combinatorial logic
// combinatorial logic
assign nUD = ~(~cpuA0 || cpuRnW);
assign nLD = ~(cpuA0 || ~cpuSize0 || cpuSize1 || cpuRnW);
always_comb begin
// DSACK intermediary signals
if(dsack68genState == S1) begin
nDsack68 <= 1'b0;
// CPU reset signals
if(resetgenState != S2) begin
ncpuReset <= 1'b0;
ncpuHalt <= 1'b0;
end else begin
nDsack68 <= 1'b1;
end
if(dsackSEgenState == S1) begin
nDsackSE <= 1'b0;
end else begin
nDsackSE <= 1'b1;
ncpuReset <= 1'bz;
ncpuHalt <= 1'bz;
end
// Upper/Lower data strobes
if(npdsBg == 1) begin
npdsUds <= 1'bZ;
npdsLds <= 1'bZ;
// bus request & grant
if(resetgenState == S0) begin
npdsBr <= 1'bz;
end else begin
if(ncpuDS == 0 && nUD == 0) npdsUds <= 0;
else npdsUds <= 1;
if(ncpuDS == 0 && nLD == 0) npdsLds <= 0;
else npdsLds <= 1;
npdsBr <= 1'b0;
end
// Address strobe
if(npdsBg == 1) begin
npdsAs <= 1'bZ;
if(resetgenState == S2) begin
npdsBGack <= 1'b0;
end else begin
npdsAs <= nAS;
npdsBGack <= 1'bz;
end
// buffer enable signals
@ -299,69 +259,91 @@ always_comb begin
nbufAEn <= 1'b1;
nbufCEn <= 1'b1;
end
// data buffer direction
bufDDir <= cpuRnW;
// autovector request
if(cpuFC == 3'h7 && nDsack68 == 1'b0) begin
ncpuAvec <= 1'b0;
end else begin
ncpuAvec <= 1'b1;
// CPU cache inhibit
if(cpuAddrHi >= 4'h6) begin
ncpuCiin <= 1'b0;
end else begin
ncpuCiin <= 1'bz;
end
// VMA signal
if(vmagenCount >= 4'h3) begin
npdsVma <= 1'b0;
// Upper/Lower data strobes
if(npdsBg == 1) begin
npdsUds <= 1'bZ;
npdsLds <= 1'bZ;
end else begin
npdsVma <= 1'bz;
if(cpuRnW == 1 && busState == S1) begin
npdsUds <= nUD;
npdsLds <= nLD;
end else if (busState == S2 || busState == S3 ||
busState == S4 || busState == S5 ||
busState == S6 || busState == S7 ||
busState == S8) begin
npdsUds <= nUD;
npdsLds <= nLD;
end else begin
npdsUds <= 1;
npdsLds <= 1;
end
end
// DS Ack signals
// 8-bit: ncpuDsack1=1, ncpuDsack0=0
// 16-bit: ncpuDsack1=0, ncpuDsack0=1
// nDsack68 is always an 8-bit transfer
// nDsackSE is a 16-bit transfer below address $50,0000
// nDsackSE is an 8-bit transfer above address $50,0000, inclusive
if(
(
nDsack68 == 0 ||
(nDsackSE == 0 && cpuAddrHi >= 4'h5)
)
&& cpuFC < 3'h7 ) begin
ncpuDsack0 <= 0;
end else begin
ncpuDsack0 <= 1;
end
if(nDsackSE == 0 && cpuAddrHi < 4'h5 && cpuFC < 3'h7) begin
ncpuDsack1 <= 0;
end else begin
ncpuDsack1 <= 1;
// Address strobe
if(npdsBg == 1) npdsAs <= 1'bZ;
else begin
if(busState != S0) npdsAs <= 0;
else npdsAs <= 1;
end
// CPU reset signals
if(resetgenState != S2) begin
ncpuReset <= 1'b0;
ncpuHalt <= 1'b0;
end else begin
ncpuReset <= 1'bz;
ncpuHalt <= 1'bz;
// 6800 bus VMA signal
if(npdsBg == 1) npdsVma <= 1'bZ;
else begin
if(busState == S5 || busState == S6 ||
busState == S7 || busState == S8) begin
npdsVma <= 0;
end else npdsVma <= 1;
end
// bus request & grant
if(resetgenState == S0) begin
npdsBr <= 1'bz;
// 68030 bus termination signals
// FPU will terminate on its own
if(termState == S1) begin
if(cpuAddrHi < 4'h5 && cpuFC < 3'h7) begin
// RAM/ROM access - 16-bit
ncpuDsack0 <= 1'bZ;
ncpuDsack1 <= 0;
ncpuAvec <= 1'bZ;
ncpuBerr <= 1'bZ;
end else if(cpuAddrHi >= 4'h5 && cpuFC < 3'h7) begin
// peripheral access - 8-bit
ncpuDsack0 <= 0;
ncpuDsack1 <= 1'bZ;
ncpuAvec <= 1'bZ;
ncpuBerr <= 1'bZ;
end else if(cpuFC == 3'h7) begin
// autovector interrupt
ncpuAvec <= 0;
ncpuDsack0 <= 1'bZ;
ncpuDsack1 <= 1'bZ;
ncpuBerr <= 1'bZ;
end else begin
// this is an odd case. how did it happen?
// may as well throw an error
ncpuBerr <= 0;
ncpuDsack0 <= 1'bZ;
ncpuDsack1 <= 1'bZ;
ncpuAvec <= 1'bZ;
end
end else begin
npdsBr <= 1'b0;
end
if(resetgenState == S2) begin
npdsBGack <= 1'b0;
end else begin
npdsBGack <= 1'bz;
ncpuBerr <= 1'bZ;
ncpuDsack0 <= 1'bZ;
ncpuDsack1 <= 1'bZ;
ncpuAvec <= 1'bZ;
end
// FPU chip enable & presence detect
if(cpuAddrMid == 7'h11 && cpuFC == 3'h7) begin
if(cpuAddrMid == 7'h11 && cpuFC == 3'h7 && ncpuAS) begin
nfpuCe <= 1'b0;
if(nfpuSense == 1'b1) begin
// pulled high means FPU missing. assert bus error
@ -373,12 +355,6 @@ always_comb begin
nfpuCe <= 1'b1;
ncpuBerr <= 1'bz;
end
// CPU cache inhibit
if(cpuAddrHi >= 4'h6) begin
ncpuCiin <= 1'b0;
end else begin
ncpuCiin <= 1'bz;
end
end
endmodule