mirror of
https://github.com/techav-homebrew/SE-Exp30.git
synced 2025-01-24 21:33:52 +00:00
1519 lines
20 KiB
Plaintext
1519 lines
20 KiB
Plaintext
/*
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WARNING: Do NOT edit the input and output ports in this file in a text
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editor if you plan to continue editing the block that represents it in
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the Block Editor! File corruption is VERY likely to occur.
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*/
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/*
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Copyright (C) 1991-2013 Altera Corporation
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Your use of Altera Corporation's design tools, logic functions
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and other software and tools, and its AMPP partner logic
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functions, and any output files from any of the foregoing
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(including device programming or simulation files), and any
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associated documentation or information are expressly subject
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to the terms and conditions of the Altera Program License
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Subscription Agreement, Altera MegaCore Function License
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Agreement, or other applicable license agreement, including,
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without limitation, that your use is for the sole purpose of
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programming logic devices manufactured by Altera and sold by
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Altera or its authorized distributors. Please refer to the
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applicable agreement for further details.
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*/
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HEADER
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{
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VERSION = 1;
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TIME_UNIT = ns;
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DATA_OFFSET = 0.0;
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DATA_DURATION = 10000.0;
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SIMULATION_TIME = 0.0;
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GRID_PHASE = 0.0;
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GRID_PERIOD = 10.0;
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GRID_DUTY_CYCLE = 50;
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}
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SIGNAL("cpuFC")
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{
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VALUE_TYPE = NINE_LEVEL_BIT;
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SIGNAL_TYPE = BUS;
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WIDTH = 3;
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LSB_INDEX = 0;
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DIRECTION = INPUT;
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PARENT = "";
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}
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SIGNAL("cpuFC[2]")
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{
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VALUE_TYPE = NINE_LEVEL_BIT;
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SIGNAL_TYPE = SINGLE_BIT;
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WIDTH = 1;
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LSB_INDEX = -1;
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DIRECTION = INPUT;
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PARENT = "cpuFC";
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}
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SIGNAL("cpuFC[1]")
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{
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VALUE_TYPE = NINE_LEVEL_BIT;
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SIGNAL_TYPE = SINGLE_BIT;
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WIDTH = 1;
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LSB_INDEX = -1;
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DIRECTION = INPUT;
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PARENT = "cpuFC";
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}
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SIGNAL("cpuFC[0]")
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{
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VALUE_TYPE = NINE_LEVEL_BIT;
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SIGNAL_TYPE = SINGLE_BIT;
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WIDTH = 1;
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LSB_INDEX = -1;
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DIRECTION = INPUT;
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PARENT = "cpuFC";
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}
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SIGNAL("bufDDir")
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{
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VALUE_TYPE = NINE_LEVEL_BIT;
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SIGNAL_TYPE = SINGLE_BIT;
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WIDTH = 1;
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LSB_INDEX = -1;
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DIRECTION = OUTPUT;
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PARENT = "";
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}
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SIGNAL("cpuA0")
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{
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VALUE_TYPE = NINE_LEVEL_BIT;
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SIGNAL_TYPE = SINGLE_BIT;
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WIDTH = 1;
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LSB_INDEX = -1;
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DIRECTION = INPUT;
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PARENT = "";
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}
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SIGNAL("cpuAddrHi[20]")
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{
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VALUE_TYPE = NINE_LEVEL_BIT;
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SIGNAL_TYPE = SINGLE_BIT;
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WIDTH = 1;
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LSB_INDEX = -1;
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DIRECTION = INPUT;
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PARENT = "";
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}
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SIGNAL("cpuAddrHi[21]")
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{
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VALUE_TYPE = NINE_LEVEL_BIT;
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SIGNAL_TYPE = SINGLE_BIT;
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WIDTH = 1;
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LSB_INDEX = -1;
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DIRECTION = INPUT;
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PARENT = "";
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}
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SIGNAL("cpuAddrHi[22]")
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{
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VALUE_TYPE = NINE_LEVEL_BIT;
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SIGNAL_TYPE = SINGLE_BIT;
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WIDTH = 1;
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LSB_INDEX = -1;
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DIRECTION = INPUT;
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PARENT = "";
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}
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SIGNAL("cpuAddrHi[23]")
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{
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VALUE_TYPE = NINE_LEVEL_BIT;
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SIGNAL_TYPE = SINGLE_BIT;
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WIDTH = 1;
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LSB_INDEX = -1;
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DIRECTION = INPUT;
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PARENT = "";
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}
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SIGNAL("cpuAddrMid[13]")
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{
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VALUE_TYPE = NINE_LEVEL_BIT;
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SIGNAL_TYPE = SINGLE_BIT;
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WIDTH = 1;
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LSB_INDEX = -1;
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DIRECTION = INPUT;
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PARENT = "";
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}
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SIGNAL("cpuAddrMid[14]")
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{
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VALUE_TYPE = NINE_LEVEL_BIT;
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SIGNAL_TYPE = SINGLE_BIT;
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WIDTH = 1;
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LSB_INDEX = -1;
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DIRECTION = INPUT;
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PARENT = "";
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}
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SIGNAL("cpuAddrMid[15]")
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{
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VALUE_TYPE = NINE_LEVEL_BIT;
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SIGNAL_TYPE = SINGLE_BIT;
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WIDTH = 1;
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LSB_INDEX = -1;
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DIRECTION = INPUT;
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PARENT = "";
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}
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SIGNAL("cpuAddrMid[16]")
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{
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VALUE_TYPE = NINE_LEVEL_BIT;
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SIGNAL_TYPE = SINGLE_BIT;
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WIDTH = 1;
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LSB_INDEX = -1;
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DIRECTION = INPUT;
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PARENT = "";
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}
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SIGNAL("cpuAddrMid[17]")
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{
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VALUE_TYPE = NINE_LEVEL_BIT;
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SIGNAL_TYPE = SINGLE_BIT;
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WIDTH = 1;
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LSB_INDEX = -1;
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DIRECTION = INPUT;
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PARENT = "";
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}
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SIGNAL("cpuAddrMid[18]")
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{
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VALUE_TYPE = NINE_LEVEL_BIT;
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SIGNAL_TYPE = SINGLE_BIT;
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WIDTH = 1;
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LSB_INDEX = -1;
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DIRECTION = INPUT;
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PARENT = "";
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}
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SIGNAL("cpuAddrMid[19]")
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{
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VALUE_TYPE = NINE_LEVEL_BIT;
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SIGNAL_TYPE = SINGLE_BIT;
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WIDTH = 1;
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LSB_INDEX = -1;
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DIRECTION = INPUT;
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PARENT = "";
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}
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SIGNAL("cpuClock")
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{
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VALUE_TYPE = NINE_LEVEL_BIT;
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SIGNAL_TYPE = SINGLE_BIT;
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WIDTH = 1;
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LSB_INDEX = -1;
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DIRECTION = INPUT;
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PARENT = "";
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}
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SIGNAL("cpuRnW")
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{
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VALUE_TYPE = NINE_LEVEL_BIT;
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SIGNAL_TYPE = SINGLE_BIT;
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WIDTH = 1;
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LSB_INDEX = -1;
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DIRECTION = INPUT;
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PARENT = "";
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}
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SIGNAL("cpuSize0")
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{
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VALUE_TYPE = NINE_LEVEL_BIT;
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SIGNAL_TYPE = SINGLE_BIT;
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WIDTH = 1;
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LSB_INDEX = -1;
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DIRECTION = INPUT;
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PARENT = "";
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}
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SIGNAL("cpuSize1")
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{
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VALUE_TYPE = NINE_LEVEL_BIT;
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SIGNAL_TYPE = SINGLE_BIT;
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WIDTH = 1;
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LSB_INDEX = -1;
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DIRECTION = INPUT;
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PARENT = "";
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}
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SIGNAL("nbufAEn")
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{
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VALUE_TYPE = NINE_LEVEL_BIT;
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SIGNAL_TYPE = SINGLE_BIT;
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WIDTH = 1;
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LSB_INDEX = -1;
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DIRECTION = OUTPUT;
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PARENT = "";
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}
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SIGNAL("nbufCEn")
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{
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VALUE_TYPE = NINE_LEVEL_BIT;
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SIGNAL_TYPE = SINGLE_BIT;
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WIDTH = 1;
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LSB_INDEX = -1;
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DIRECTION = OUTPUT;
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PARENT = "";
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}
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SIGNAL("nbufDhiEn")
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{
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VALUE_TYPE = NINE_LEVEL_BIT;
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SIGNAL_TYPE = SINGLE_BIT;
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WIDTH = 1;
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LSB_INDEX = -1;
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DIRECTION = OUTPUT;
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PARENT = "";
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}
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SIGNAL("nbufDlo1En")
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{
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VALUE_TYPE = NINE_LEVEL_BIT;
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SIGNAL_TYPE = SINGLE_BIT;
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WIDTH = 1;
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LSB_INDEX = -1;
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DIRECTION = OUTPUT;
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PARENT = "";
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}
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SIGNAL("nbufDlo2En")
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{
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VALUE_TYPE = NINE_LEVEL_BIT;
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SIGNAL_TYPE = SINGLE_BIT;
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WIDTH = 1;
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LSB_INDEX = -1;
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DIRECTION = OUTPUT;
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PARENT = "";
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}
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SIGNAL("ncpuBG")
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{
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VALUE_TYPE = NINE_LEVEL_BIT;
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SIGNAL_TYPE = SINGLE_BIT;
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WIDTH = 1;
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LSB_INDEX = -1;
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DIRECTION = INPUT;
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PARENT = "";
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}
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SIGNAL("ncpuBerr")
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{
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VALUE_TYPE = NINE_LEVEL_BIT;
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SIGNAL_TYPE = SINGLE_BIT;
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WIDTH = 1;
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LSB_INDEX = -1;
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DIRECTION = BIDIR;
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PARENT = "";
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}
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SIGNAL("ncpuCiin")
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{
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VALUE_TYPE = NINE_LEVEL_BIT;
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SIGNAL_TYPE = SINGLE_BIT;
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WIDTH = 1;
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LSB_INDEX = -1;
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DIRECTION = BIDIR;
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PARENT = "";
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}
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SIGNAL("ncpuDS")
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{
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VALUE_TYPE = NINE_LEVEL_BIT;
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SIGNAL_TYPE = SINGLE_BIT;
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WIDTH = 1;
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LSB_INDEX = -1;
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DIRECTION = INPUT;
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PARENT = "";
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}
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SIGNAL("ncpuHalt")
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{
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VALUE_TYPE = NINE_LEVEL_BIT;
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SIGNAL_TYPE = SINGLE_BIT;
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WIDTH = 1;
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LSB_INDEX = -1;
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DIRECTION = BIDIR;
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PARENT = "";
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}
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SIGNAL("ncpuReset")
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{
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VALUE_TYPE = NINE_LEVEL_BIT;
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SIGNAL_TYPE = SINGLE_BIT;
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WIDTH = 1;
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LSB_INDEX = -1;
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DIRECTION = BIDIR;
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PARENT = "";
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}
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SIGNAL("nfpuCe")
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{
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VALUE_TYPE = NINE_LEVEL_BIT;
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SIGNAL_TYPE = SINGLE_BIT;
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WIDTH = 1;
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LSB_INDEX = -1;
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DIRECTION = OUTPUT;
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PARENT = "";
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}
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SIGNAL("nfpuSense")
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{
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VALUE_TYPE = NINE_LEVEL_BIT;
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SIGNAL_TYPE = SINGLE_BIT;
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WIDTH = 1;
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LSB_INDEX = -1;
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DIRECTION = INPUT;
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PARENT = "";
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}
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SIGNAL("npdsBGack")
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{
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VALUE_TYPE = NINE_LEVEL_BIT;
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SIGNAL_TYPE = SINGLE_BIT;
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WIDTH = 1;
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LSB_INDEX = -1;
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DIRECTION = OUTPUT;
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PARENT = "";
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}
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SIGNAL("npdsBg")
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{
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VALUE_TYPE = NINE_LEVEL_BIT;
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SIGNAL_TYPE = SINGLE_BIT;
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WIDTH = 1;
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LSB_INDEX = -1;
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DIRECTION = INPUT;
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PARENT = "";
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}
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SIGNAL("npdsBr")
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{
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VALUE_TYPE = NINE_LEVEL_BIT;
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SIGNAL_TYPE = SINGLE_BIT;
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WIDTH = 1;
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LSB_INDEX = -1;
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DIRECTION = OUTPUT;
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PARENT = "";
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}
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SIGNAL("npdsDtack")
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{
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VALUE_TYPE = NINE_LEVEL_BIT;
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SIGNAL_TYPE = SINGLE_BIT;
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WIDTH = 1;
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LSB_INDEX = -1;
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DIRECTION = INPUT;
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PARENT = "";
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}
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SIGNAL("npdsLds")
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{
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VALUE_TYPE = NINE_LEVEL_BIT;
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SIGNAL_TYPE = SINGLE_BIT;
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WIDTH = 1;
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LSB_INDEX = -1;
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DIRECTION = BIDIR;
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PARENT = "";
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}
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SIGNAL("npdsReset")
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{
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VALUE_TYPE = NINE_LEVEL_BIT;
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SIGNAL_TYPE = SINGLE_BIT;
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WIDTH = 1;
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LSB_INDEX = -1;
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DIRECTION = INPUT;
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PARENT = "";
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}
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SIGNAL("npdsUds")
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{
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VALUE_TYPE = NINE_LEVEL_BIT;
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SIGNAL_TYPE = SINGLE_BIT;
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WIDTH = 1;
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LSB_INDEX = -1;
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DIRECTION = BIDIR;
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PARENT = "";
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}
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SIGNAL("npdsVma")
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{
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VALUE_TYPE = NINE_LEVEL_BIT;
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SIGNAL_TYPE = SINGLE_BIT;
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WIDTH = 1;
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LSB_INDEX = -1;
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DIRECTION = BIDIR;
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PARENT = "";
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}
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SIGNAL("npdsVpa")
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{
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VALUE_TYPE = NINE_LEVEL_BIT;
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SIGNAL_TYPE = SINGLE_BIT;
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WIDTH = 1;
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LSB_INDEX = -1;
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DIRECTION = INPUT;
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PARENT = "";
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}
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SIGNAL("pdsC8m")
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{
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VALUE_TYPE = NINE_LEVEL_BIT;
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SIGNAL_TYPE = SINGLE_BIT;
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WIDTH = 1;
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LSB_INDEX = -1;
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DIRECTION = INPUT;
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PARENT = "";
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}
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SIGNAL("pdsClockE")
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{
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VALUE_TYPE = NINE_LEVEL_BIT;
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SIGNAL_TYPE = SINGLE_BIT;
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WIDTH = 1;
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LSB_INDEX = -1;
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DIRECTION = INPUT;
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PARENT = "";
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}
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GROUP("cpuAddrHi")
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{
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MEMBERS = "cpuAddrHi[20]", "cpuAddrHi[21]", "cpuAddrHi[22]", "cpuAddrHi[23]";
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}
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GROUP("cpuAddrMid")
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{
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MEMBERS = "cpuAddrMid[13]", "cpuAddrMid[14]", "cpuAddrMid[15]", "cpuAddrMid[16]", "cpuAddrMid[17]", "cpuAddrMid[18]", "cpuAddrMid[19]";
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}
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GROUP("cpuSize")
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{
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MEMBERS = "cpuSize0", "cpuSize1";
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}
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|
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|
SIGNAL("ncpuAvec")
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|
{
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VALUE_TYPE = NINE_LEVEL_BIT;
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SIGNAL_TYPE = SINGLE_BIT;
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WIDTH = 1;
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|
LSB_INDEX = -1;
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DIRECTION = OUTPUT;
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|
PARENT = "";
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}
|
|
|
|
SIGNAL("ncpuDsack0")
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|
{
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VALUE_TYPE = NINE_LEVEL_BIT;
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SIGNAL_TYPE = SINGLE_BIT;
|
|
WIDTH = 1;
|
|
LSB_INDEX = -1;
|
|
DIRECTION = BIDIR;
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|
PARENT = "";
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|
}
|
|
|
|
SIGNAL("ncpuDsack1")
|
|
{
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VALUE_TYPE = NINE_LEVEL_BIT;
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|
SIGNAL_TYPE = SINGLE_BIT;
|
|
WIDTH = 1;
|
|
LSB_INDEX = -1;
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|
DIRECTION = BIDIR;
|
|
PARENT = "";
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|
}
|
|
|
|
SIGNAL("ncpuAS")
|
|
{
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|
VALUE_TYPE = NINE_LEVEL_BIT;
|
|
SIGNAL_TYPE = SINGLE_BIT;
|
|
WIDTH = 1;
|
|
LSB_INDEX = -1;
|
|
DIRECTION = INPUT;
|
|
PARENT = "";
|
|
}
|
|
|
|
SIGNAL("npdsAs")
|
|
{
|
|
VALUE_TYPE = NINE_LEVEL_BIT;
|
|
SIGNAL_TYPE = SINGLE_BIT;
|
|
WIDTH = 1;
|
|
LSB_INDEX = -1;
|
|
DIRECTION = BIDIR;
|
|
PARENT = "";
|
|
}
|
|
|
|
TRANSITION_LIST("cpuFC[2]")
|
|
{
|
|
NODE
|
|
{
|
|
REPEAT = 1;
|
|
LEVEL 0 FOR 10000.0;
|
|
}
|
|
}
|
|
|
|
TRANSITION_LIST("cpuFC[1]")
|
|
{
|
|
NODE
|
|
{
|
|
REPEAT = 1;
|
|
LEVEL 0 FOR 10000.0;
|
|
}
|
|
}
|
|
|
|
TRANSITION_LIST("cpuFC[0]")
|
|
{
|
|
NODE
|
|
{
|
|
REPEAT = 1;
|
|
LEVEL 0 FOR 10000.0;
|
|
}
|
|
}
|
|
|
|
TRANSITION_LIST("bufDDir")
|
|
{
|
|
NODE
|
|
{
|
|
REPEAT = 1;
|
|
LEVEL X FOR 10000.0;
|
|
}
|
|
}
|
|
|
|
TRANSITION_LIST("cpuA0")
|
|
{
|
|
NODE
|
|
{
|
|
REPEAT = 1;
|
|
LEVEL 0 FOR 10000.0;
|
|
}
|
|
}
|
|
|
|
TRANSITION_LIST("cpuAddrHi[20]")
|
|
{
|
|
NODE
|
|
{
|
|
REPEAT = 1;
|
|
LEVEL 0 FOR 10000.0;
|
|
}
|
|
}
|
|
|
|
TRANSITION_LIST("cpuAddrHi[21]")
|
|
{
|
|
NODE
|
|
{
|
|
REPEAT = 1;
|
|
LEVEL 0 FOR 10000.0;
|
|
}
|
|
}
|
|
|
|
TRANSITION_LIST("cpuAddrHi[22]")
|
|
{
|
|
NODE
|
|
{
|
|
REPEAT = 1;
|
|
LEVEL 0 FOR 10000.0;
|
|
}
|
|
}
|
|
|
|
TRANSITION_LIST("cpuAddrHi[23]")
|
|
{
|
|
NODE
|
|
{
|
|
REPEAT = 1;
|
|
LEVEL 0 FOR 10000.0;
|
|
}
|
|
}
|
|
|
|
TRANSITION_LIST("cpuAddrMid[13]")
|
|
{
|
|
NODE
|
|
{
|
|
REPEAT = 1;
|
|
LEVEL 0 FOR 10000.0;
|
|
}
|
|
}
|
|
|
|
TRANSITION_LIST("cpuAddrMid[14]")
|
|
{
|
|
NODE
|
|
{
|
|
REPEAT = 1;
|
|
LEVEL 0 FOR 10000.0;
|
|
}
|
|
}
|
|
|
|
TRANSITION_LIST("cpuAddrMid[15]")
|
|
{
|
|
NODE
|
|
{
|
|
REPEAT = 1;
|
|
LEVEL 0 FOR 10000.0;
|
|
}
|
|
}
|
|
|
|
TRANSITION_LIST("cpuAddrMid[16]")
|
|
{
|
|
NODE
|
|
{
|
|
REPEAT = 1;
|
|
LEVEL 0 FOR 10000.0;
|
|
}
|
|
}
|
|
|
|
TRANSITION_LIST("cpuAddrMid[17]")
|
|
{
|
|
NODE
|
|
{
|
|
REPEAT = 1;
|
|
LEVEL 0 FOR 10000.0;
|
|
}
|
|
}
|
|
|
|
TRANSITION_LIST("cpuAddrMid[18]")
|
|
{
|
|
NODE
|
|
{
|
|
REPEAT = 1;
|
|
LEVEL 0 FOR 10000.0;
|
|
}
|
|
}
|
|
|
|
TRANSITION_LIST("cpuAddrMid[19]")
|
|
{
|
|
NODE
|
|
{
|
|
REPEAT = 1;
|
|
LEVEL 0 FOR 10000.0;
|
|
}
|
|
}
|
|
|
|
TRANSITION_LIST("cpuClock")
|
|
{
|
|
NODE
|
|
{
|
|
REPEAT = 1;
|
|
NODE
|
|
{
|
|
REPEAT = 500;
|
|
LEVEL 0 FOR 10.0;
|
|
LEVEL 1 FOR 10.0;
|
|
}
|
|
}
|
|
}
|
|
|
|
TRANSITION_LIST("cpuRnW")
|
|
{
|
|
NODE
|
|
{
|
|
REPEAT = 1;
|
|
LEVEL 0 FOR 10000.0;
|
|
}
|
|
}
|
|
|
|
TRANSITION_LIST("cpuSize0")
|
|
{
|
|
NODE
|
|
{
|
|
REPEAT = 1;
|
|
LEVEL 0 FOR 10000.0;
|
|
}
|
|
}
|
|
|
|
TRANSITION_LIST("cpuSize1")
|
|
{
|
|
NODE
|
|
{
|
|
REPEAT = 1;
|
|
LEVEL 0 FOR 10000.0;
|
|
}
|
|
}
|
|
|
|
TRANSITION_LIST("nbufAEn")
|
|
{
|
|
NODE
|
|
{
|
|
REPEAT = 1;
|
|
LEVEL X FOR 10000.0;
|
|
}
|
|
}
|
|
|
|
TRANSITION_LIST("nbufCEn")
|
|
{
|
|
NODE
|
|
{
|
|
REPEAT = 1;
|
|
LEVEL X FOR 10000.0;
|
|
}
|
|
}
|
|
|
|
TRANSITION_LIST("nbufDhiEn")
|
|
{
|
|
NODE
|
|
{
|
|
REPEAT = 1;
|
|
LEVEL X FOR 10000.0;
|
|
}
|
|
}
|
|
|
|
TRANSITION_LIST("nbufDlo1En")
|
|
{
|
|
NODE
|
|
{
|
|
REPEAT = 1;
|
|
LEVEL X FOR 10000.0;
|
|
}
|
|
}
|
|
|
|
TRANSITION_LIST("nbufDlo2En")
|
|
{
|
|
NODE
|
|
{
|
|
REPEAT = 1;
|
|
LEVEL X FOR 10000.0;
|
|
}
|
|
}
|
|
|
|
TRANSITION_LIST("ncpuBG")
|
|
{
|
|
NODE
|
|
{
|
|
REPEAT = 1;
|
|
LEVEL 1 FOR 10000.0;
|
|
}
|
|
}
|
|
|
|
TRANSITION_LIST("ncpuBerr")
|
|
{
|
|
NODE
|
|
{
|
|
REPEAT = 1;
|
|
LEVEL Z FOR 10000.0;
|
|
}
|
|
}
|
|
|
|
TRANSITION_LIST("ncpuCiin")
|
|
{
|
|
NODE
|
|
{
|
|
REPEAT = 1;
|
|
LEVEL Z FOR 10000.0;
|
|
}
|
|
}
|
|
|
|
TRANSITION_LIST("ncpuDS")
|
|
{
|
|
NODE
|
|
{
|
|
REPEAT = 1;
|
|
LEVEL 1 FOR 10000.0;
|
|
}
|
|
}
|
|
|
|
TRANSITION_LIST("ncpuHalt")
|
|
{
|
|
NODE
|
|
{
|
|
REPEAT = 1;
|
|
LEVEL Z FOR 10000.0;
|
|
}
|
|
}
|
|
|
|
TRANSITION_LIST("ncpuReset")
|
|
{
|
|
NODE
|
|
{
|
|
REPEAT = 1;
|
|
LEVEL Z FOR 10000.0;
|
|
}
|
|
}
|
|
|
|
TRANSITION_LIST("nfpuCe")
|
|
{
|
|
NODE
|
|
{
|
|
REPEAT = 1;
|
|
LEVEL X FOR 10000.0;
|
|
}
|
|
}
|
|
|
|
TRANSITION_LIST("nfpuSense")
|
|
{
|
|
NODE
|
|
{
|
|
REPEAT = 1;
|
|
LEVEL 0 FOR 10000.0;
|
|
}
|
|
}
|
|
|
|
TRANSITION_LIST("npdsBGack")
|
|
{
|
|
NODE
|
|
{
|
|
REPEAT = 1;
|
|
LEVEL X FOR 10000.0;
|
|
}
|
|
}
|
|
|
|
TRANSITION_LIST("npdsBg")
|
|
{
|
|
NODE
|
|
{
|
|
REPEAT = 1;
|
|
LEVEL 1 FOR 30.0;
|
|
LEVEL 0 FOR 9970.0;
|
|
}
|
|
}
|
|
|
|
TRANSITION_LIST("npdsBr")
|
|
{
|
|
NODE
|
|
{
|
|
REPEAT = 1;
|
|
LEVEL X FOR 10000.0;
|
|
}
|
|
}
|
|
|
|
TRANSITION_LIST("npdsDtack")
|
|
{
|
|
NODE
|
|
{
|
|
REPEAT = 1;
|
|
LEVEL 1 FOR 630.0;
|
|
LEVEL 0 FOR 440.0;
|
|
LEVEL 1 FOR 290.0;
|
|
LEVEL 0 FOR 410.0;
|
|
LEVEL 1 FOR 8230.0;
|
|
}
|
|
}
|
|
|
|
TRANSITION_LIST("npdsLds")
|
|
{
|
|
NODE
|
|
{
|
|
REPEAT = 1;
|
|
LEVEL Z FOR 10000.0;
|
|
}
|
|
}
|
|
|
|
TRANSITION_LIST("npdsReset")
|
|
{
|
|
NODE
|
|
{
|
|
REPEAT = 1;
|
|
LEVEL 0 FOR 10.0;
|
|
LEVEL 1 FOR 9990.0;
|
|
}
|
|
}
|
|
|
|
TRANSITION_LIST("npdsUds")
|
|
{
|
|
NODE
|
|
{
|
|
REPEAT = 1;
|
|
LEVEL Z FOR 10000.0;
|
|
}
|
|
}
|
|
|
|
TRANSITION_LIST("npdsVma")
|
|
{
|
|
NODE
|
|
{
|
|
REPEAT = 1;
|
|
LEVEL Z FOR 10000.0;
|
|
}
|
|
}
|
|
|
|
TRANSITION_LIST("npdsVpa")
|
|
{
|
|
NODE
|
|
{
|
|
REPEAT = 1;
|
|
LEVEL 1 FOR 10000.0;
|
|
}
|
|
}
|
|
|
|
TRANSITION_LIST("pdsC8m")
|
|
{
|
|
NODE
|
|
{
|
|
REPEAT = 1;
|
|
NODE
|
|
{
|
|
REPEAT = 80;
|
|
LEVEL 0 FOR 62.5;
|
|
LEVEL 1 FOR 62.5;
|
|
}
|
|
}
|
|
}
|
|
|
|
TRANSITION_LIST("pdsClockE")
|
|
{
|
|
NODE
|
|
{
|
|
REPEAT = 1;
|
|
NODE
|
|
{
|
|
REPEAT = 8;
|
|
LEVEL 0 FOR 625.0;
|
|
LEVEL 1 FOR 625.0;
|
|
}
|
|
}
|
|
}
|
|
|
|
TRANSITION_LIST("ncpuAvec")
|
|
{
|
|
NODE
|
|
{
|
|
REPEAT = 1;
|
|
LEVEL X FOR 10000.0;
|
|
}
|
|
}
|
|
|
|
TRANSITION_LIST("ncpuDsack0")
|
|
{
|
|
NODE
|
|
{
|
|
REPEAT = 1;
|
|
LEVEL Z FOR 10000.0;
|
|
}
|
|
}
|
|
|
|
TRANSITION_LIST("ncpuDsack1")
|
|
{
|
|
NODE
|
|
{
|
|
REPEAT = 1;
|
|
LEVEL Z FOR 10000.0;
|
|
}
|
|
}
|
|
|
|
TRANSITION_LIST("ncpuAS")
|
|
{
|
|
NODE
|
|
{
|
|
REPEAT = 1;
|
|
LEVEL 1 FOR 40.0;
|
|
LEVEL 0 FOR 870.0;
|
|
LEVEL 1 FOR 20.0;
|
|
LEVEL 0 FOR 740.0;
|
|
LEVEL 1 FOR 8330.0;
|
|
}
|
|
}
|
|
|
|
TRANSITION_LIST("npdsAs")
|
|
{
|
|
NODE
|
|
{
|
|
REPEAT = 1;
|
|
LEVEL Z FOR 10000.0;
|
|
}
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "npdsReset";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Binary;
|
|
TREE_INDEX = 0;
|
|
TREE_LEVEL = 0;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "cpuClock";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Binary;
|
|
TREE_INDEX = 1;
|
|
TREE_LEVEL = 0;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "pdsC8m";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Binary;
|
|
TREE_INDEX = 2;
|
|
TREE_LEVEL = 0;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "pdsClockE";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Binary;
|
|
TREE_INDEX = 3;
|
|
TREE_LEVEL = 0;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "cpuAddrHi";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Binary;
|
|
TREE_INDEX = 4;
|
|
TREE_LEVEL = 0;
|
|
CHILDREN = 5, 6, 7, 8;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "cpuAddrHi[20]";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Binary;
|
|
TREE_INDEX = 5;
|
|
TREE_LEVEL = 1;
|
|
PARENT = 4;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "cpuAddrHi[21]";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Binary;
|
|
TREE_INDEX = 6;
|
|
TREE_LEVEL = 1;
|
|
PARENT = 4;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "cpuAddrHi[22]";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Binary;
|
|
TREE_INDEX = 7;
|
|
TREE_LEVEL = 1;
|
|
PARENT = 4;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "cpuAddrHi[23]";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Binary;
|
|
TREE_INDEX = 8;
|
|
TREE_LEVEL = 1;
|
|
PARENT = 4;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "cpuAddrMid";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Binary;
|
|
TREE_INDEX = 9;
|
|
TREE_LEVEL = 0;
|
|
CHILDREN = 10, 11, 12, 13, 14, 15, 16;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "cpuAddrMid[13]";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Binary;
|
|
TREE_INDEX = 10;
|
|
TREE_LEVEL = 1;
|
|
PARENT = 9;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "cpuAddrMid[14]";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Binary;
|
|
TREE_INDEX = 11;
|
|
TREE_LEVEL = 1;
|
|
PARENT = 9;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "cpuAddrMid[15]";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Binary;
|
|
TREE_INDEX = 12;
|
|
TREE_LEVEL = 1;
|
|
PARENT = 9;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "cpuAddrMid[16]";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Binary;
|
|
TREE_INDEX = 13;
|
|
TREE_LEVEL = 1;
|
|
PARENT = 9;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "cpuAddrMid[17]";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Binary;
|
|
TREE_INDEX = 14;
|
|
TREE_LEVEL = 1;
|
|
PARENT = 9;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "cpuAddrMid[18]";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Binary;
|
|
TREE_INDEX = 15;
|
|
TREE_LEVEL = 1;
|
|
PARENT = 9;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "cpuAddrMid[19]";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Binary;
|
|
TREE_INDEX = 16;
|
|
TREE_LEVEL = 1;
|
|
PARENT = 9;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "cpuA0";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Binary;
|
|
TREE_INDEX = 17;
|
|
TREE_LEVEL = 0;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "cpuSize";
|
|
EXPAND_STATUS = EXPANDED;
|
|
RADIX = Binary;
|
|
TREE_INDEX = 18;
|
|
TREE_LEVEL = 0;
|
|
CHILDREN = 19, 20;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "cpuSize0";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Binary;
|
|
TREE_INDEX = 19;
|
|
TREE_LEVEL = 1;
|
|
PARENT = 18;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "cpuSize1";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Binary;
|
|
TREE_INDEX = 20;
|
|
TREE_LEVEL = 1;
|
|
PARENT = 18;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "cpuFC";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Binary;
|
|
TREE_INDEX = 21;
|
|
TREE_LEVEL = 0;
|
|
CHILDREN = 22, 23, 24;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "cpuFC[2]";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Binary;
|
|
TREE_INDEX = 22;
|
|
TREE_LEVEL = 1;
|
|
PARENT = 21;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "cpuFC[1]";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Binary;
|
|
TREE_INDEX = 23;
|
|
TREE_LEVEL = 1;
|
|
PARENT = 21;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "cpuFC[0]";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Binary;
|
|
TREE_INDEX = 24;
|
|
TREE_LEVEL = 1;
|
|
PARENT = 21;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "cpuRnW";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Binary;
|
|
TREE_INDEX = 25;
|
|
TREE_LEVEL = 0;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "ncpuDS";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Binary;
|
|
TREE_INDEX = 26;
|
|
TREE_LEVEL = 0;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "ncpuAS";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Binary;
|
|
TREE_INDEX = 27;
|
|
TREE_LEVEL = 0;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "npdsAs";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Binary;
|
|
TREE_INDEX = 28;
|
|
TREE_LEVEL = 0;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "ncpuBG";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Binary;
|
|
TREE_INDEX = 29;
|
|
TREE_LEVEL = 0;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "ncpuBerr";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Binary;
|
|
TREE_INDEX = 30;
|
|
TREE_LEVEL = 0;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "ncpuCiin";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Binary;
|
|
TREE_INDEX = 31;
|
|
TREE_LEVEL = 0;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "ncpuAvec";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Binary;
|
|
TREE_INDEX = 32;
|
|
TREE_LEVEL = 0;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "ncpuDsack0";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Binary;
|
|
TREE_INDEX = 33;
|
|
TREE_LEVEL = 0;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "ncpuDsack1";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Binary;
|
|
TREE_INDEX = 34;
|
|
TREE_LEVEL = 0;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "npdsDtack";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Binary;
|
|
TREE_INDEX = 35;
|
|
TREE_LEVEL = 0;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "npdsUds";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Binary;
|
|
TREE_INDEX = 36;
|
|
TREE_LEVEL = 0;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "npdsLds";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Binary;
|
|
TREE_INDEX = 37;
|
|
TREE_LEVEL = 0;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "npdsVma";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Binary;
|
|
TREE_INDEX = 38;
|
|
TREE_LEVEL = 0;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "npdsVpa";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Binary;
|
|
TREE_INDEX = 39;
|
|
TREE_LEVEL = 0;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "ncpuHalt";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Binary;
|
|
TREE_INDEX = 40;
|
|
TREE_LEVEL = 0;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "ncpuReset";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Binary;
|
|
TREE_INDEX = 41;
|
|
TREE_LEVEL = 0;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "npdsBGack";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Binary;
|
|
TREE_INDEX = 42;
|
|
TREE_LEVEL = 0;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "npdsBg";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Binary;
|
|
TREE_INDEX = 43;
|
|
TREE_LEVEL = 0;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "nfpuCe";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Binary;
|
|
TREE_INDEX = 44;
|
|
TREE_LEVEL = 0;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "nfpuSense";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Binary;
|
|
TREE_INDEX = 45;
|
|
TREE_LEVEL = 0;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "npdsBr";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Binary;
|
|
TREE_INDEX = 46;
|
|
TREE_LEVEL = 0;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "bufDDir";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Binary;
|
|
TREE_INDEX = 47;
|
|
TREE_LEVEL = 0;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "nbufDhiEn";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Binary;
|
|
TREE_INDEX = 48;
|
|
TREE_LEVEL = 0;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "nbufDlo1En";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Binary;
|
|
TREE_INDEX = 49;
|
|
TREE_LEVEL = 0;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "nbufDlo2En";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Binary;
|
|
TREE_INDEX = 50;
|
|
TREE_LEVEL = 0;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "nbufAEn";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Binary;
|
|
TREE_INDEX = 51;
|
|
TREE_LEVEL = 0;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "nbufCEn";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Binary;
|
|
TREE_INDEX = 52;
|
|
TREE_LEVEL = 0;
|
|
}
|
|
|
|
TIME_BAR
|
|
{
|
|
TIME = 0;
|
|
MASTER = TRUE;
|
|
}
|
|
;
|