1680 lines
22 KiB
Plaintext
1680 lines
22 KiB
Plaintext
/*
|
|
WARNING: Do NOT edit the input and output ports in this file in a text
|
|
editor if you plan to continue editing the block that represents it in
|
|
the Block Editor! File corruption is VERY likely to occur.
|
|
*/
|
|
|
|
/*
|
|
Copyright (C) 1991-2013 Altera Corporation
|
|
Your use of Altera Corporation's design tools, logic functions
|
|
and other software and tools, and its AMPP partner logic
|
|
functions, and any output files from any of the foregoing
|
|
(including device programming or simulation files), and any
|
|
associated documentation or information are expressly subject
|
|
to the terms and conditions of the Altera Program License
|
|
Subscription Agreement, Altera MegaCore Function License
|
|
Agreement, or other applicable license agreement, including,
|
|
without limitation, that your use is for the sole purpose of
|
|
programming logic devices manufactured by Altera and sold by
|
|
Altera or its authorized distributors. Please refer to the
|
|
applicable agreement for further details.
|
|
*/
|
|
|
|
HEADER
|
|
{
|
|
VERSION = 1;
|
|
TIME_UNIT = ns;
|
|
DATA_OFFSET = 0.0;
|
|
DATA_DURATION = 10000.0;
|
|
SIMULATION_TIME = 0.0;
|
|
GRID_PHASE = 0.0;
|
|
GRID_PERIOD = 10.0;
|
|
GRID_DUTY_CYCLE = 50;
|
|
}
|
|
|
|
SIGNAL("cpuFC")
|
|
{
|
|
VALUE_TYPE = NINE_LEVEL_BIT;
|
|
SIGNAL_TYPE = BUS;
|
|
WIDTH = 3;
|
|
LSB_INDEX = 0;
|
|
DIRECTION = INPUT;
|
|
PARENT = "";
|
|
}
|
|
|
|
SIGNAL("cpuFC[2]")
|
|
{
|
|
VALUE_TYPE = NINE_LEVEL_BIT;
|
|
SIGNAL_TYPE = SINGLE_BIT;
|
|
WIDTH = 1;
|
|
LSB_INDEX = -1;
|
|
DIRECTION = INPUT;
|
|
PARENT = "cpuFC";
|
|
}
|
|
|
|
SIGNAL("cpuFC[1]")
|
|
{
|
|
VALUE_TYPE = NINE_LEVEL_BIT;
|
|
SIGNAL_TYPE = SINGLE_BIT;
|
|
WIDTH = 1;
|
|
LSB_INDEX = -1;
|
|
DIRECTION = INPUT;
|
|
PARENT = "cpuFC";
|
|
}
|
|
|
|
SIGNAL("cpuFC[0]")
|
|
{
|
|
VALUE_TYPE = NINE_LEVEL_BIT;
|
|
SIGNAL_TYPE = SINGLE_BIT;
|
|
WIDTH = 1;
|
|
LSB_INDEX = -1;
|
|
DIRECTION = INPUT;
|
|
PARENT = "cpuFC";
|
|
}
|
|
|
|
SIGNAL("bufACEn")
|
|
{
|
|
VALUE_TYPE = NINE_LEVEL_BIT;
|
|
SIGNAL_TYPE = SINGLE_BIT;
|
|
WIDTH = 1;
|
|
LSB_INDEX = -1;
|
|
DIRECTION = OUTPUT;
|
|
PARENT = "";
|
|
}
|
|
|
|
SIGNAL("bufCCEn")
|
|
{
|
|
VALUE_TYPE = NINE_LEVEL_BIT;
|
|
SIGNAL_TYPE = SINGLE_BIT;
|
|
WIDTH = 1;
|
|
LSB_INDEX = -1;
|
|
DIRECTION = OUTPUT;
|
|
PARENT = "";
|
|
}
|
|
|
|
SIGNAL("bufDDIR")
|
|
{
|
|
VALUE_TYPE = NINE_LEVEL_BIT;
|
|
SIGNAL_TYPE = SINGLE_BIT;
|
|
WIDTH = 1;
|
|
LSB_INDEX = -1;
|
|
DIRECTION = OUTPUT;
|
|
PARENT = "";
|
|
}
|
|
|
|
SIGNAL("bufDHICEn")
|
|
{
|
|
VALUE_TYPE = NINE_LEVEL_BIT;
|
|
SIGNAL_TYPE = SINGLE_BIT;
|
|
WIDTH = 1;
|
|
LSB_INDEX = -1;
|
|
DIRECTION = OUTPUT;
|
|
PARENT = "";
|
|
}
|
|
|
|
SIGNAL("bufDLO1CEn")
|
|
{
|
|
VALUE_TYPE = NINE_LEVEL_BIT;
|
|
SIGNAL_TYPE = SINGLE_BIT;
|
|
WIDTH = 1;
|
|
LSB_INDEX = -1;
|
|
DIRECTION = OUTPUT;
|
|
PARENT = "";
|
|
}
|
|
|
|
SIGNAL("bufDLO2CEn")
|
|
{
|
|
VALUE_TYPE = NINE_LEVEL_BIT;
|
|
SIGNAL_TYPE = SINGLE_BIT;
|
|
WIDTH = 1;
|
|
LSB_INDEX = -1;
|
|
DIRECTION = OUTPUT;
|
|
PARENT = "";
|
|
}
|
|
|
|
SIGNAL("cpuA0")
|
|
{
|
|
VALUE_TYPE = NINE_LEVEL_BIT;
|
|
SIGNAL_TYPE = SINGLE_BIT;
|
|
WIDTH = 1;
|
|
LSB_INDEX = -1;
|
|
DIRECTION = INPUT;
|
|
PARENT = "";
|
|
}
|
|
|
|
SIGNAL("cpuAHI")
|
|
{
|
|
VALUE_TYPE = NINE_LEVEL_BIT;
|
|
SIGNAL_TYPE = BUS;
|
|
WIDTH = 4;
|
|
LSB_INDEX = 0;
|
|
DIRECTION = INPUT;
|
|
PARENT = "";
|
|
}
|
|
|
|
SIGNAL("cpuAHI[3]")
|
|
{
|
|
VALUE_TYPE = NINE_LEVEL_BIT;
|
|
SIGNAL_TYPE = SINGLE_BIT;
|
|
WIDTH = 1;
|
|
LSB_INDEX = -1;
|
|
DIRECTION = INPUT;
|
|
PARENT = "cpuAHI";
|
|
}
|
|
|
|
SIGNAL("cpuAHI[2]")
|
|
{
|
|
VALUE_TYPE = NINE_LEVEL_BIT;
|
|
SIGNAL_TYPE = SINGLE_BIT;
|
|
WIDTH = 1;
|
|
LSB_INDEX = -1;
|
|
DIRECTION = INPUT;
|
|
PARENT = "cpuAHI";
|
|
}
|
|
|
|
SIGNAL("cpuAHI[1]")
|
|
{
|
|
VALUE_TYPE = NINE_LEVEL_BIT;
|
|
SIGNAL_TYPE = SINGLE_BIT;
|
|
WIDTH = 1;
|
|
LSB_INDEX = -1;
|
|
DIRECTION = INPUT;
|
|
PARENT = "cpuAHI";
|
|
}
|
|
|
|
SIGNAL("cpuAHI[0]")
|
|
{
|
|
VALUE_TYPE = NINE_LEVEL_BIT;
|
|
SIGNAL_TYPE = SINGLE_BIT;
|
|
WIDTH = 1;
|
|
LSB_INDEX = -1;
|
|
DIRECTION = INPUT;
|
|
PARENT = "cpuAHI";
|
|
}
|
|
|
|
SIGNAL("cpuAMID")
|
|
{
|
|
VALUE_TYPE = NINE_LEVEL_BIT;
|
|
SIGNAL_TYPE = BUS;
|
|
WIDTH = 7;
|
|
LSB_INDEX = 0;
|
|
DIRECTION = INPUT;
|
|
PARENT = "";
|
|
}
|
|
|
|
SIGNAL("cpuAMID[6]")
|
|
{
|
|
VALUE_TYPE = NINE_LEVEL_BIT;
|
|
SIGNAL_TYPE = SINGLE_BIT;
|
|
WIDTH = 1;
|
|
LSB_INDEX = -1;
|
|
DIRECTION = INPUT;
|
|
PARENT = "cpuAMID";
|
|
}
|
|
|
|
SIGNAL("cpuAMID[5]")
|
|
{
|
|
VALUE_TYPE = NINE_LEVEL_BIT;
|
|
SIGNAL_TYPE = SINGLE_BIT;
|
|
WIDTH = 1;
|
|
LSB_INDEX = -1;
|
|
DIRECTION = INPUT;
|
|
PARENT = "cpuAMID";
|
|
}
|
|
|
|
SIGNAL("cpuAMID[4]")
|
|
{
|
|
VALUE_TYPE = NINE_LEVEL_BIT;
|
|
SIGNAL_TYPE = SINGLE_BIT;
|
|
WIDTH = 1;
|
|
LSB_INDEX = -1;
|
|
DIRECTION = INPUT;
|
|
PARENT = "cpuAMID";
|
|
}
|
|
|
|
SIGNAL("cpuAMID[3]")
|
|
{
|
|
VALUE_TYPE = NINE_LEVEL_BIT;
|
|
SIGNAL_TYPE = SINGLE_BIT;
|
|
WIDTH = 1;
|
|
LSB_INDEX = -1;
|
|
DIRECTION = INPUT;
|
|
PARENT = "cpuAMID";
|
|
}
|
|
|
|
SIGNAL("cpuAMID[2]")
|
|
{
|
|
VALUE_TYPE = NINE_LEVEL_BIT;
|
|
SIGNAL_TYPE = SINGLE_BIT;
|
|
WIDTH = 1;
|
|
LSB_INDEX = -1;
|
|
DIRECTION = INPUT;
|
|
PARENT = "cpuAMID";
|
|
}
|
|
|
|
SIGNAL("cpuAMID[1]")
|
|
{
|
|
VALUE_TYPE = NINE_LEVEL_BIT;
|
|
SIGNAL_TYPE = SINGLE_BIT;
|
|
WIDTH = 1;
|
|
LSB_INDEX = -1;
|
|
DIRECTION = INPUT;
|
|
PARENT = "cpuAMID";
|
|
}
|
|
|
|
SIGNAL("cpuAMID[0]")
|
|
{
|
|
VALUE_TYPE = NINE_LEVEL_BIT;
|
|
SIGNAL_TYPE = SINGLE_BIT;
|
|
WIDTH = 1;
|
|
LSB_INDEX = -1;
|
|
DIRECTION = INPUT;
|
|
PARENT = "cpuAMID";
|
|
}
|
|
|
|
SIGNAL("cpuASn")
|
|
{
|
|
VALUE_TYPE = NINE_LEVEL_BIT;
|
|
SIGNAL_TYPE = SINGLE_BIT;
|
|
WIDTH = 1;
|
|
LSB_INDEX = -1;
|
|
DIRECTION = INPUT;
|
|
PARENT = "";
|
|
}
|
|
|
|
SIGNAL("cpuAVECn")
|
|
{
|
|
VALUE_TYPE = NINE_LEVEL_BIT;
|
|
SIGNAL_TYPE = SINGLE_BIT;
|
|
WIDTH = 1;
|
|
LSB_INDEX = -1;
|
|
DIRECTION = OUTPUT;
|
|
PARENT = "";
|
|
}
|
|
|
|
SIGNAL("cpuBERRn")
|
|
{
|
|
VALUE_TYPE = NINE_LEVEL_BIT;
|
|
SIGNAL_TYPE = SINGLE_BIT;
|
|
WIDTH = 1;
|
|
LSB_INDEX = -1;
|
|
DIRECTION = OUTPUT;
|
|
PARENT = "";
|
|
}
|
|
|
|
SIGNAL("cpuBGn")
|
|
{
|
|
VALUE_TYPE = NINE_LEVEL_BIT;
|
|
SIGNAL_TYPE = SINGLE_BIT;
|
|
WIDTH = 1;
|
|
LSB_INDEX = -1;
|
|
DIRECTION = INPUT;
|
|
PARENT = "";
|
|
}
|
|
|
|
SIGNAL("cpuCIINn")
|
|
{
|
|
VALUE_TYPE = NINE_LEVEL_BIT;
|
|
SIGNAL_TYPE = SINGLE_BIT;
|
|
WIDTH = 1;
|
|
LSB_INDEX = -1;
|
|
DIRECTION = OUTPUT;
|
|
PARENT = "";
|
|
}
|
|
|
|
SIGNAL("cpuClock")
|
|
{
|
|
VALUE_TYPE = NINE_LEVEL_BIT;
|
|
SIGNAL_TYPE = SINGLE_BIT;
|
|
WIDTH = 1;
|
|
LSB_INDEX = -1;
|
|
DIRECTION = INPUT;
|
|
PARENT = "";
|
|
}
|
|
|
|
SIGNAL("cpuDSACK0nz")
|
|
{
|
|
VALUE_TYPE = NINE_LEVEL_BIT;
|
|
SIGNAL_TYPE = SINGLE_BIT;
|
|
WIDTH = 1;
|
|
LSB_INDEX = -1;
|
|
DIRECTION = BIDIR;
|
|
PARENT = "";
|
|
}
|
|
|
|
SIGNAL("cpuDSACK1nz")
|
|
{
|
|
VALUE_TYPE = NINE_LEVEL_BIT;
|
|
SIGNAL_TYPE = SINGLE_BIT;
|
|
WIDTH = 1;
|
|
LSB_INDEX = -1;
|
|
DIRECTION = BIDIR;
|
|
PARENT = "";
|
|
}
|
|
|
|
SIGNAL("cpuDSn")
|
|
{
|
|
VALUE_TYPE = NINE_LEVEL_BIT;
|
|
SIGNAL_TYPE = SINGLE_BIT;
|
|
WIDTH = 1;
|
|
LSB_INDEX = -1;
|
|
DIRECTION = INPUT;
|
|
PARENT = "";
|
|
}
|
|
|
|
SIGNAL("cpuHALTnz")
|
|
{
|
|
VALUE_TYPE = NINE_LEVEL_BIT;
|
|
SIGNAL_TYPE = SINGLE_BIT;
|
|
WIDTH = 1;
|
|
LSB_INDEX = -1;
|
|
DIRECTION = BIDIR;
|
|
PARENT = "";
|
|
}
|
|
|
|
SIGNAL("cpuRESETnz")
|
|
{
|
|
VALUE_TYPE = NINE_LEVEL_BIT;
|
|
SIGNAL_TYPE = SINGLE_BIT;
|
|
WIDTH = 1;
|
|
LSB_INDEX = -1;
|
|
DIRECTION = BIDIR;
|
|
PARENT = "";
|
|
}
|
|
|
|
SIGNAL("cpuRnW")
|
|
{
|
|
VALUE_TYPE = NINE_LEVEL_BIT;
|
|
SIGNAL_TYPE = SINGLE_BIT;
|
|
WIDTH = 1;
|
|
LSB_INDEX = -1;
|
|
DIRECTION = INPUT;
|
|
PARENT = "";
|
|
}
|
|
|
|
SIGNAL("cpuSIZE0")
|
|
{
|
|
VALUE_TYPE = NINE_LEVEL_BIT;
|
|
SIGNAL_TYPE = SINGLE_BIT;
|
|
WIDTH = 1;
|
|
LSB_INDEX = -1;
|
|
DIRECTION = INPUT;
|
|
PARENT = "";
|
|
}
|
|
|
|
SIGNAL("cpuSIZE1")
|
|
{
|
|
VALUE_TYPE = NINE_LEVEL_BIT;
|
|
SIGNAL_TYPE = SINGLE_BIT;
|
|
WIDTH = 1;
|
|
LSB_INDEX = -1;
|
|
DIRECTION = INPUT;
|
|
PARENT = "";
|
|
}
|
|
|
|
SIGNAL("fpuCEn")
|
|
{
|
|
VALUE_TYPE = NINE_LEVEL_BIT;
|
|
SIGNAL_TYPE = SINGLE_BIT;
|
|
WIDTH = 1;
|
|
LSB_INDEX = -1;
|
|
DIRECTION = OUTPUT;
|
|
PARENT = "";
|
|
}
|
|
|
|
SIGNAL("fpuSENSEn")
|
|
{
|
|
VALUE_TYPE = NINE_LEVEL_BIT;
|
|
SIGNAL_TYPE = SINGLE_BIT;
|
|
WIDTH = 1;
|
|
LSB_INDEX = -1;
|
|
DIRECTION = INPUT;
|
|
PARENT = "";
|
|
}
|
|
|
|
SIGNAL("pdsASnz")
|
|
{
|
|
VALUE_TYPE = NINE_LEVEL_BIT;
|
|
SIGNAL_TYPE = SINGLE_BIT;
|
|
WIDTH = 1;
|
|
LSB_INDEX = -1;
|
|
DIRECTION = BIDIR;
|
|
PARENT = "";
|
|
}
|
|
|
|
SIGNAL("pdsBERRn")
|
|
{
|
|
VALUE_TYPE = NINE_LEVEL_BIT;
|
|
SIGNAL_TYPE = SINGLE_BIT;
|
|
WIDTH = 1;
|
|
LSB_INDEX = -1;
|
|
DIRECTION = INPUT;
|
|
PARENT = "";
|
|
}
|
|
|
|
SIGNAL("pdsBGACKn")
|
|
{
|
|
VALUE_TYPE = NINE_LEVEL_BIT;
|
|
SIGNAL_TYPE = SINGLE_BIT;
|
|
WIDTH = 1;
|
|
LSB_INDEX = -1;
|
|
DIRECTION = OUTPUT;
|
|
PARENT = "";
|
|
}
|
|
|
|
SIGNAL("pdsBGn")
|
|
{
|
|
VALUE_TYPE = NINE_LEVEL_BIT;
|
|
SIGNAL_TYPE = SINGLE_BIT;
|
|
WIDTH = 1;
|
|
LSB_INDEX = -1;
|
|
DIRECTION = INPUT;
|
|
PARENT = "";
|
|
}
|
|
|
|
SIGNAL("pdsBRn")
|
|
{
|
|
VALUE_TYPE = NINE_LEVEL_BIT;
|
|
SIGNAL_TYPE = SINGLE_BIT;
|
|
WIDTH = 1;
|
|
LSB_INDEX = -1;
|
|
DIRECTION = OUTPUT;
|
|
PARENT = "";
|
|
}
|
|
|
|
SIGNAL("pdsC8M")
|
|
{
|
|
VALUE_TYPE = NINE_LEVEL_BIT;
|
|
SIGNAL_TYPE = SINGLE_BIT;
|
|
WIDTH = 1;
|
|
LSB_INDEX = -1;
|
|
DIRECTION = INPUT;
|
|
PARENT = "";
|
|
}
|
|
|
|
SIGNAL("pdsClockE")
|
|
{
|
|
VALUE_TYPE = NINE_LEVEL_BIT;
|
|
SIGNAL_TYPE = SINGLE_BIT;
|
|
WIDTH = 1;
|
|
LSB_INDEX = -1;
|
|
DIRECTION = OUTPUT;
|
|
PARENT = "";
|
|
}
|
|
|
|
SIGNAL("pdsDTACKn")
|
|
{
|
|
VALUE_TYPE = NINE_LEVEL_BIT;
|
|
SIGNAL_TYPE = SINGLE_BIT;
|
|
WIDTH = 1;
|
|
LSB_INDEX = -1;
|
|
DIRECTION = INPUT;
|
|
PARENT = "";
|
|
}
|
|
|
|
SIGNAL("pdsLDSnz")
|
|
{
|
|
VALUE_TYPE = NINE_LEVEL_BIT;
|
|
SIGNAL_TYPE = SINGLE_BIT;
|
|
WIDTH = 1;
|
|
LSB_INDEX = -1;
|
|
DIRECTION = BIDIR;
|
|
PARENT = "";
|
|
}
|
|
|
|
SIGNAL("pdsRESETn")
|
|
{
|
|
VALUE_TYPE = NINE_LEVEL_BIT;
|
|
SIGNAL_TYPE = SINGLE_BIT;
|
|
WIDTH = 1;
|
|
LSB_INDEX = -1;
|
|
DIRECTION = INPUT;
|
|
PARENT = "";
|
|
}
|
|
|
|
SIGNAL("pdsUDSnz")
|
|
{
|
|
VALUE_TYPE = NINE_LEVEL_BIT;
|
|
SIGNAL_TYPE = SINGLE_BIT;
|
|
WIDTH = 1;
|
|
LSB_INDEX = -1;
|
|
DIRECTION = BIDIR;
|
|
PARENT = "";
|
|
}
|
|
|
|
SIGNAL("pdsVMAnz")
|
|
{
|
|
VALUE_TYPE = NINE_LEVEL_BIT;
|
|
SIGNAL_TYPE = SINGLE_BIT;
|
|
WIDTH = 1;
|
|
LSB_INDEX = -1;
|
|
DIRECTION = BIDIR;
|
|
PARENT = "";
|
|
}
|
|
|
|
SIGNAL("pdsVPAn")
|
|
{
|
|
VALUE_TYPE = NINE_LEVEL_BIT;
|
|
SIGNAL_TYPE = SINGLE_BIT;
|
|
WIDTH = 1;
|
|
LSB_INDEX = -1;
|
|
DIRECTION = INPUT;
|
|
PARENT = "";
|
|
}
|
|
|
|
SIGNAL("pdsPMCYCn")
|
|
{
|
|
VALUE_TYPE = NINE_LEVEL_BIT;
|
|
SIGNAL_TYPE = SINGLE_BIT;
|
|
WIDTH = 1;
|
|
LSB_INDEX = -1;
|
|
DIRECTION = INPUT;
|
|
PARENT = "";
|
|
}
|
|
|
|
TRANSITION_LIST("cpuFC[2]")
|
|
{
|
|
NODE
|
|
{
|
|
REPEAT = 1;
|
|
LEVEL 0 FOR 2580.0;
|
|
LEVEL 1 FOR 1160.0;
|
|
LEVEL 0 FOR 400.0;
|
|
LEVEL 1 FOR 120.0;
|
|
LEVEL 0 FOR 5740.0;
|
|
}
|
|
}
|
|
|
|
TRANSITION_LIST("cpuFC[1]")
|
|
{
|
|
NODE
|
|
{
|
|
REPEAT = 1;
|
|
LEVEL 0 FOR 2580.0;
|
|
LEVEL 1 FOR 1160.0;
|
|
LEVEL 0 FOR 400.0;
|
|
LEVEL 1 FOR 120.0;
|
|
LEVEL 0 FOR 5740.0;
|
|
}
|
|
}
|
|
|
|
TRANSITION_LIST("cpuFC[0]")
|
|
{
|
|
NODE
|
|
{
|
|
REPEAT = 1;
|
|
LEVEL 0 FOR 2580.0;
|
|
LEVEL 1 FOR 1160.0;
|
|
LEVEL 0 FOR 400.0;
|
|
LEVEL 1 FOR 120.0;
|
|
LEVEL 0 FOR 5740.0;
|
|
}
|
|
}
|
|
|
|
TRANSITION_LIST("bufACEn")
|
|
{
|
|
NODE
|
|
{
|
|
REPEAT = 1;
|
|
LEVEL X FOR 10000.0;
|
|
}
|
|
}
|
|
|
|
TRANSITION_LIST("bufCCEn")
|
|
{
|
|
NODE
|
|
{
|
|
REPEAT = 1;
|
|
LEVEL X FOR 10000.0;
|
|
}
|
|
}
|
|
|
|
TRANSITION_LIST("bufDDIR")
|
|
{
|
|
NODE
|
|
{
|
|
REPEAT = 1;
|
|
LEVEL X FOR 10000.0;
|
|
}
|
|
}
|
|
|
|
TRANSITION_LIST("bufDHICEn")
|
|
{
|
|
NODE
|
|
{
|
|
REPEAT = 1;
|
|
LEVEL X FOR 10000.0;
|
|
}
|
|
}
|
|
|
|
TRANSITION_LIST("bufDLO1CEn")
|
|
{
|
|
NODE
|
|
{
|
|
REPEAT = 1;
|
|
LEVEL X FOR 10000.0;
|
|
}
|
|
}
|
|
|
|
TRANSITION_LIST("bufDLO2CEn")
|
|
{
|
|
NODE
|
|
{
|
|
REPEAT = 1;
|
|
LEVEL X FOR 10000.0;
|
|
}
|
|
}
|
|
|
|
TRANSITION_LIST("cpuA0")
|
|
{
|
|
NODE
|
|
{
|
|
REPEAT = 1;
|
|
LEVEL 0 FOR 10000.0;
|
|
}
|
|
}
|
|
|
|
TRANSITION_LIST("cpuAHI[3]")
|
|
{
|
|
NODE
|
|
{
|
|
REPEAT = 1;
|
|
LEVEL 0 FOR 900.0;
|
|
LEVEL 1 FOR 1580.0;
|
|
LEVEL 0 FOR 100.0;
|
|
LEVEL 1 FOR 1160.0;
|
|
LEVEL 0 FOR 6260.0;
|
|
}
|
|
}
|
|
|
|
TRANSITION_LIST("cpuAHI[2]")
|
|
{
|
|
NODE
|
|
{
|
|
REPEAT = 1;
|
|
LEVEL 0 FOR 1380.0;
|
|
LEVEL 1 FOR 1100.0;
|
|
LEVEL 0 FOR 100.0;
|
|
LEVEL 1 FOR 1160.0;
|
|
LEVEL 0 FOR 560.0;
|
|
LEVEL 1 FOR 720.0;
|
|
LEVEL 0 FOR 4980.0;
|
|
}
|
|
}
|
|
|
|
TRANSITION_LIST("cpuAHI[1]")
|
|
{
|
|
NODE
|
|
{
|
|
REPEAT = 1;
|
|
LEVEL 0 FOR 1380.0;
|
|
LEVEL 1 FOR 1100.0;
|
|
LEVEL 0 FOR 100.0;
|
|
LEVEL 1 FOR 1160.0;
|
|
LEVEL 0 FOR 6260.0;
|
|
}
|
|
}
|
|
|
|
TRANSITION_LIST("cpuAHI[0]")
|
|
{
|
|
NODE
|
|
{
|
|
REPEAT = 1;
|
|
LEVEL 0 FOR 900.0;
|
|
LEVEL 1 FOR 480.0;
|
|
LEVEL 0 FOR 1200.0;
|
|
LEVEL 1 FOR 1160.0;
|
|
LEVEL 0 FOR 560.0;
|
|
LEVEL 1 FOR 720.0;
|
|
LEVEL 0 FOR 4980.0;
|
|
}
|
|
}
|
|
|
|
TRANSITION_LIST("cpuAMID[6]")
|
|
{
|
|
NODE
|
|
{
|
|
REPEAT = 1;
|
|
LEVEL 0 FOR 2580.0;
|
|
LEVEL 1 FOR 1160.0;
|
|
LEVEL 0 FOR 560.0;
|
|
LEVEL 1 FOR 720.0;
|
|
LEVEL 0 FOR 4980.0;
|
|
}
|
|
}
|
|
|
|
TRANSITION_LIST("cpuAMID[5]")
|
|
{
|
|
NODE
|
|
{
|
|
REPEAT = 1;
|
|
LEVEL 0 FOR 2580.0;
|
|
LEVEL 1 FOR 1160.0;
|
|
LEVEL 0 FOR 560.0;
|
|
LEVEL 1 FOR 720.0;
|
|
LEVEL 0 FOR 4980.0;
|
|
}
|
|
}
|
|
|
|
TRANSITION_LIST("cpuAMID[4]")
|
|
{
|
|
NODE
|
|
{
|
|
REPEAT = 1;
|
|
LEVEL 0 FOR 2580.0;
|
|
LEVEL 1 FOR 1160.0;
|
|
LEVEL 0 FOR 400.0;
|
|
LEVEL 1 FOR 120.0;
|
|
LEVEL 0 FOR 40.0;
|
|
LEVEL 1 FOR 720.0;
|
|
LEVEL 0 FOR 4980.0;
|
|
}
|
|
}
|
|
|
|
TRANSITION_LIST("cpuAMID[3]")
|
|
{
|
|
NODE
|
|
{
|
|
REPEAT = 1;
|
|
LEVEL 0 FOR 2580.0;
|
|
LEVEL 1 FOR 1160.0;
|
|
LEVEL 0 FOR 560.0;
|
|
LEVEL 1 FOR 720.0;
|
|
LEVEL 0 FOR 4980.0;
|
|
}
|
|
}
|
|
|
|
TRANSITION_LIST("cpuAMID[2]")
|
|
{
|
|
NODE
|
|
{
|
|
REPEAT = 1;
|
|
LEVEL 0 FOR 2580.0;
|
|
LEVEL 1 FOR 1160.0;
|
|
LEVEL 0 FOR 560.0;
|
|
LEVEL 1 FOR 720.0;
|
|
LEVEL 0 FOR 4980.0;
|
|
}
|
|
}
|
|
|
|
TRANSITION_LIST("cpuAMID[1]")
|
|
{
|
|
NODE
|
|
{
|
|
REPEAT = 1;
|
|
LEVEL 0 FOR 2580.0;
|
|
LEVEL 1 FOR 1160.0;
|
|
LEVEL 0 FOR 560.0;
|
|
LEVEL 1 FOR 720.0;
|
|
LEVEL 0 FOR 4980.0;
|
|
}
|
|
}
|
|
|
|
TRANSITION_LIST("cpuAMID[0]")
|
|
{
|
|
NODE
|
|
{
|
|
REPEAT = 1;
|
|
LEVEL 0 FOR 2580.0;
|
|
LEVEL 1 FOR 1160.0;
|
|
LEVEL 0 FOR 400.0;
|
|
LEVEL 1 FOR 120.0;
|
|
LEVEL 0 FOR 40.0;
|
|
LEVEL 1 FOR 720.0;
|
|
LEVEL 0 FOR 4980.0;
|
|
}
|
|
}
|
|
|
|
TRANSITION_LIST("cpuASn")
|
|
{
|
|
NODE
|
|
{
|
|
REPEAT = 1;
|
|
LEVEL 1 FOR 360.0;
|
|
LEVEL 0 FOR 480.0;
|
|
LEVEL 1 FOR 80.0;
|
|
LEVEL 0 FOR 440.0;
|
|
LEVEL 1 FOR 40.0;
|
|
LEVEL 0 FOR 1080.0;
|
|
LEVEL 1 FOR 100.0;
|
|
LEVEL 0 FOR 1140.0;
|
|
LEVEL 1 FOR 40.0;
|
|
LEVEL 0 FOR 360.0;
|
|
LEVEL 1 FOR 40.0;
|
|
LEVEL 0 FOR 80.0;
|
|
LEVEL 1 FOR 60.0;
|
|
LEVEL 0 FOR 720.0;
|
|
LEVEL 1 FOR 80.0;
|
|
LEVEL 0 FOR 960.0;
|
|
LEVEL 1 FOR 220.0;
|
|
LEVEL 0 FOR 780.0;
|
|
LEVEL 1 FOR 2940.0;
|
|
}
|
|
}
|
|
|
|
TRANSITION_LIST("cpuAVECn")
|
|
{
|
|
NODE
|
|
{
|
|
REPEAT = 1;
|
|
LEVEL X FOR 10000.0;
|
|
}
|
|
}
|
|
|
|
TRANSITION_LIST("cpuBERRn")
|
|
{
|
|
NODE
|
|
{
|
|
REPEAT = 1;
|
|
LEVEL X FOR 10000.0;
|
|
}
|
|
}
|
|
|
|
TRANSITION_LIST("cpuBGn")
|
|
{
|
|
NODE
|
|
{
|
|
REPEAT = 1;
|
|
LEVEL 1 FOR 10000.0;
|
|
}
|
|
}
|
|
|
|
TRANSITION_LIST("cpuCIINn")
|
|
{
|
|
NODE
|
|
{
|
|
REPEAT = 1;
|
|
LEVEL X FOR 10000.0;
|
|
}
|
|
}
|
|
|
|
TRANSITION_LIST("cpuClock")
|
|
{
|
|
NODE
|
|
{
|
|
REPEAT = 1;
|
|
NODE
|
|
{
|
|
REPEAT = 250;
|
|
LEVEL 0 FOR 20.0;
|
|
LEVEL 1 FOR 20.0;
|
|
}
|
|
}
|
|
}
|
|
|
|
TRANSITION_LIST("cpuDSACK0nz")
|
|
{
|
|
NODE
|
|
{
|
|
REPEAT = 1;
|
|
LEVEL Z FOR 4180.0;
|
|
LEVEL 0 FOR 80.0;
|
|
LEVEL Z FOR 5740.0;
|
|
}
|
|
}
|
|
|
|
TRANSITION_LIST("cpuDSACK1nz")
|
|
{
|
|
NODE
|
|
{
|
|
REPEAT = 1;
|
|
LEVEL Z FOR 4180.0;
|
|
LEVEL 0 FOR 80.0;
|
|
LEVEL Z FOR 5740.0;
|
|
}
|
|
}
|
|
|
|
TRANSITION_LIST("cpuDSn")
|
|
{
|
|
NODE
|
|
{
|
|
REPEAT = 1;
|
|
LEVEL 1 FOR 360.0;
|
|
LEVEL 0 FOR 480.0;
|
|
LEVEL 1 FOR 80.0;
|
|
LEVEL 0 FOR 440.0;
|
|
LEVEL 1 FOR 80.0;
|
|
LEVEL 0 FOR 1040.0;
|
|
LEVEL 1 FOR 100.0;
|
|
LEVEL 0 FOR 1140.0;
|
|
LEVEL 1 FOR 80.0;
|
|
LEVEL 0 FOR 320.0;
|
|
LEVEL 1 FOR 40.0;
|
|
LEVEL 0 FOR 80.0;
|
|
LEVEL 1 FOR 60.0;
|
|
LEVEL 0 FOR 720.0;
|
|
LEVEL 1 FOR 4980.0;
|
|
}
|
|
}
|
|
|
|
TRANSITION_LIST("cpuHALTnz")
|
|
{
|
|
NODE
|
|
{
|
|
REPEAT = 1;
|
|
LEVEL Z FOR 10000.0;
|
|
}
|
|
}
|
|
|
|
TRANSITION_LIST("cpuRESETnz")
|
|
{
|
|
NODE
|
|
{
|
|
REPEAT = 1;
|
|
LEVEL Z FOR 10000.0;
|
|
}
|
|
}
|
|
|
|
TRANSITION_LIST("cpuRnW")
|
|
{
|
|
NODE
|
|
{
|
|
REPEAT = 1;
|
|
LEVEL 1 FOR 1380.0;
|
|
LEVEL 0 FOR 1120.0;
|
|
LEVEL 1 FOR 7500.0;
|
|
}
|
|
}
|
|
|
|
TRANSITION_LIST("cpuSIZE0")
|
|
{
|
|
NODE
|
|
{
|
|
REPEAT = 1;
|
|
LEVEL 0 FOR 1380.0;
|
|
LEVEL 1 FOR 1100.0;
|
|
LEVEL 0 FOR 7520.0;
|
|
}
|
|
}
|
|
|
|
TRANSITION_LIST("cpuSIZE1")
|
|
{
|
|
NODE
|
|
{
|
|
REPEAT = 1;
|
|
LEVEL 0 FOR 900.0;
|
|
LEVEL 1 FOR 480.0;
|
|
LEVEL 0 FOR 8620.0;
|
|
}
|
|
}
|
|
|
|
TRANSITION_LIST("fpuCEn")
|
|
{
|
|
NODE
|
|
{
|
|
REPEAT = 1;
|
|
LEVEL X FOR 10000.0;
|
|
}
|
|
}
|
|
|
|
TRANSITION_LIST("fpuSENSEn")
|
|
{
|
|
NODE
|
|
{
|
|
REPEAT = 1;
|
|
LEVEL 1 FOR 10000.0;
|
|
}
|
|
}
|
|
|
|
TRANSITION_LIST("pdsASnz")
|
|
{
|
|
NODE
|
|
{
|
|
REPEAT = 1;
|
|
LEVEL Z FOR 10000.0;
|
|
}
|
|
}
|
|
|
|
TRANSITION_LIST("pdsBERRn")
|
|
{
|
|
NODE
|
|
{
|
|
REPEAT = 1;
|
|
LEVEL 1 FOR 10000.0;
|
|
}
|
|
}
|
|
|
|
TRANSITION_LIST("pdsBGACKn")
|
|
{
|
|
NODE
|
|
{
|
|
REPEAT = 1;
|
|
LEVEL X FOR 10000.0;
|
|
}
|
|
}
|
|
|
|
TRANSITION_LIST("pdsBGn")
|
|
{
|
|
NODE
|
|
{
|
|
REPEAT = 1;
|
|
LEVEL 1 FOR 240.0;
|
|
LEVEL 0 FOR 9760.0;
|
|
}
|
|
}
|
|
|
|
TRANSITION_LIST("pdsBRn")
|
|
{
|
|
NODE
|
|
{
|
|
REPEAT = 1;
|
|
LEVEL X FOR 10000.0;
|
|
}
|
|
}
|
|
|
|
TRANSITION_LIST("pdsC8M")
|
|
{
|
|
NODE
|
|
{
|
|
REPEAT = 1;
|
|
NODE
|
|
{
|
|
REPEAT = 80;
|
|
LEVEL 0 FOR 62.5;
|
|
LEVEL 1 FOR 62.5;
|
|
}
|
|
}
|
|
}
|
|
|
|
TRANSITION_LIST("pdsClockE")
|
|
{
|
|
NODE
|
|
{
|
|
REPEAT = 1;
|
|
LEVEL X FOR 10000.0;
|
|
}
|
|
}
|
|
|
|
TRANSITION_LIST("pdsDTACKn")
|
|
{
|
|
NODE
|
|
{
|
|
REPEAT = 1;
|
|
LEVEL 1 FOR 740.0;
|
|
LEVEL 0 FOR 120.0;
|
|
LEVEL 1 FOR 420.0;
|
|
LEVEL 0 FOR 100.0;
|
|
LEVEL 1 FOR 2680.0;
|
|
LEVEL 0 FOR 80.0;
|
|
LEVEL 1 FOR 5860.0;
|
|
}
|
|
}
|
|
|
|
TRANSITION_LIST("pdsLDSnz")
|
|
{
|
|
NODE
|
|
{
|
|
REPEAT = 1;
|
|
LEVEL Z FOR 10000.0;
|
|
}
|
|
}
|
|
|
|
TRANSITION_LIST("pdsRESETn")
|
|
{
|
|
NODE
|
|
{
|
|
REPEAT = 1;
|
|
LEVEL 1 FOR 80.0;
|
|
LEVEL 0 FOR 160.0;
|
|
LEVEL 1 FOR 9760.0;
|
|
}
|
|
}
|
|
|
|
TRANSITION_LIST("pdsUDSnz")
|
|
{
|
|
NODE
|
|
{
|
|
REPEAT = 1;
|
|
LEVEL Z FOR 10000.0;
|
|
}
|
|
}
|
|
|
|
TRANSITION_LIST("pdsVMAnz")
|
|
{
|
|
NODE
|
|
{
|
|
REPEAT = 1;
|
|
LEVEL Z FOR 10000.0;
|
|
}
|
|
}
|
|
|
|
TRANSITION_LIST("pdsVPAn")
|
|
{
|
|
NODE
|
|
{
|
|
REPEAT = 1;
|
|
LEVEL 1 FOR 1440.0;
|
|
LEVEL 0 FOR 1060.0;
|
|
LEVEL 1 FOR 100.0;
|
|
LEVEL 0 FOR 1140.0;
|
|
LEVEL 1 FOR 6260.0;
|
|
}
|
|
}
|
|
|
|
TRANSITION_LIST("pdsPMCYCn")
|
|
{
|
|
NODE
|
|
{
|
|
REPEAT = 1;
|
|
LEVEL 0 FOR 5060.0;
|
|
LEVEL 1 FOR 560.0;
|
|
LEVEL 0 FOR 440.0;
|
|
LEVEL 1 FOR 60.0;
|
|
LEVEL 0 FOR 440.0;
|
|
LEVEL 1 FOR 60.0;
|
|
LEVEL 0 FOR 440.0;
|
|
LEVEL 1 FOR 60.0;
|
|
LEVEL 0 FOR 2880.0;
|
|
}
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "cpuClock";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Binary;
|
|
TREE_INDEX = 0;
|
|
TREE_LEVEL = 0;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "pdsC8M";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Binary;
|
|
TREE_INDEX = 1;
|
|
TREE_LEVEL = 0;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "pdsClockE";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Binary;
|
|
TREE_INDEX = 2;
|
|
TREE_LEVEL = 0;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "pdsPMCYCn";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Binary;
|
|
TREE_INDEX = 3;
|
|
TREE_LEVEL = 0;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "cpuASn";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Binary;
|
|
TREE_INDEX = 4;
|
|
TREE_LEVEL = 0;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "cpuDSn";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Binary;
|
|
TREE_INDEX = 5;
|
|
TREE_LEVEL = 0;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "pdsDTACKn";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Binary;
|
|
TREE_INDEX = 6;
|
|
TREE_LEVEL = 0;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "pdsVPAn";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Binary;
|
|
TREE_INDEX = 7;
|
|
TREE_LEVEL = 0;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "cpuRnW";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Binary;
|
|
TREE_INDEX = 8;
|
|
TREE_LEVEL = 0;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "cpuA0";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Binary;
|
|
TREE_INDEX = 9;
|
|
TREE_LEVEL = 0;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "cpuSIZE0";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Binary;
|
|
TREE_INDEX = 10;
|
|
TREE_LEVEL = 0;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "cpuSIZE1";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Binary;
|
|
TREE_INDEX = 11;
|
|
TREE_LEVEL = 0;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "cpuFC";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Binary;
|
|
TREE_INDEX = 12;
|
|
TREE_LEVEL = 0;
|
|
CHILDREN = 13, 14, 15;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "cpuFC[2]";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Binary;
|
|
TREE_INDEX = 13;
|
|
TREE_LEVEL = 1;
|
|
PARENT = 12;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "cpuFC[1]";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Binary;
|
|
TREE_INDEX = 14;
|
|
TREE_LEVEL = 1;
|
|
PARENT = 12;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "cpuFC[0]";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Binary;
|
|
TREE_INDEX = 15;
|
|
TREE_LEVEL = 1;
|
|
PARENT = 12;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "cpuAHI";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Hexadecimal;
|
|
TREE_INDEX = 16;
|
|
TREE_LEVEL = 0;
|
|
CHILDREN = 17, 18, 19, 20;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "cpuAHI[3]";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Hexadecimal;
|
|
TREE_INDEX = 17;
|
|
TREE_LEVEL = 1;
|
|
PARENT = 16;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "cpuAHI[2]";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Hexadecimal;
|
|
TREE_INDEX = 18;
|
|
TREE_LEVEL = 1;
|
|
PARENT = 16;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "cpuAHI[1]";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Hexadecimal;
|
|
TREE_INDEX = 19;
|
|
TREE_LEVEL = 1;
|
|
PARENT = 16;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "cpuAHI[0]";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Hexadecimal;
|
|
TREE_INDEX = 20;
|
|
TREE_LEVEL = 1;
|
|
PARENT = 16;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "cpuAMID";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Hexadecimal;
|
|
TREE_INDEX = 21;
|
|
TREE_LEVEL = 0;
|
|
CHILDREN = 22, 23, 24, 25, 26, 27, 28;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "cpuAMID[6]";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Hexadecimal;
|
|
TREE_INDEX = 22;
|
|
TREE_LEVEL = 1;
|
|
PARENT = 21;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "cpuAMID[5]";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Hexadecimal;
|
|
TREE_INDEX = 23;
|
|
TREE_LEVEL = 1;
|
|
PARENT = 21;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "cpuAMID[4]";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Hexadecimal;
|
|
TREE_INDEX = 24;
|
|
TREE_LEVEL = 1;
|
|
PARENT = 21;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "cpuAMID[3]";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Hexadecimal;
|
|
TREE_INDEX = 25;
|
|
TREE_LEVEL = 1;
|
|
PARENT = 21;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "cpuAMID[2]";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Hexadecimal;
|
|
TREE_INDEX = 26;
|
|
TREE_LEVEL = 1;
|
|
PARENT = 21;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "cpuAMID[1]";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Hexadecimal;
|
|
TREE_INDEX = 27;
|
|
TREE_LEVEL = 1;
|
|
PARENT = 21;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "cpuAMID[0]";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Hexadecimal;
|
|
TREE_INDEX = 28;
|
|
TREE_LEVEL = 1;
|
|
PARENT = 21;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "cpuBGn";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Binary;
|
|
TREE_INDEX = 29;
|
|
TREE_LEVEL = 0;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "cpuDSACK0nz";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Binary;
|
|
TREE_INDEX = 30;
|
|
TREE_LEVEL = 0;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "cpuDSACK1nz";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Binary;
|
|
TREE_INDEX = 31;
|
|
TREE_LEVEL = 0;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "cpuHALTnz";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Binary;
|
|
TREE_INDEX = 32;
|
|
TREE_LEVEL = 0;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "cpuRESETnz";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Binary;
|
|
TREE_INDEX = 33;
|
|
TREE_LEVEL = 0;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "fpuCEn";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Binary;
|
|
TREE_INDEX = 34;
|
|
TREE_LEVEL = 0;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "fpuSENSEn";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Binary;
|
|
TREE_INDEX = 35;
|
|
TREE_LEVEL = 0;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "pdsASnz";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Binary;
|
|
TREE_INDEX = 36;
|
|
TREE_LEVEL = 0;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "pdsBERRn";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Binary;
|
|
TREE_INDEX = 37;
|
|
TREE_LEVEL = 0;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "pdsBGACKn";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Binary;
|
|
TREE_INDEX = 38;
|
|
TREE_LEVEL = 0;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "pdsBGn";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Binary;
|
|
TREE_INDEX = 39;
|
|
TREE_LEVEL = 0;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "pdsBRn";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Binary;
|
|
TREE_INDEX = 40;
|
|
TREE_LEVEL = 0;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "pdsUDSnz";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Binary;
|
|
TREE_INDEX = 41;
|
|
TREE_LEVEL = 0;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "pdsLDSnz";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Binary;
|
|
TREE_INDEX = 42;
|
|
TREE_LEVEL = 0;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "pdsVMAnz";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Binary;
|
|
TREE_INDEX = 43;
|
|
TREE_LEVEL = 0;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "pdsRESETn";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Binary;
|
|
TREE_INDEX = 44;
|
|
TREE_LEVEL = 0;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "cpuAVECn";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Binary;
|
|
TREE_INDEX = 45;
|
|
TREE_LEVEL = 0;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "cpuBERRn";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Binary;
|
|
TREE_INDEX = 46;
|
|
TREE_LEVEL = 0;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "bufACEn";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Binary;
|
|
TREE_INDEX = 47;
|
|
TREE_LEVEL = 0;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "bufCCEn";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Binary;
|
|
TREE_INDEX = 48;
|
|
TREE_LEVEL = 0;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "bufDDIR";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Binary;
|
|
TREE_INDEX = 49;
|
|
TREE_LEVEL = 0;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "bufDHICEn";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Binary;
|
|
TREE_INDEX = 50;
|
|
TREE_LEVEL = 0;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "bufDLO1CEn";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Binary;
|
|
TREE_INDEX = 51;
|
|
TREE_LEVEL = 0;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "bufDLO2CEn";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Binary;
|
|
TREE_INDEX = 52;
|
|
TREE_LEVEL = 0;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "cpuCIINn";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Binary;
|
|
TREE_INDEX = 53;
|
|
TREE_LEVEL = 0;
|
|
}
|
|
|
|
TIME_BAR
|
|
{
|
|
TIME = 5060000;
|
|
MASTER = TRUE;
|
|
}
|
|
;
|