368 lines
12 KiB
Systemverilog
368 lines
12 KiB
Systemverilog
/******************************************************************************
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* SE-Exp30 MacSE Accelerator
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* techav
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* 2021-03-20
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* Processor Accelerator System Translation Engine
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******************************************************************************
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* Handles all logic to translate the Mac SE 68000 PDS bus to the 68030 bus as
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* well as additional logic for interfacing with the 68882 FPU.
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*****************************************************************************/
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module paste (
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inout wire ncpuReset, // 68030 reset signal (tristate)
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inout wire ncpuHalt, // 68030 halt signal (tristate)
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input wire ncpuDS, // 68030 data strobe signal
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output wire ncpuDsack0, // 68030 DS Ack 0 signal
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output wire ncpuDsack1, // 68030 DS Ack 1 signal
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input wire cpuSize0, // 68030 Size 0 signal
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input wire cpuSize1, // 68030 Size 1 signal
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input wire cpuA0, // 68030 Address 0 signal
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input logic [23:20] cpuAddrHi, // 68030 Address Hi (16MB) signals
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input logic [19:13] cpuAddrMid, // 68030 Address Mid (FPU decode) signals
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output wire ncpuAvec, // 68030 Autovector request signal
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input logic [2:0] cpuFC, // 68030 Function Code signals
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input wire cpuClock, // 68030 Primary CPU Clock signal
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input wire cpuRnW, // 68030 Read/Write signal
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input wire ncpuBG, // 68030 Bus Grant signal
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inout wire ncpuBerr, // 68030 Bus Error signal
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inout wire ncpuCiin, // 68030 Cache Inhibit signal
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input wire npdsReset, // PDS Reset signal
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inout wire npdsLds, // PDS Lower Data Strobe signal
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inout wire npdsUds, // PDS Upper Data Strobe signal
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input wire npdsDtack, // PDS Data Xfer Ack signal
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input wire npdsBg, // PDS Bus Grant signal
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output wire npdsBGack, // PDS Bus Grant Ack signal
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output wire npdsBr, // PDS Bus Request signal
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inout wire npdsVma, // PDS Valid Memory Addr signal
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input wire npdsVpa, // PDS Valid Peripheral Addr signal
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input wire pdsC8m, // PDS 8MHz System Clock signal
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input wire pdsClockE, // PDS 800kHz 6800 bus E clock
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output wire nbufDhiEn, // Data buffer CPU[31:24] <=> PDS[15:8]
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output wire nbufDlo1En, // Data buffer CPU[23:16] <=> PDS[7:0]
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output wire nbufDlo2En, // Data buffer CPU[31:24] <=> PDS[7:0]
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output wire bufDDir, // Data buffer direction
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output wire nbufCEn, // Control signal buffer enable
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output wire nbufAEn, // Address buffer enable
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input wire nfpuSense, // FPU Presence Detect signal
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output wire nfpuCe // FPU Chip Select signal
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);
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// define state machine states
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parameter
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S0 = 2'h0,
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S1 = 2'h1,
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S2 = 2'h2;
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// state machine state variables
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logic [1:0] vmagenState; // state machine for npdsVma generator
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logic [1:0] dsack68genState; // state machine for nDsack68 generator
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logic [1:0] dsackSEgenState; // state machine for nDsackSE generator
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logic [1:0] resetgenState; // state machine for nCpuReset generator
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logic [3:0] vmagenCount; // state counter for npdsVma generator
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// intermediate signals
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wire nDsack68; // 6800 bus termination signal
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wire nDsackSE; // SE bus termination signal
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wire nUD; // SE upper data byte select
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wire nLD; // SE lower data byte select
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// state machine for npdsVma generation
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always @(posedge pdsC8m or negedge npdsReset) begin
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// sync state machine clocked by 8MHz system clock with async reset
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if(npdsReset == 1'b0) begin
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vmagenState <= S0;
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vmagenCount <= 4'h0;
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end else begin
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case(vmagenState)
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S0 : begin
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// wait for 6800 bus cycle to begin
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// marked by assertion of npdsVpa and pdsClockE
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if (npdsVpa == 1'b0 && pdsClockE == 1'b1) begin
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vmagenState <= S1;
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end else begin
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vmagenState <= S0;
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end
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vmagenCount <= 4'h0;
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end
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S1 : begin
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// wait for deassertion of pdsClockE
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if (pdsClockE == 1'b0) begin
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vmagenState <= S2;
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end else begin
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vmagenState <= S1;
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end
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vmagenCount <= 4'h0;
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end
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S2 : begin
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// increment vmagenCount until == 4'hA
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if (vmagenCount == 4'hA) begin
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vmagenState <= S0;
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vmagenCount <= 4'h0;
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end else begin
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vmagenState <= S2;
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vmagenCount <= vmagenCount + 1'b1;
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end
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end
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default: begin
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// how did we end up here? reset to S0
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vmagenState <= S0;
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vmagenCount <= 4'h0;
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end
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endcase
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end
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end
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// state machine for nDsack68 generation
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always @(posedge cpuClock or negedge npdsReset) begin
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// sync state machine clocked by primary CPU clock with async reset
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if(npdsReset == 1'b0) begin
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dsack68genState <= S0;
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end else begin
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case(dsack68genState)
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S0 : begin
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// wait for vmagenCount == 4'hA
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if (vmagenCount == 4'hA) begin
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dsack68genState <= S1;
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end else begin
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dsack68genState <= S0;
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end
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end
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S1 : begin
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// immediately progress to S2
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dsack68genState <= S2;
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end
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S2 : begin
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// wait for vmagenCount to reset to 0
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if (vmagenCount == 4'h0) begin
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dsack68genState <= S0;
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end else begin
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dsack68genState <= S2;
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end
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end
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default: begin
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// shouldn't be here. reset to S0
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dsack68genState <= S0;
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end
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endcase
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end
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end
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// state machine for nDsackSE generation
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always @(posedge cpuClock or negedge npdsReset) begin
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// sync state machine clocked by primary CPU clock with async reset
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if(npdsReset == 1'b0) begin
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dsackSEgenState <= S0;
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end else begin
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case(dsackSEgenState)
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S0 : begin
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// wait for assertion of npdsDtack
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if(npdsDtack == 1'b0) begin
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dsackSEgenState <= S1;
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end else begin
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dsackSEgenState <= S0;
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end
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end
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S1 : begin
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// immediately proceed to S3
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dsackSEgenState <= S2;
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end
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S2 : begin
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// wait for deassertion of npdsDtack
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if (npdsDtack == 1'b1) begin
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dsackSEgenState <= S0;
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end else begin
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dsackSEgenState <= S2;
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end
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end
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default: begin
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// shouldn't be here. reset to S0
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dsackSEgenState <= S0;
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end
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endcase
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end
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end
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// state machine for power on reset
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always @(posedge cpuClock or negedge npdsReset) begin
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// sync state machine clocked by primary CPU clock with async reset
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if(npdsReset == 1'b0) begin
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resetgenState <= S0;
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end else begin
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case(resetgenState)
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S0 : begin
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// wait for deassertion of npdsReset
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if(npdsReset == 1'b1) begin
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resetgenState <= S1;
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end else begin
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// shouldn't actually end up here
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resetgenState <= S0;
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end
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end
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S1 : begin
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// wait for Bus Grant from SE
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if(npdsBg == 1'b0) begin
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resetgenState <= S2;
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end else begin
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resetgenState <= S1;
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end
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end
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S2 : begin
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// this is actually our idle state.
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// stay here until the system resets again.
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if(npdsReset == 1'b1) begin
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resetgenState <= S2;
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end else begin
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resetgenState <= S0;
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end
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end
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default: begin
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// really shouldn't be here
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resetgenState <= S0;
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end
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endcase
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end
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end
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// and finally, our combinatorial logic
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always_comb begin
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// DSACK intermediary signals
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if(dsack68genState == S1) begin
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nDsack68 <= 1'b0;
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end else begin
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nDsack68 <= 1'b1;
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end
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if(dsackSEgenState == S1) begin
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nDsackSE <= 1'b0;
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end else begin
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nDsackSE <= 1'b1;
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end
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// Upper/Lower data byte intermediary signals
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if(~cpuA0 || cpuRnW) begin
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nUD <= 1'b0;
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end else begin
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nUD <= 1'b1;
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end
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if(cpuA0 || ~cpuSize0 || cpuSize1 || cpuRnW) begin
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nLD <= 1'b0;
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end else begin
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nLD <= 1'b1;
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end
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// Upper/Lower data strobes
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if(~ncpuDS || ~nUD) begin
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npdsUds <= 1'b0;
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end else begin
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npdsUds <= 1'bZ;
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end
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if(~ncpuDS || ~nLD) begin
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npdsLds <= 1'b0;
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end else begin
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npdsLds <= 1'bZ;
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end
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// buffer enable signals
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if(ncpuBG == 1'b1) begin
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if(~nUD || ~npdsBg) begin
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nbufDhiEn <= 1'b0;
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end else begin
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nbufDhiEn <= 1'b1;
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end
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if(~nLD || nUD || ~npdsBg) begin
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nbufDlo2En <= 1'b0;
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end else begin
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nbufDlo2En <= 1'b1;
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end
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if(~nLD || ~nUD || ~npdsBg) begin
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nbufDlo1En <= 1'b0;
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end else begin
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nbufDlo1En <= 1'b1;
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end
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if(npdsBg <= 1'b0) begin
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nbufAEn <= 1'b0;
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nbufCEn <= 1'b0;
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end else begin
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nbufAEn <= 1'b1;
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nbufCEn <= 1'b1;
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end
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end else begin
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nbufDhiEn <= 1'b1;
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nbufDlo2En <= 1'b1;
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nbufDlo1En <= 1'b1;
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nbufAEn <= 1'b1;
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nbufCEn <= 1'b1;
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end
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// data buffer direction
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bufDDir <= cpuRnW;
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// autovector request
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if(cpuFC == 3'h7 && nDsack68 == 1'b0) begin
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ncpuAvec <= 1'b0;
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end else begin
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ncpuAvec <= 1'b1;
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end
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// VMA signal
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if(vmagenCount >= 4'h3) begin
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npdsVma <= 1'b0;
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end else begin
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npdsVma <= 1'bz;
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end
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// DS Ack signals
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if((nDsack68 == 1'b0 || (nDsackSE == 1'b0 && cpuAddrHi < 4'h5)) && cpuFC < 3'h7) begin
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ncpuDsack0 <= 1'b0;
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end else begin
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ncpuDsack0 <= 1'b1;
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end
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if(nDsackSE == 1'b0 && cpuAddrHi >= 4'h5 && cpuFC < 3'h7) begin
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ncpuDsack1 <= 1'b0;
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end else begin
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ncpuDsack1 <= 1'b1;
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end
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// CPU reset signals
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if(resetgenState == S2) begin
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ncpuReset <= 1'b0;
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ncpuHalt <= 1'b0;
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end else begin
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ncpuReset <= 1'bz;
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ncpuHalt <= 1'bz;
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end
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// bus request & grant
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if(resetgenState == S0) begin
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npdsBr <= 1'bz;
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end else begin
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npdsBr <= 1'b0;
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end
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if(resetgenState == S2) begin
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npdsBGack <= 1'b0;
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end else begin
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npdsBGack <= 1'bz;
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end
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// FPU chip enable & presence detect
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if(cpuAddrMid == 7'h11 && cpuFC == 3'h7) begin
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nfpuCe <= 1'b0;
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if(nfpuSense == 1'b1) begin
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// pulled high means FPU missing. assert bus error
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ncpuBerr <= 1'b0;
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end else begin
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ncpuBerr <= 1'bz;
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end
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end else begin
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nfpuCe <= 1'b1;
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ncpuBerr <= 1'bz;
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end
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// CPU cache inhibit
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if(cpuAddrHi >= 4'h6) begin
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ncpuCiin <= 1'b0;
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end else begin
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ncpuCiin <= 1'bz;
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end
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end
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endmodule |