Macintosh-HW
/
SE-VGA
mirror of https://github.com/techav-homebrew/SE-VGA.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

CPU Cycle Improvements 1

This commit is contained in:
techav 2021-04-18 10:28:04 -05:00
parent 7a519feab3
commit 3b00823d6c
2 changed files with 79 additions and 49 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

12
cpusnoop.sv
View File

@ -32,6 +32,7 @@ module cpusnoop (
logic [7:0] dataCacheHi; // store data for cpu writes to high byte
wire cpuBufSel; // is CPU accessing frame buffer?
logic [2:0] cycleState; // state machine state
reg cpuCycleEnded; // mark cpu has ended its cycle
// define state machine states
parameter
@ -66,6 +67,14 @@ module cpusnoop (
cpuBufSel <= 1'b0;
end
end
// keep an eye out for cpu ending its cycle
always @(negedge pixClock or negedge nReset) begin
if(!nReset) cpuCycleEnded <= 0;
else if(cycleState == S2) cpuCycleEnded <= 0;
else if(ncpuUDS == 1 && ncpuLDS == 1 && (cycleState == S3 || cycleState == S4 || cycleState == S5)) cpuCycleEnded <= 1;
else cpuCycleEnded <= cpuCycleEnded;
end
// CPU Write to VRAM state machine
always @(negedge pixClock or negedge nReset) begin
@ -156,7 +165,8 @@ module cpusnoop (
end
S5 : begin
// wait for CPU to negate both ncpuUDS and ncpuLDS
if(ncpuUDS == 1 && ncpuLDS == 1) begin
//if(ncpuUDS == 1 && ncpuLDS == 1) begin
if(cpuCycleEnded == 1) begin
cycleState <= S0;
end else begin
cycleState <= S5;

116
sevga.vwf
View File

@ -1202,7 +1202,9 @@ TRANSITION_LIST("cpuAddr[1]")
NODE
{
REPEAT = 1;
LEVEL 0 FOR 33000.0;
LEVEL 0 FOR 1280.0;
LEVEL 1 FOR 420.0;
LEVEL 0 FOR 31300.0;
}
}
@ -1212,8 +1214,8 @@ TRANSITION_LIST("cpuAddr[2]")
{
REPEAT = 1;
LEVEL 0 FOR 960.0;
LEVEL 1 FOR 320.0;
LEVEL 0 FOR 31720.0;
LEVEL 1 FOR 740.0;
LEVEL 0 FOR 31300.0;
}
}
@ -1243,8 +1245,8 @@ TRANSITION_LIST("cpuAddr[5]")
LEVEL 0 FOR 600.0;
LEVEL 1 FOR 320.0;
LEVEL 0 FOR 40.0;
LEVEL 1 FOR 320.0;
LEVEL 0 FOR 31720.0;
LEVEL 1 FOR 740.0;
LEVEL 0 FOR 31300.0;
}
}
@ -1274,8 +1276,8 @@ TRANSITION_LIST("cpuAddr[8]")
LEVEL 0 FOR 600.0;
LEVEL 1 FOR 320.0;
LEVEL 0 FOR 40.0;
LEVEL 1 FOR 320.0;
LEVEL 0 FOR 31720.0;
LEVEL 1 FOR 740.0;
LEVEL 0 FOR 31300.0;
}
}
@ -1287,8 +1289,8 @@ TRANSITION_LIST("cpuAddr[9]")
LEVEL 0 FOR 600.0;
LEVEL 1 FOR 320.0;
LEVEL 0 FOR 40.0;
LEVEL 1 FOR 320.0;
LEVEL 0 FOR 31720.0;
LEVEL 1 FOR 740.0;
LEVEL 0 FOR 31300.0;
}
}
@ -1300,8 +1302,8 @@ TRANSITION_LIST("cpuAddr[10]")
LEVEL 0 FOR 600.0;
LEVEL 1 FOR 320.0;
LEVEL 0 FOR 40.0;
LEVEL 1 FOR 320.0;
LEVEL 0 FOR 31720.0;
LEVEL 1 FOR 740.0;
LEVEL 0 FOR 31300.0;
}
}
@ -1331,8 +1333,8 @@ TRANSITION_LIST("cpuAddr[13]")
LEVEL 0 FOR 600.0;
LEVEL 1 FOR 320.0;
LEVEL 0 FOR 40.0;
LEVEL 1 FOR 320.0;
LEVEL 0 FOR 31720.0;
LEVEL 1 FOR 740.0;
LEVEL 0 FOR 31300.0;
}
}
@ -1353,8 +1355,8 @@ TRANSITION_LIST("cpuAddr[15]")
LEVEL 0 FOR 600.0;
LEVEL 1 FOR 320.0;
LEVEL 0 FOR 40.0;
LEVEL 1 FOR 320.0;
LEVEL 0 FOR 31720.0;
LEVEL 1 FOR 740.0;
LEVEL 0 FOR 31300.0;
}
}
@ -1366,8 +1368,8 @@ TRANSITION_LIST("cpuAddr[16]")
LEVEL 0 FOR 600.0;
LEVEL 1 FOR 320.0;
LEVEL 0 FOR 40.0;
LEVEL 1 FOR 320.0;
LEVEL 0 FOR 31720.0;
LEVEL 1 FOR 740.0;
LEVEL 0 FOR 31300.0;
}
}
@ -1379,8 +1381,8 @@ TRANSITION_LIST("cpuAddr[17]")
LEVEL 0 FOR 600.0;
LEVEL 1 FOR 320.0;
LEVEL 0 FOR 40.0;
LEVEL 1 FOR 320.0;
LEVEL 0 FOR 31720.0;
LEVEL 1 FOR 740.0;
LEVEL 0 FOR 31300.0;
}
}
@ -1392,8 +1394,8 @@ TRANSITION_LIST("cpuAddr[18]")
LEVEL 0 FOR 600.0;
LEVEL 1 FOR 320.0;
LEVEL 0 FOR 40.0;
LEVEL 1 FOR 320.0;
LEVEL 0 FOR 31720.0;
LEVEL 1 FOR 740.0;
LEVEL 0 FOR 31300.0;
}
}
@ -1405,8 +1407,8 @@ TRANSITION_LIST("cpuAddr[19]")
LEVEL 0 FOR 600.0;
LEVEL 1 FOR 320.0;
LEVEL 0 FOR 40.0;
LEVEL 1 FOR 320.0;
LEVEL 0 FOR 31720.0;
LEVEL 1 FOR 740.0;
LEVEL 0 FOR 31300.0;
}
}
@ -1418,8 +1420,8 @@ TRANSITION_LIST("cpuAddr[20]")
LEVEL 0 FOR 600.0;
LEVEL 1 FOR 320.0;
LEVEL 0 FOR 40.0;
LEVEL 1 FOR 320.0;
LEVEL 0 FOR 31720.0;
LEVEL 1 FOR 740.0;
LEVEL 0 FOR 31300.0;
}
}
@ -1431,8 +1433,8 @@ TRANSITION_LIST("cpuAddr[21]")
LEVEL 0 FOR 600.0;
LEVEL 1 FOR 320.0;
LEVEL 0 FOR 40.0;
LEVEL 1 FOR 320.0;
LEVEL 0 FOR 31720.0;
LEVEL 1 FOR 740.0;
LEVEL 0 FOR 31300.0;
}
}
@ -1487,8 +1489,8 @@ TRANSITION_LIST("cpuData[14]")
{
REPEAT = 1;
LEVEL 0 FOR 960.0;
LEVEL 1 FOR 320.0;
LEVEL 0 FOR 31720.0;
LEVEL 1 FOR 740.0;
LEVEL 0 FOR 31300.0;
}
}
@ -1499,7 +1501,9 @@ TRANSITION_LIST("cpuData[13]")
REPEAT = 1;
LEVEL 0 FOR 600.0;
LEVEL 1 FOR 320.0;
LEVEL 0 FOR 32080.0;
LEVEL 0 FOR 360.0;
LEVEL 1 FOR 420.0;
LEVEL 0 FOR 31300.0;
}
}
@ -1508,7 +1512,9 @@ TRANSITION_LIST("cpuData[12]")
NODE
{
REPEAT = 1;
LEVEL 0 FOR 33000.0;
LEVEL 0 FOR 1280.0;
LEVEL 1 FOR 420.0;
LEVEL 0 FOR 31300.0;
}
}
@ -1517,7 +1523,9 @@ TRANSITION_LIST("cpuData[11]")
NODE
{
REPEAT = 1;
LEVEL 0 FOR 33000.0;
LEVEL 0 FOR 1280.0;
LEVEL 1 FOR 420.0;
LEVEL 0 FOR 31300.0;
}
}
@ -1528,7 +1536,9 @@ TRANSITION_LIST("cpuData[10]")
REPEAT = 1;
LEVEL 0 FOR 600.0;
LEVEL 1 FOR 320.0;
LEVEL 0 FOR 32080.0;
LEVEL 0 FOR 360.0;
LEVEL 1 FOR 420.0;
LEVEL 0 FOR 31300.0;
}
}
@ -1538,8 +1548,8 @@ TRANSITION_LIST("cpuData[9]")
{
REPEAT = 1;
LEVEL 0 FOR 960.0;
LEVEL 1 FOR 320.0;
LEVEL 0 FOR 31720.0;
LEVEL 1 FOR 740.0;
LEVEL 0 FOR 31300.0;
}
}
@ -1576,7 +1586,9 @@ TRANSITION_LIST("cpuData[6]")
REPEAT = 1;
LEVEL 0 FOR 600.0;
LEVEL 1 FOR 320.0;
LEVEL 0 FOR 32080.0;
LEVEL 0 FOR 360.0;
LEVEL 1 FOR 420.0;
LEVEL 0 FOR 31300.0;
}
}
@ -1597,8 +1609,8 @@ TRANSITION_LIST("cpuData[4]")
{
REPEAT = 1;
LEVEL 0 FOR 960.0;
LEVEL 1 FOR 320.0;
LEVEL 0 FOR 31720.0;
LEVEL 1 FOR 740.0;
LEVEL 0 FOR 31300.0;
}
}
@ -1607,7 +1619,9 @@ TRANSITION_LIST("cpuData[3]")
NODE
{
REPEAT = 1;
LEVEL 0 FOR 33000.0;
LEVEL 0 FOR 1280.0;
LEVEL 1 FOR 420.0;
LEVEL 0 FOR 31300.0;
}
}
@ -1632,8 +1646,8 @@ TRANSITION_LIST("cpuData[1]")
LEVEL 0 FOR 600.0;
LEVEL 1 FOR 320.0;
LEVEL 0 FOR 40.0;
LEVEL 1 FOR 320.0;
LEVEL 0 FOR 31720.0;
LEVEL 1 FOR 740.0;
LEVEL 0 FOR 31300.0;
}
}
@ -1657,7 +1671,9 @@ TRANSITION_LIST("cpuRnW")
LEVEL 0 FOR 320.0;
LEVEL 1 FOR 40.0;
LEVEL 0 FOR 320.0;
LEVEL 1 FOR 31720.0;
LEVEL 1 FOR 20.0;
LEVEL 0 FOR 400.0;
LEVEL 1 FOR 31300.0;
}
}
@ -1679,9 +1695,11 @@ TRANSITION_LIST("ncpuAS")
REPEAT = 1;
LEVEL 1 FOR 610.0;
LEVEL 0 FOR 310.0;
LEVEL 1 FOR 60.0;
LEVEL 0 FOR 300.0;
LEVEL 1 FOR 31720.0;
LEVEL 1 FOR 100.0;
LEVEL 0 FOR 260.0;
LEVEL 1 FOR 40.0;
LEVEL 0 FOR 120.0;
LEVEL 1 FOR 31560.0;
}
}
@ -1692,8 +1710,8 @@ TRANSITION_LIST("ncpuLDS")
REPEAT = 1;
LEVEL 1 FOR 760.0;
LEVEL 0 FOR 160.0;
LEVEL 1 FOR 200.0;
LEVEL 0 FOR 160.0;
LEVEL 1 FOR 240.0;
LEVEL 0 FOR 120.0;
LEVEL 1 FOR 31720.0;
}
}
@ -1705,7 +1723,9 @@ TRANSITION_LIST("ncpuUDS")
REPEAT = 1;
LEVEL 1 FOR 760.0;
LEVEL 0 FOR 160.0;
LEVEL 1 FOR 32080.0;
LEVEL 1 FOR 440.0;
LEVEL 0 FOR 80.0;
LEVEL 1 FOR 31560.0;
}
}