From 51da9252610f6efe9d120e8a24676a78cb8094f8 Mon Sep 17 00:00:00 2001
From: techav <76832805+techav-homebrew@users.noreply.github.com>
Date: Sun, 25 Jul 2021 18:11:49 -0500
Subject: [PATCH 01/14] XGA Board Rev

Rework of board to add support for pixel-doubled image on XGA resolution frame, and installation in Plus or 512k
---
 Gerbers/copper_bottom.gbr      | 44262 +++++++++++++++--------
 Gerbers/copper_top.gbr         | 59598 +++++++++++++++++++++----------
 Gerbers/drill_1_16.xln         |  1217 +-
 Gerbers/profile.gbr            |   186 +-
 Gerbers/silkscreen_bottom.gbr  | 12159 +++++--
 Gerbers/silkscreen_top.gbr     | 42380 ++++++++++++----------
 Gerbers/soldermask_bottom.gbr  |   582 +-
 Gerbers/soldermask_top.gbr     |  1469 +-
 Gerbers/solderpaste_bottom.gbr |     8 +
 Gerbers/solderpaste_top.gbr    |   901 +-
 10 files changed, 107503 insertions(+), 55259 deletions(-)

diff --git a/Gerbers/copper_bottom.gbr b/Gerbers/copper_bottom.gbr
index d04d652..a8ec71e 100644
--- a/Gerbers/copper_bottom.gbr
+++ b/Gerbers/copper_bottom.gbr
@@ -9,15023 +9,30473 @@ G75*
 5,1,8,0,0,1.08239X$1,22.5*%
 G01*
 %ADD10C,1.320800*%
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+%ADD11C,1.422400*%
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+%ADD13C,0.908000*%
+%ADD14R,1.600200X1.168400*%
+%ADD15C,0.406400*%
+%ADD16C,1.508000*%
+%ADD17C,0.604800*%
+%ADD18C,0.812800*%
+%ADD19C,0.254000*%
+%ADD20C,1.016000*%
+%ADD21C,0.127000*%
 
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+X762249Y604519D01*
+X762111Y604502D01*
+X761972Y604489D01*
+X761953Y604482D01*
+X761933Y604479D01*
+X761804Y604428D01*
+X761673Y604381D01*
+X761656Y604370D01*
+X761637Y604362D01*
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+X761380Y604176D01*
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+X761093Y602730D01*
+X761100Y602711D01*
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+X761296Y597331D01*
+X761400Y597240D01*
+X761501Y597144D01*
+X761519Y597134D01*
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+X762148Y596907D01*
+X762249Y596901D01*
+X802332Y596901D01*
+X802430Y596913D01*
 G37*
-%LPD*%
 %LPC*%
 G36*
-X339428Y44957D02*
-X339428Y44957D01*
-X334517Y49868D01*
-X334517Y56812D01*
-X339428Y61723D01*
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-X351283Y49868D01*
-X346372Y44957D01*
-X339428Y44957D01*
+X87131Y613409D02*
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+X97791Y620531D01*
+X96437Y617264D01*
+X93936Y614763D01*
+X90669Y613409D01*
+X87131Y613409D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X237828Y44957D02*
-X237828Y44957D01*
-X232917Y49868D01*
-X232917Y56812D01*
-X237828Y61723D01*
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-X244772Y44957D01*
-X237828Y44957D01*
+X87131Y537209D02*
+X87131Y537209D01*
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+X97791Y544331D01*
+X96437Y541064D01*
+X93936Y538563D01*
+X90669Y537209D01*
+X87131Y537209D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X415628Y44957D02*
-X415628Y44957D01*
-X410717Y49868D01*
-X410717Y56812D01*
-X415628Y61723D01*
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-X422572Y44957D01*
-X415628Y44957D01*
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+X97791Y595131D01*
+X96437Y591864D01*
+X93936Y589363D01*
+X90669Y588009D01*
+X87131Y588009D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X441028Y44957D02*
-X441028Y44957D01*
-X436117Y49868D01*
-X436117Y56812D01*
-X441028Y61723D01*
-X447972Y61723D01*
-X452883Y56812D01*
-X452883Y49868D01*
-X447972Y44957D01*
-X441028Y44957D01*
+X87131Y562609D02*
+X87131Y562609D01*
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+X96437Y566464D01*
+X93936Y563963D01*
+X90669Y562609D01*
+X87131Y562609D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X199728Y207517D02*
-X199728Y207517D01*
-X194817Y212428D01*
-X194817Y219372D01*
-X199728Y224283D01*
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-X211583Y219372D01*
-X211583Y212428D01*
-X206672Y207517D01*
-X199728Y207517D01*
+X87131Y511809D02*
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+X96437Y515664D01*
+X93936Y513163D01*
+X90669Y511809D01*
+X87131Y511809D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X491828Y44957D02*
-X491828Y44957D01*
-X486917Y49868D01*
-X486917Y56812D01*
-X491828Y61723D01*
-X498772Y61723D01*
-X503683Y56812D01*
-X503683Y49868D01*
-X498772Y44957D01*
-X491828Y44957D01*
+X823747Y29289D02*
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+X834311Y36347D01*
+X832969Y33109D01*
+X830491Y30631D01*
+X827253Y29289D01*
+X823747Y29289D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X199728Y182117D02*
-X199728Y182117D01*
-X194817Y187028D01*
-X194817Y193972D01*
-X199728Y198883D01*
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-X211583Y187028D01*
-X206672Y182117D01*
-X199728Y182117D01*
+X874547Y29289D02*
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+X867489Y36347D01*
+X867489Y39853D01*
+X868831Y43091D01*
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+X878053Y46911D01*
+X881291Y45569D01*
+X883769Y43091D01*
+X885111Y39853D01*
+X885111Y36347D01*
+X883769Y33109D01*
+X881291Y30631D01*
+X878053Y29289D01*
+X874547Y29289D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X517228Y44957D02*
-X517228Y44957D01*
-X512317Y49868D01*
-X512317Y56812D01*
-X517228Y61723D01*
-X524172Y61723D01*
-X529083Y56812D01*
-X529083Y49868D01*
-X524172Y44957D01*
-X517228Y44957D01*
+X366547Y80089D02*
+X366547Y80089D01*
+X363309Y81431D01*
+X360831Y83909D01*
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+X359489Y90653D01*
+X360831Y93891D01*
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+X366547Y97711D01*
+X370053Y97711D01*
+X373291Y96369D01*
+X375769Y93891D01*
+X377111Y90653D01*
+X377111Y87147D01*
+X375769Y83909D01*
+X373291Y81431D01*
+X370053Y80089D01*
+X366547Y80089D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X542628Y44957D02*
-X542628Y44957D01*
-X537717Y49868D01*
-X537717Y56812D01*
-X542628Y61723D01*
-X549572Y61723D01*
-X554483Y56812D01*
-X554483Y49868D01*
-X549572Y44957D01*
-X542628Y44957D01*
+X849147Y29289D02*
+X849147Y29289D01*
+X845909Y30631D01*
+X843431Y33109D01*
+X842089Y36347D01*
+X842089Y39853D01*
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+X845909Y45569D01*
+X849147Y46911D01*
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+X859711Y36347D01*
+X858369Y33109D01*
+X855891Y30631D01*
+X852653Y29289D01*
+X849147Y29289D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X568028Y44957D02*
-X568028Y44957D01*
-X563117Y49868D01*
-X563117Y56812D01*
-X568028Y61723D01*
-X574972Y61723D01*
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-X579883Y49868D01*
-X574972Y44957D01*
-X568028Y44957D01*
+X823747Y80089D02*
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+X834311Y87147D01*
+X832969Y83909D01*
+X830491Y81431D01*
+X827253Y80089D01*
+X823747Y80089D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X390228Y44957D02*
-X390228Y44957D01*
-X385317Y49868D01*
-X385317Y56812D01*
-X390228Y61723D01*
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-X390228Y44957D01*
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+X377111Y61747D01*
+X375769Y58509D01*
+X373291Y56031D01*
+X370053Y54689D01*
+X366547Y54689D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X364828Y44957D02*
-X364828Y44957D01*
-X359917Y49868D01*
-X359917Y56812D01*
-X364828Y61723D01*
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+X859711Y87147D01*
+X858369Y83909D01*
+X855891Y81431D01*
+X852653Y80089D01*
+X849147Y80089D01*
 G37*
 %LPD*%
-%LPC*%
 G36*
-X466428Y44957D02*
-X466428Y44957D01*
-X461517Y49868D01*
-X461517Y56812D01*
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+X612148Y93639D01*
+X612169Y93551D01*
+X612181Y93462D01*
+X612206Y93397D01*
+X612223Y93330D01*
+X612265Y93250D01*
+X612298Y93167D01*
+X612339Y93110D01*
+X612371Y93048D01*
+X612432Y92982D01*
+X612484Y92909D01*
+X612538Y92865D01*
+X612585Y92813D01*
+X612660Y92764D01*
+X612729Y92706D01*
+X612793Y92677D01*
+X612851Y92638D01*
+X612936Y92609D01*
+X613017Y92571D01*
+X613086Y92558D01*
+X613152Y92535D01*
+X613241Y92528D01*
+X613329Y92511D01*
+X613399Y92515D01*
+X613469Y92510D01*
+X613557Y92525D01*
 G37*
-%LPD*%
 %LPC*%
 G36*
-X314028Y44957D02*
-X314028Y44957D01*
-X309117Y49868D01*
-X309117Y56812D01*
-X314028Y61723D01*
-X320972Y61723D01*
-X325883Y56812D01*
-X325883Y49868D01*
-X320972Y44957D01*
-X314028Y44957D01*
+X163433Y398017D02*
+X163433Y398017D01*
+X160352Y399293D01*
+X157993Y401652D01*
+X156717Y404733D01*
+X156717Y408067D01*
+X157993Y411148D01*
+X160352Y413507D01*
+X163433Y414783D01*
+X166767Y414783D01*
+X169848Y413507D01*
+X172207Y411148D01*
+X173483Y408067D01*
+X173483Y404733D01*
+X172207Y401652D01*
+X169848Y399293D01*
+X166767Y398017D01*
+X163433Y398017D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X288628Y44957D02*
-X288628Y44957D01*
-X283717Y49868D01*
-X283717Y56812D01*
-X288628Y61723D01*
-X295572Y61723D01*
-X300483Y56812D01*
-X300483Y49868D01*
-X295572Y44957D01*
-X288628Y44957D01*
+X188833Y398017D02*
+X188833Y398017D01*
+X185752Y399293D01*
+X183393Y401652D01*
+X182117Y404733D01*
+X182117Y408067D01*
+X183393Y411148D01*
+X185752Y413507D01*
+X188833Y414783D01*
+X192167Y414783D01*
+X195248Y413507D01*
+X197607Y411148D01*
+X198883Y408067D01*
+X198883Y404733D01*
+X197607Y401652D01*
+X195248Y399293D01*
+X192167Y398017D01*
+X188833Y398017D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X263228Y44957D02*
-X263228Y44957D01*
-X258317Y49868D01*
-X258317Y56812D01*
-X263228Y61723D01*
-X270172Y61723D01*
-X275083Y56812D01*
-X275083Y49868D01*
-X270172Y44957D01*
-X263228Y44957D01*
+X188833Y448817D02*
+X188833Y448817D01*
+X185752Y450093D01*
+X183393Y452452D01*
+X182117Y455533D01*
+X182117Y458867D01*
+X183393Y461948D01*
+X185752Y464307D01*
+X188833Y465583D01*
+X192167Y465583D01*
+X195248Y464307D01*
+X197607Y461948D01*
+X198883Y458867D01*
+X198883Y455533D01*
+X197607Y452452D01*
+X195248Y450093D01*
+X192167Y448817D01*
+X188833Y448817D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X212428Y44957D02*
-X212428Y44957D01*
-X207517Y49868D01*
-X207517Y56812D01*
-X212428Y61723D01*
-X219372Y61723D01*
-X224283Y56812D01*
-X224283Y49868D01*
-X219372Y44957D01*
-X212428Y44957D01*
+X163433Y448817D02*
+X163433Y448817D01*
+X160352Y450093D01*
+X157993Y452452D01*
+X156717Y455533D01*
+X156717Y458867D01*
+X157993Y461948D01*
+X160352Y464307D01*
+X163433Y465583D01*
+X166767Y465583D01*
+X169848Y464307D01*
+X172207Y461948D01*
+X173483Y458867D01*
+X173483Y455533D01*
+X172207Y452452D01*
+X169848Y450093D01*
+X166767Y448817D01*
+X163433Y448817D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X187028Y44957D02*
-X187028Y44957D01*
-X182117Y49868D01*
-X182117Y56812D01*
-X187028Y61723D01*
-X193972Y61723D01*
-X198883Y56812D01*
-X198883Y49868D01*
-X193972Y44957D01*
-X187028Y44957D01*
+X188833Y423417D02*
+X188833Y423417D01*
+X185752Y424693D01*
+X183393Y427052D01*
+X182117Y430133D01*
+X182117Y433467D01*
+X183393Y436548D01*
+X185752Y438907D01*
+X188833Y440183D01*
+X192167Y440183D01*
+X195248Y438907D01*
+X197607Y436548D01*
+X198883Y433467D01*
+X198883Y430133D01*
+X197607Y427052D01*
+X195248Y424693D01*
+X192167Y423417D01*
+X188833Y423417D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X593428Y44957D02*
-X593428Y44957D01*
-X588517Y49868D01*
-X588517Y56812D01*
-X593428Y61723D01*
-X600372Y61723D01*
-X605283Y56812D01*
-X605283Y49868D01*
-X600372Y44957D01*
-X593428Y44957D01*
+X163433Y423417D02*
+X163433Y423417D01*
+X160352Y424693D01*
+X157993Y427052D01*
+X156717Y430133D01*
+X156717Y433467D01*
+X157993Y436548D01*
+X160352Y438907D01*
+X163433Y440183D01*
+X166767Y440183D01*
+X169848Y438907D01*
+X172207Y436548D01*
+X173483Y433467D01*
+X173483Y430133D01*
+X172207Y427052D01*
+X169848Y424693D01*
+X166767Y423417D01*
+X163433Y423417D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X136228Y44957D02*
-X136228Y44957D01*
-X131317Y49868D01*
-X131317Y56812D01*
-X136228Y61723D01*
-X143172Y61723D01*
-X148083Y56812D01*
-X148083Y49868D01*
-X143172Y44957D01*
-X136228Y44957D01*
+X125434Y538225D02*
+X125434Y538225D01*
+X122539Y539424D01*
+X120324Y541639D01*
+X119125Y544534D01*
+X119125Y547666D01*
+X120324Y550561D01*
+X122539Y552776D01*
+X125434Y553975D01*
+X128566Y553975D01*
+X131461Y552776D01*
+X133676Y550561D01*
+X134875Y547666D01*
+X134875Y544534D01*
+X133676Y541639D01*
+X131461Y539424D01*
+X128566Y538225D01*
+X125434Y538225D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X110828Y44957D02*
-X110828Y44957D01*
-X105917Y49868D01*
-X105917Y56812D01*
-X110828Y61723D01*
-X117772Y61723D01*
-X122683Y56812D01*
-X122683Y49868D01*
-X117772Y44957D01*
-X110828Y44957D01*
+X735034Y4825D02*
+X735034Y4825D01*
+X732139Y6024D01*
+X729924Y8239D01*
+X728725Y11134D01*
+X728725Y14266D01*
+X729924Y17161D01*
+X732139Y19376D01*
+X735034Y20575D01*
+X738166Y20575D01*
+X741061Y19376D01*
+X743276Y17161D01*
+X744475Y14266D01*
+X744475Y11134D01*
+X743276Y8239D01*
+X741061Y6024D01*
+X738166Y4825D01*
+X735034Y4825D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X580938Y169925D02*
-X580938Y169925D01*
-X576325Y174538D01*
-X576325Y181062D01*
-X580938Y185675D01*
-X587462Y185675D01*
-X592075Y181062D01*
-X592075Y174538D01*
-X587462Y169925D01*
-X580938Y169925D01*
+X760434Y4825D02*
+X760434Y4825D01*
+X757539Y6024D01*
+X755324Y8239D01*
+X754125Y11134D01*
+X754125Y14266D01*
+X755324Y17161D01*
+X757539Y19376D01*
+X760434Y20575D01*
+X763566Y20575D01*
+X766461Y19376D01*
+X768676Y17161D01*
+X769875Y14266D01*
+X769875Y11134D01*
+X768676Y8239D01*
+X766461Y6024D01*
+X763566Y4825D01*
+X760434Y4825D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X580938Y296925D02*
-X580938Y296925D01*
-X576325Y301538D01*
-X576325Y308062D01*
-X580938Y312675D01*
-X587462Y312675D01*
-X592075Y308062D01*
-X592075Y301538D01*
-X587462Y296925D01*
-X580938Y296925D01*
+X785834Y4825D02*
+X785834Y4825D01*
+X782939Y6024D01*
+X780724Y8239D01*
+X779525Y11134D01*
+X779525Y14266D01*
+X780724Y17161D01*
+X782939Y19376D01*
+X785834Y20575D01*
+X788966Y20575D01*
+X791861Y19376D01*
+X794076Y17161D01*
+X795275Y14266D01*
+X795275Y11134D01*
+X794076Y8239D01*
+X791861Y6024D01*
+X788966Y4825D01*
+X785834Y4825D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X174538Y182625D02*
-X174538Y182625D01*
-X169925Y187238D01*
-X169925Y193762D01*
-X174538Y198375D01*
-X181062Y198375D01*
-X185675Y193762D01*
-X185675Y187238D01*
-X181062Y182625D01*
-X174538Y182625D01*
+X214334Y398525D02*
+X214334Y398525D01*
+X211439Y399724D01*
+X209224Y401939D01*
+X208025Y404834D01*
+X208025Y407966D01*
+X209224Y410861D01*
+X211439Y413076D01*
+X214334Y414275D01*
+X217466Y414275D01*
+X220361Y413076D01*
+X222576Y410861D01*
+X223775Y407966D01*
+X223775Y404834D01*
+X222576Y401939D01*
+X220361Y399724D01*
+X217466Y398525D01*
+X214334Y398525D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X47538Y182625D02*
-X47538Y182625D01*
-X42925Y187238D01*
-X42925Y193762D01*
-X47538Y198375D01*
-X54062Y198375D01*
-X58675Y193762D01*
-X58675Y187238D01*
-X54062Y182625D01*
-X47538Y182625D01*
+X811234Y4825D02*
+X811234Y4825D01*
+X808339Y6024D01*
+X806124Y8239D01*
+X804925Y11134D01*
+X804925Y14266D01*
+X806124Y17161D01*
+X808339Y19376D01*
+X811234Y20575D01*
+X814366Y20575D01*
+X817261Y19376D01*
+X819476Y17161D01*
+X820675Y14266D01*
+X820675Y11134D01*
+X819476Y8239D01*
+X817261Y6024D01*
+X814366Y4825D01*
+X811234Y4825D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X47538Y208025D02*
-X47538Y208025D01*
-X42925Y212638D01*
-X42925Y219162D01*
-X47538Y223775D01*
-X54062Y223775D01*
-X58675Y219162D01*
-X58675Y212638D01*
-X54062Y208025D01*
-X47538Y208025D01*
+X862034Y4825D02*
+X862034Y4825D01*
+X859139Y6024D01*
+X856924Y8239D01*
+X855725Y11134D01*
+X855725Y14266D01*
+X856924Y17161D01*
+X859139Y19376D01*
+X862034Y20575D01*
+X865166Y20575D01*
+X868061Y19376D01*
+X870276Y17161D01*
+X871475Y14266D01*
+X871475Y11134D01*
+X870276Y8239D01*
+X868061Y6024D01*
+X865166Y4825D01*
+X862034Y4825D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X174538Y208025D02*
-X174538Y208025D01*
-X169925Y212638D01*
-X169925Y219162D01*
-X174538Y223775D01*
-X181062Y223775D01*
-X185675Y219162D01*
-X185675Y212638D01*
-X181062Y208025D01*
-X174538Y208025D01*
+X150834Y614425D02*
+X150834Y614425D01*
+X147939Y615624D01*
+X145724Y617839D01*
+X144525Y620734D01*
+X144525Y623866D01*
+X145724Y626761D01*
+X147939Y628976D01*
+X150834Y630175D01*
+X153966Y630175D01*
+X156861Y628976D01*
+X159076Y626761D01*
+X160275Y623866D01*
+X160275Y620734D01*
+X159076Y617839D01*
+X156861Y615624D01*
+X153966Y614425D01*
+X150834Y614425D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X276138Y322325D02*
-X276138Y322325D01*
-X271525Y326938D01*
-X271525Y333462D01*
-X276138Y338075D01*
-X282662Y338075D01*
-X287275Y333462D01*
-X287275Y326938D01*
-X282662Y322325D01*
-X276138Y322325D01*
+X836634Y4825D02*
+X836634Y4825D01*
+X833739Y6024D01*
+X831524Y8239D01*
+X830325Y11134D01*
+X830325Y14266D01*
+X831524Y17161D01*
+X833739Y19376D01*
+X836634Y20575D01*
+X839766Y20575D01*
+X842661Y19376D01*
+X844876Y17161D01*
+X846075Y14266D01*
+X846075Y11134D01*
+X844876Y8239D01*
+X842661Y6024D01*
+X839766Y4825D01*
+X836634Y4825D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X174538Y157225D02*
-X174538Y157225D01*
-X169925Y161838D01*
-X169925Y168362D01*
-X174538Y172975D01*
-X181062Y172975D01*
-X185675Y168362D01*
-X185675Y161838D01*
-X181062Y157225D01*
-X174538Y157225D01*
+X811234Y233425D02*
+X811234Y233425D01*
+X808339Y234624D01*
+X806124Y236839D01*
+X804925Y239734D01*
+X804925Y242866D01*
+X806124Y245761D01*
+X808339Y247976D01*
+X811234Y249175D01*
+X814366Y249175D01*
+X817261Y247976D01*
+X819476Y245761D01*
+X820675Y242866D01*
+X820675Y239734D01*
+X819476Y236839D01*
+X817261Y234624D01*
+X814366Y233425D01*
+X811234Y233425D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X403138Y360425D02*
-X403138Y360425D01*
-X398525Y365038D01*
-X398525Y371562D01*
-X403138Y376175D01*
-X409662Y376175D01*
-X414275Y371562D01*
-X414275Y365038D01*
-X409662Y360425D01*
-X403138Y360425D01*
+X836634Y106425D02*
+X836634Y106425D01*
+X833739Y107624D01*
+X831524Y109839D01*
+X830325Y112734D01*
+X830325Y115866D01*
+X831524Y118761D01*
+X833739Y120976D01*
+X836634Y122175D01*
+X839766Y122175D01*
+X842661Y120976D01*
+X844876Y118761D01*
+X846075Y115866D01*
+X846075Y112734D01*
+X844876Y109839D01*
+X842661Y107624D01*
+X839766Y106425D01*
+X836634Y106425D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X326938Y360425D02*
-X326938Y360425D01*
-X322325Y365038D01*
-X322325Y371562D01*
-X326938Y376175D01*
-X333462Y376175D01*
-X338075Y371562D01*
-X338075Y365038D01*
-X333462Y360425D01*
-X326938Y360425D01*
-G37*
-%LPD*%
-%LPC*%
-G36*
-X227034Y271525D02*
-X227034Y271525D01*
-X224139Y272724D01*
-X221924Y274939D01*
-X220725Y277834D01*
-X220725Y280966D01*
-X221924Y283861D01*
-X224139Y286076D01*
-X227034Y287275D01*
-X230166Y287275D01*
-X233061Y286076D01*
-X235276Y283861D01*
-X236475Y280966D01*
-X236475Y277834D01*
-X235276Y274939D01*
-X233061Y272724D01*
-X230166Y271525D01*
-X227034Y271525D01*
+X506434Y233425D02*
+X506434Y233425D01*
+X503539Y234624D01*
+X501324Y236839D01*
+X500125Y239734D01*
+X500125Y242866D01*
+X501324Y245761D01*
+X503539Y247976D01*
+X506434Y249175D01*
+X509566Y249175D01*
+X512461Y247976D01*
+X514676Y245761D01*
+X515875Y242866D01*
+X515875Y239734D01*
+X514676Y236839D01*
+X512461Y234624D01*
+X509566Y233425D01*
+X506434Y233425D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X150834Y347725D02*
-X150834Y347725D01*
-X147939Y348924D01*
-X145724Y351139D01*
-X144525Y354034D01*
-X144525Y357166D01*
-X145724Y360061D01*
-X147939Y362276D01*
-X150834Y363475D01*
-X153966Y363475D01*
-X156861Y362276D01*
-X159076Y360061D01*
-X160275Y357166D01*
-X160275Y354034D01*
-X159076Y351139D01*
-X156861Y348924D01*
-X153966Y347725D01*
-X150834Y347725D01*
-G37*
-%LPD*%
-%LPC*%
-G36*
-X26669Y166369D02*
-X26669Y166369D01*
-X26669Y174245D01*
-X32905Y174245D01*
-X34671Y173893D01*
-X36336Y173204D01*
-X37833Y172203D01*
-X39107Y170929D01*
-X40108Y169432D01*
-X40797Y167767D01*
-X41075Y166369D01*
-X26669Y166369D01*
-G37*
-%LPD*%
-%LPC*%
-G36*
-X953769Y153669D02*
-X953769Y153669D01*
-X953769Y168075D01*
-X955167Y167797D01*
-X956832Y167108D01*
-X958329Y166107D01*
-X959603Y164833D01*
-X960604Y163336D01*
-X961293Y161671D01*
-X961645Y159905D01*
-X961645Y153669D01*
-X953769Y153669D01*
-G37*
-%LPD*%
-%LPC*%
-G36*
-X953769Y280669D02*
-X953769Y280669D01*
-X953769Y295075D01*
-X955167Y294797D01*
-X956832Y294108D01*
-X958329Y293107D01*
-X959603Y291833D01*
-X960604Y290336D01*
-X961293Y288671D01*
-X961645Y286905D01*
-X961645Y280669D01*
-X953769Y280669D01*
-G37*
-%LPD*%
-%LPC*%
-G36*
-X9725Y166369D02*
-X9725Y166369D01*
-X10003Y167767D01*
-X10692Y169432D01*
-X11693Y170929D01*
-X12967Y172203D01*
-X14464Y173204D01*
-X16129Y173893D01*
-X17895Y174245D01*
-X24131Y174245D01*
-X24131Y166369D01*
-X9725Y166369D01*
-G37*
-%LPD*%
-%LPC*%
-G36*
-X953769Y278131D02*
-X953769Y278131D01*
-X961645Y278131D01*
-X961645Y271895D01*
-X961293Y270129D01*
-X960604Y268464D01*
-X959603Y266967D01*
-X958329Y265693D01*
-X956832Y264692D01*
-X955167Y264003D01*
-X953769Y263725D01*
-X953769Y278131D01*
-G37*
-%LPD*%
-%LPC*%
-G36*
-X953769Y151131D02*
-X953769Y151131D01*
-X961645Y151131D01*
-X961645Y144895D01*
-X961293Y143129D01*
-X960604Y141464D01*
-X959603Y139967D01*
-X958329Y138693D01*
-X956832Y137692D01*
-X955167Y137003D01*
-X953769Y136725D01*
-X953769Y151131D01*
+X455634Y233425D02*
+X455634Y233425D01*
+X452739Y234624D01*
+X450524Y236839D01*
+X449325Y239734D01*
+X449325Y242866D01*
+X450524Y245761D01*
+X452739Y247976D01*
+X455634Y249175D01*
+X458766Y249175D01*
+X461661Y247976D01*
+X463876Y245761D01*
+X465075Y242866D01*
+X465075Y239734D01*
+X463876Y236839D01*
+X461661Y234624D01*
+X458766Y233425D01*
+X455634Y233425D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X943355Y153669D02*
-X943355Y153669D01*
-X943355Y159905D01*
-X943707Y161671D01*
-X944396Y163336D01*
-X945397Y164833D01*
-X946671Y166107D01*
-X948168Y167108D01*
-X949833Y167797D01*
-X951231Y168075D01*
-X951231Y153669D01*
-X943355Y153669D01*
+X862034Y106425D02*
+X862034Y106425D01*
+X859139Y107624D01*
+X856924Y109839D01*
+X855725Y112734D01*
+X855725Y115866D01*
+X856924Y118761D01*
+X859139Y120976D01*
+X862034Y122175D01*
+X865166Y122175D01*
+X868061Y120976D01*
+X870276Y118761D01*
+X871475Y115866D01*
+X871475Y112734D01*
+X870276Y109839D01*
+X868061Y107624D01*
+X865166Y106425D01*
+X862034Y106425D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X26669Y155955D02*
-X26669Y155955D01*
-X26669Y163831D01*
-X41075Y163831D01*
-X40797Y162433D01*
-X40108Y160768D01*
-X39107Y159271D01*
-X37833Y157997D01*
-X36336Y156996D01*
-X34671Y156307D01*
-X32905Y155955D01*
-X26669Y155955D01*
+X811234Y106425D02*
+X811234Y106425D01*
+X808339Y107624D01*
+X806124Y109839D01*
+X804925Y112734D01*
+X804925Y115866D01*
+X806124Y118761D01*
+X808339Y120976D01*
+X811234Y122175D01*
+X814366Y122175D01*
+X817261Y120976D01*
+X819476Y118761D01*
+X820675Y115866D01*
+X820675Y112734D01*
+X819476Y109839D01*
+X817261Y107624D01*
+X814366Y106425D01*
+X811234Y106425D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X943355Y280669D02*
-X943355Y280669D01*
-X943355Y286905D01*
-X943707Y288671D01*
-X944396Y290336D01*
-X945397Y291833D01*
-X946671Y293107D01*
-X948168Y294108D01*
-X949833Y294797D01*
-X951231Y295075D01*
-X951231Y280669D01*
-X943355Y280669D01*
+X214334Y449325D02*
+X214334Y449325D01*
+X211439Y450524D01*
+X209224Y452739D01*
+X208025Y455634D01*
+X208025Y458766D01*
+X209224Y461661D01*
+X211439Y463876D01*
+X214334Y465075D01*
+X217466Y465075D01*
+X220361Y463876D01*
+X222576Y461661D01*
+X223775Y458766D01*
+X223775Y455634D01*
+X222576Y452739D01*
+X220361Y450524D01*
+X217466Y449325D01*
+X214334Y449325D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X949833Y264003D02*
-X949833Y264003D01*
-X948168Y264692D01*
-X946671Y265693D01*
-X945397Y266967D01*
-X944396Y268464D01*
-X943707Y270129D01*
-X943355Y271895D01*
-X943355Y278131D01*
-X951231Y278131D01*
-X951231Y263725D01*
-X949833Y264003D01*
+X252434Y233425D02*
+X252434Y233425D01*
+X249539Y234624D01*
+X247324Y236839D01*
+X246125Y239734D01*
+X246125Y242866D01*
+X247324Y245761D01*
+X249539Y247976D01*
+X252434Y249175D01*
+X255566Y249175D01*
+X258461Y247976D01*
+X260676Y245761D01*
+X261875Y242866D01*
+X261875Y239734D01*
+X260676Y236839D01*
+X258461Y234624D01*
+X255566Y233425D01*
+X252434Y233425D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X949833Y137003D02*
-X949833Y137003D01*
-X948168Y137692D01*
-X946671Y138693D01*
-X945397Y139967D01*
-X944396Y141464D01*
-X943707Y143129D01*
-X943355Y144895D01*
-X943355Y151131D01*
-X951231Y151131D01*
-X951231Y136725D01*
-X949833Y137003D01*
+X227034Y233425D02*
+X227034Y233425D01*
+X224139Y234624D01*
+X221924Y236839D01*
+X220725Y239734D01*
+X220725Y242866D01*
+X221924Y245761D01*
+X224139Y247976D01*
+X227034Y249175D01*
+X230166Y249175D01*
+X233061Y247976D01*
+X235276Y245761D01*
+X236475Y242866D01*
+X236475Y239734D01*
+X235276Y236839D01*
+X233061Y234624D01*
+X230166Y233425D01*
+X227034Y233425D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X17895Y155955D02*
-X17895Y155955D01*
-X16129Y156307D01*
-X14464Y156996D01*
-X12967Y157997D01*
-X11693Y159271D01*
-X10692Y160768D01*
-X10003Y162433D01*
-X9725Y163831D01*
-X24131Y163831D01*
-X24131Y155955D01*
-X17895Y155955D01*
+X201634Y233425D02*
+X201634Y233425D01*
+X198739Y234624D01*
+X196524Y236839D01*
+X195325Y239734D01*
+X195325Y242866D01*
+X196524Y245761D01*
+X198739Y247976D01*
+X201634Y249175D01*
+X204766Y249175D01*
+X207661Y247976D01*
+X209876Y245761D01*
+X211075Y242866D01*
+X211075Y239734D01*
+X209876Y236839D01*
+X207661Y234624D01*
+X204766Y233425D01*
+X201634Y233425D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X547369Y204469D02*
-X547369Y204469D01*
-X547369Y213361D01*
-X550309Y213361D01*
-X556261Y207409D01*
-X556261Y204469D01*
-X547369Y204469D01*
+X176234Y233425D02*
+X176234Y233425D01*
+X173339Y234624D01*
+X171124Y236839D01*
+X169925Y239734D01*
+X169925Y242866D01*
+X171124Y245761D01*
+X173339Y247976D01*
+X176234Y249175D01*
+X179366Y249175D01*
+X182261Y247976D01*
+X184476Y245761D01*
+X185675Y242866D01*
+X185675Y239734D01*
+X184476Y236839D01*
+X182261Y234624D01*
+X179366Y233425D01*
+X176234Y233425D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X547369Y306069D02*
-X547369Y306069D01*
-X547369Y314961D01*
-X550309Y314961D01*
-X556261Y309009D01*
-X556261Y306069D01*
-X547369Y306069D01*
+X760434Y233425D02*
+X760434Y233425D01*
+X757539Y234624D01*
+X755324Y236839D01*
+X754125Y239734D01*
+X754125Y242866D01*
+X755324Y245761D01*
+X757539Y247976D01*
+X760434Y249175D01*
+X763566Y249175D01*
+X766461Y247976D01*
+X768676Y245761D01*
+X769875Y242866D01*
+X769875Y239734D01*
+X768676Y236839D01*
+X766461Y234624D01*
+X763566Y233425D01*
+X760434Y233425D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X547369Y303531D02*
-X547369Y303531D01*
-X556261Y303531D01*
-X556261Y300591D01*
-X550309Y294639D01*
-X547369Y294639D01*
-X547369Y303531D01*
+X150834Y538225D02*
+X150834Y538225D01*
+X147939Y539424D01*
+X145724Y541639D01*
+X144525Y544534D01*
+X144525Y547666D01*
+X145724Y550561D01*
+X147939Y552776D01*
+X150834Y553975D01*
+X153966Y553975D01*
+X156861Y552776D01*
+X159076Y550561D01*
+X160275Y547666D01*
+X160275Y544534D01*
+X159076Y541639D01*
+X156861Y539424D01*
+X153966Y538225D01*
+X150834Y538225D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X547369Y201931D02*
-X547369Y201931D01*
-X556261Y201931D01*
-X556261Y198991D01*
-X550309Y193039D01*
-X547369Y193039D01*
-X547369Y201931D01*
+X214334Y423925D02*
+X214334Y423925D01*
+X211439Y425124D01*
+X209224Y427339D01*
+X208025Y430234D01*
+X208025Y433366D01*
+X209224Y436261D01*
+X211439Y438476D01*
+X214334Y439675D01*
+X217466Y439675D01*
+X220361Y438476D01*
+X222576Y436261D01*
+X223775Y433366D01*
+X223775Y430234D01*
+X222576Y427339D01*
+X220361Y425124D01*
+X217466Y423925D01*
+X214334Y423925D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X535939Y306069D02*
-X535939Y306069D01*
-X535939Y309009D01*
-X541891Y314961D01*
-X544831Y314961D01*
-X544831Y306069D01*
-X535939Y306069D01*
+X277834Y233425D02*
+X277834Y233425D01*
+X274939Y234624D01*
+X272724Y236839D01*
+X271525Y239734D01*
+X271525Y242866D01*
+X272724Y245761D01*
+X274939Y247976D01*
+X277834Y249175D01*
+X280966Y249175D01*
+X283861Y247976D01*
+X286076Y245761D01*
+X287275Y242866D01*
+X287275Y239734D01*
+X286076Y236839D01*
+X283861Y234624D01*
+X280966Y233425D01*
+X277834Y233425D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X535939Y204469D02*
-X535939Y204469D01*
-X535939Y207409D01*
-X541891Y213361D01*
-X544831Y213361D01*
-X544831Y204469D01*
-X535939Y204469D01*
+X709634Y4825D02*
+X709634Y4825D01*
+X706739Y6024D01*
+X704524Y8239D01*
+X703325Y11134D01*
+X703325Y14266D01*
+X704524Y17161D01*
+X706739Y19376D01*
+X709634Y20575D01*
+X712766Y20575D01*
+X715661Y19376D01*
+X717876Y17161D01*
+X719075Y14266D01*
+X719075Y11134D01*
+X717876Y8239D01*
+X715661Y6024D01*
+X712766Y4825D01*
+X709634Y4825D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X541891Y294639D02*
-X541891Y294639D01*
-X535939Y300591D01*
-X535939Y303531D01*
-X544831Y303531D01*
-X544831Y294639D01*
-X541891Y294639D01*
+X684234Y4825D02*
+X684234Y4825D01*
+X681339Y6024D01*
+X679124Y8239D01*
+X677925Y11134D01*
+X677925Y14266D01*
+X679124Y17161D01*
+X681339Y19376D01*
+X684234Y20575D01*
+X687366Y20575D01*
+X690261Y19376D01*
+X692476Y17161D01*
+X693675Y14266D01*
+X693675Y11134D01*
+X692476Y8239D01*
+X690261Y6024D01*
+X687366Y4825D01*
+X684234Y4825D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X541891Y193039D02*
-X541891Y193039D01*
-X535939Y198991D01*
-X535939Y201931D01*
-X544831Y201931D01*
-X544831Y193039D01*
-X541891Y193039D01*
+X658834Y4825D02*
+X658834Y4825D01*
+X655939Y6024D01*
+X653724Y8239D01*
+X652525Y11134D01*
+X652525Y14266D01*
+X653724Y17161D01*
+X655939Y19376D01*
+X658834Y20575D01*
+X661966Y20575D01*
+X664861Y19376D01*
+X667076Y17161D01*
+X668275Y14266D01*
+X668275Y11134D01*
+X667076Y8239D01*
+X664861Y6024D01*
+X661966Y4825D01*
+X658834Y4825D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X750569Y80009D02*
-X750569Y80009D01*
-X750569Y88393D01*
-X753298Y88393D01*
-X758953Y82738D01*
-X758953Y80009D01*
-X750569Y80009D01*
+X633434Y4825D02*
+X633434Y4825D01*
+X630539Y6024D01*
+X628324Y8239D01*
+X627125Y11134D01*
+X627125Y14266D01*
+X628324Y17161D01*
+X630539Y19376D01*
+X633434Y20575D01*
+X636566Y20575D01*
+X639461Y19376D01*
+X641676Y17161D01*
+X642875Y14266D01*
+X642875Y11134D01*
+X641676Y8239D01*
+X639461Y6024D01*
+X636566Y4825D01*
+X633434Y4825D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X166369Y105409D02*
-X166369Y105409D01*
-X166369Y113793D01*
-X169098Y113793D01*
-X174753Y108138D01*
-X174753Y105409D01*
-X166369Y105409D01*
+X608034Y4825D02*
+X608034Y4825D01*
+X605139Y6024D01*
+X602924Y8239D01*
+X601725Y11134D01*
+X601725Y14266D01*
+X602924Y17161D01*
+X605139Y19376D01*
+X608034Y20575D01*
+X611166Y20575D01*
+X614061Y19376D01*
+X616276Y17161D01*
+X617475Y14266D01*
+X617475Y11134D01*
+X616276Y8239D01*
+X614061Y6024D01*
+X611166Y4825D01*
+X608034Y4825D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X852169Y80009D02*
-X852169Y80009D01*
-X852169Y88393D01*
-X854898Y88393D01*
-X860553Y82738D01*
-X860553Y80009D01*
-X852169Y80009D01*
+X557234Y4825D02*
+X557234Y4825D01*
+X554339Y6024D01*
+X552124Y8239D01*
+X550925Y11134D01*
+X550925Y14266D01*
+X552124Y17161D01*
+X554339Y19376D01*
+X557234Y20575D01*
+X560366Y20575D01*
+X563261Y19376D01*
+X565476Y17161D01*
+X566675Y14266D01*
+X566675Y11134D01*
+X565476Y8239D01*
+X563261Y6024D01*
+X560366Y4825D01*
+X557234Y4825D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X191769Y80009D02*
-X191769Y80009D01*
-X191769Y88393D01*
-X194498Y88393D01*
-X200153Y82738D01*
-X200153Y80009D01*
-X191769Y80009D01*
+X481034Y4825D02*
+X481034Y4825D01*
+X478139Y6024D01*
+X475924Y8239D01*
+X474725Y11134D01*
+X474725Y14266D01*
+X475924Y17161D01*
+X478139Y19376D01*
+X481034Y20575D01*
+X484166Y20575D01*
+X487061Y19376D01*
+X489276Y17161D01*
+X490475Y14266D01*
+X490475Y11134D01*
+X489276Y8239D01*
+X487061Y6024D01*
+X484166Y4825D01*
+X481034Y4825D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X699769Y80009D02*
-X699769Y80009D01*
-X699769Y88393D01*
-X702498Y88393D01*
-X708153Y82738D01*
-X708153Y80009D01*
-X699769Y80009D01*
+X455634Y4825D02*
+X455634Y4825D01*
+X452739Y6024D01*
+X450524Y8239D01*
+X449325Y11134D01*
+X449325Y14266D01*
+X450524Y17161D01*
+X452739Y19376D01*
+X455634Y20575D01*
+X458766Y20575D01*
+X461661Y19376D01*
+X463876Y17161D01*
+X465075Y14266D01*
+X465075Y11134D01*
+X463876Y8239D01*
+X461661Y6024D01*
+X458766Y4825D01*
+X455634Y4825D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X877569Y80009D02*
-X877569Y80009D01*
-X877569Y88393D01*
-X880298Y88393D01*
-X885953Y82738D01*
-X885953Y80009D01*
-X877569Y80009D01*
+X430234Y4825D02*
+X430234Y4825D01*
+X427339Y6024D01*
+X425124Y8239D01*
+X423925Y11134D01*
+X423925Y14266D01*
+X425124Y17161D01*
+X427339Y19376D01*
+X430234Y20575D01*
+X433366Y20575D01*
+X436261Y19376D01*
+X438476Y17161D01*
+X439675Y14266D01*
+X439675Y11134D01*
+X438476Y8239D01*
+X436261Y6024D01*
+X433366Y4825D01*
+X430234Y4825D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X826769Y80009D02*
-X826769Y80009D01*
-X826769Y88393D01*
-X829498Y88393D01*
-X835153Y82738D01*
-X835153Y80009D01*
-X826769Y80009D01*
+X404834Y4825D02*
+X404834Y4825D01*
+X401939Y6024D01*
+X399724Y8239D01*
+X398525Y11134D01*
+X398525Y14266D01*
+X399724Y17161D01*
+X401939Y19376D01*
+X404834Y20575D01*
+X407966Y20575D01*
+X410861Y19376D01*
+X413076Y17161D01*
+X414275Y14266D01*
+X414275Y11134D01*
+X413076Y8239D01*
+X410861Y6024D01*
+X407966Y4825D01*
+X404834Y4825D01*
 G37*
 %LPD*%
-%LPC*%
 G36*
-X775969Y80009D02*
-X775969Y80009D01*
-X775969Y88393D01*
-X778698Y88393D01*
-X784353Y82738D01*
-X784353Y80009D01*
-X775969Y80009D01*
+X412579Y172738D02*
+X412579Y172738D01*
+X412718Y172751D01*
+X412737Y172758D01*
+X412757Y172761D01*
+X412886Y172812D01*
+X413018Y172859D01*
+X413034Y172870D01*
+X413053Y172878D01*
+X413165Y172959D01*
+X413281Y173037D01*
+X413294Y173053D01*
+X413310Y173064D01*
+X413399Y173172D01*
+X413491Y173276D01*
+X413500Y173294D01*
+X413513Y173309D01*
+X413573Y173435D01*
+X413636Y173559D01*
+X413640Y173579D01*
+X413649Y173597D01*
+X413675Y173733D01*
+X413705Y173869D01*
+X413705Y173890D01*
+X413709Y173909D01*
+X413700Y174048D01*
+X413696Y174187D01*
+X413690Y174207D01*
+X413689Y174227D01*
+X413646Y174359D01*
+X413607Y174493D01*
+X413597Y174510D01*
+X413591Y174529D01*
+X413516Y174647D01*
+X413446Y174767D01*
+X413427Y174788D01*
+X413421Y174798D01*
+X413406Y174812D01*
+X413339Y174887D01*
+X402393Y185834D01*
+X402315Y185894D01*
+X402243Y185962D01*
+X402190Y185991D01*
+X402142Y186028D01*
+X402051Y186068D01*
+X401964Y186116D01*
+X401906Y186131D01*
+X401850Y186155D01*
+X401752Y186170D01*
+X401657Y186195D01*
+X401556Y186201D01*
+X401536Y186205D01*
+X401524Y186203D01*
+X401496Y186205D01*
+X399541Y186205D01*
+X397025Y188721D01*
+X397025Y190676D01*
+X397013Y190774D01*
+X397010Y190873D01*
+X396993Y190931D01*
+X396985Y190991D01*
+X396949Y191083D01*
+X396921Y191179D01*
+X396891Y191231D01*
+X396868Y191287D01*
+X396810Y191367D01*
+X396760Y191452D01*
+X396694Y191528D01*
+X396682Y191544D01*
+X396672Y191552D01*
+X396654Y191573D01*
+X395559Y192668D01*
+X395481Y192728D01*
+X395409Y192796D01*
+X395356Y192825D01*
+X395308Y192862D01*
+X395217Y192902D01*
+X395130Y192950D01*
+X395072Y192965D01*
+X395016Y192989D01*
+X394918Y193004D01*
+X394823Y193029D01*
+X394722Y193035D01*
+X394702Y193039D01*
+X394690Y193037D01*
+X394662Y193039D01*
+X387658Y193039D01*
+X387520Y193022D01*
+X387382Y193009D01*
+X387363Y193002D01*
+X387343Y192999D01*
+X387213Y192948D01*
+X387082Y192901D01*
+X387066Y192890D01*
+X387047Y192882D01*
+X386935Y192801D01*
+X386819Y192723D01*
+X386806Y192707D01*
+X386790Y192696D01*
+X386701Y192588D01*
+X386609Y192484D01*
+X386600Y192466D01*
+X386587Y192451D01*
+X386527Y192325D01*
+X386464Y192201D01*
+X386460Y192181D01*
+X386451Y192163D01*
+X386425Y192026D01*
+X386395Y191891D01*
+X386395Y191870D01*
+X386391Y191851D01*
+X386400Y191712D01*
+X386404Y191573D01*
+X386410Y191553D01*
+X386411Y191533D01*
+X386454Y191401D01*
+X386493Y191267D01*
+X386503Y191250D01*
+X386509Y191231D01*
+X386584Y191113D01*
+X386654Y190993D01*
+X386673Y190972D01*
+X386679Y190962D01*
+X386694Y190948D01*
+X386761Y190873D01*
+X387547Y190086D01*
+X387625Y190026D01*
+X387697Y189958D01*
+X387750Y189929D01*
+X387798Y189892D01*
+X387889Y189852D01*
+X387976Y189804D01*
+X388034Y189789D01*
+X388090Y189765D01*
+X388188Y189750D01*
+X388283Y189725D01*
+X388384Y189719D01*
+X388404Y189715D01*
+X388416Y189717D01*
+X388444Y189715D01*
+X390399Y189715D01*
+X392915Y187199D01*
+X392915Y185244D01*
+X392927Y185146D01*
+X392930Y185047D01*
+X392947Y184989D01*
+X392955Y184929D01*
+X392991Y184837D01*
+X393019Y184741D01*
+X393049Y184689D01*
+X393072Y184633D01*
+X393130Y184553D01*
+X393180Y184468D01*
+X393246Y184392D01*
+X393258Y184376D01*
+X393268Y184368D01*
+X393286Y184347D01*
+X404541Y173092D01*
+X404619Y173032D01*
+X404691Y172964D01*
+X404744Y172935D01*
+X404792Y172898D01*
+X404883Y172858D01*
+X404970Y172810D01*
+X405028Y172795D01*
+X405084Y172771D01*
+X405182Y172756D01*
+X405277Y172731D01*
+X405378Y172725D01*
+X405398Y172721D01*
+X405410Y172723D01*
+X405438Y172721D01*
+X412442Y172721D01*
+X412579Y172738D01*
 G37*
-%LPD*%
-%LPC*%
-G36*
-X725169Y80009D02*
-X725169Y80009D01*
-X725169Y88393D01*
-X727898Y88393D01*
-X733553Y82738D01*
-X733553Y80009D01*
-X725169Y80009D01*
-G37*
-%LPD*%
-%LPC*%
-G36*
-X801369Y80009D02*
-X801369Y80009D01*
-X801369Y88393D01*
-X804098Y88393D01*
-X809753Y82738D01*
-X809753Y80009D01*
-X801369Y80009D01*
-G37*
-%LPD*%
-%LPC*%
-G36*
-X902969Y80009D02*
-X902969Y80009D01*
-X902969Y88393D01*
-X905698Y88393D01*
-X911353Y82738D01*
-X911353Y80009D01*
-X902969Y80009D01*
-G37*
-%LPD*%
-%LPC*%
-G36*
-X166369Y54609D02*
-X166369Y54609D01*
-X166369Y62993D01*
-X169098Y62993D01*
-X174753Y57338D01*
-X174753Y54609D01*
-X166369Y54609D01*
-G37*
-%LPD*%
-%LPC*%
-G36*
-X892047Y80009D02*
-X892047Y80009D01*
-X892047Y82738D01*
-X897702Y88393D01*
-X900431Y88393D01*
-X900431Y80009D01*
-X892047Y80009D01*
-G37*
-%LPD*%
-%LPC*%
-G36*
-X688847Y80009D02*
-X688847Y80009D01*
-X688847Y82738D01*
-X694502Y88393D01*
-X697231Y88393D01*
-X697231Y80009D01*
-X688847Y80009D01*
-G37*
-%LPD*%
-%LPC*%
-G36*
-X815847Y80009D02*
-X815847Y80009D01*
-X815847Y82738D01*
-X821502Y88393D01*
-X824231Y88393D01*
-X824231Y80009D01*
-X815847Y80009D01*
-G37*
-%LPD*%
-%LPC*%
-G36*
-X866647Y80009D02*
-X866647Y80009D01*
-X866647Y82738D01*
-X872302Y88393D01*
-X875031Y88393D01*
-X875031Y80009D01*
-X866647Y80009D01*
-G37*
-%LPD*%
-%LPC*%
-G36*
-X841247Y80009D02*
-X841247Y80009D01*
-X841247Y82738D01*
-X846902Y88393D01*
-X849631Y88393D01*
-X849631Y80009D01*
-X841247Y80009D01*
-G37*
-%LPD*%
-%LPC*%
-G36*
-X765047Y80009D02*
-X765047Y80009D01*
-X765047Y82738D01*
-X770702Y88393D01*
-X773431Y88393D01*
-X773431Y80009D01*
-X765047Y80009D01*
-G37*
-%LPD*%
-%LPC*%
-G36*
-X155447Y105409D02*
-X155447Y105409D01*
-X155447Y108138D01*
-X161102Y113793D01*
-X163831Y113793D01*
-X163831Y105409D01*
-X155447Y105409D01*
-G37*
-%LPD*%
-%LPC*%
-G36*
-X739647Y80009D02*
-X739647Y80009D01*
-X739647Y82738D01*
-X745302Y88393D01*
-X748031Y88393D01*
-X748031Y80009D01*
-X739647Y80009D01*
-G37*
-%LPD*%
-%LPC*%
-G36*
-X714247Y80009D02*
-X714247Y80009D01*
-X714247Y82738D01*
-X719902Y88393D01*
-X722631Y88393D01*
-X722631Y80009D01*
-X714247Y80009D01*
-G37*
-%LPD*%
 %LPC*%
 G36*
-X180847Y80009D02*
-X180847Y80009D01*
-X180847Y82738D01*
-X186502Y88393D01*
-X189231Y88393D01*
-X189231Y80009D01*
-X180847Y80009D01*
+X202044Y540289D02*
+X202044Y540289D01*
+X199909Y541174D01*
+X198274Y542809D01*
+X197389Y544944D01*
+X197389Y547256D01*
+X198274Y549391D01*
+X199909Y551026D01*
+X202044Y551911D01*
+X204356Y551911D01*
+X206491Y551026D01*
+X208126Y549391D01*
+X209011Y547256D01*
+X209011Y544944D01*
+X208126Y542809D01*
+X206491Y541174D01*
+X204356Y540289D01*
+X202044Y540289D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X155447Y54609D02*
-X155447Y54609D01*
-X155447Y57338D01*
-X161102Y62993D01*
-X163831Y62993D01*
-X163831Y54609D01*
-X155447Y54609D01*
+X202044Y565689D02*
+X202044Y565689D01*
+X199909Y566574D01*
+X198274Y568209D01*
+X197389Y570344D01*
+X197389Y572656D01*
+X198274Y574791D01*
+X199909Y576426D01*
+X202044Y577311D01*
+X204356Y577311D01*
+X206491Y576426D01*
+X208126Y574791D01*
+X209011Y572656D01*
+X209011Y570344D01*
+X208126Y568209D01*
+X206491Y566574D01*
+X204356Y565689D01*
+X202044Y565689D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X790447Y80009D02*
-X790447Y80009D01*
-X790447Y82738D01*
-X796102Y88393D01*
-X798831Y88393D01*
-X798831Y80009D01*
-X790447Y80009D01*
+X227885Y535177D02*
+X227885Y535177D01*
+X227238Y535350D01*
+X226659Y535685D01*
+X226186Y536158D01*
+X225851Y536737D01*
+X225678Y537384D01*
+X225678Y541021D01*
+X233564Y541021D01*
+X233681Y541036D01*
+X233681Y535177D01*
+X227885Y535177D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X191769Y69087D02*
-X191769Y69087D01*
-X191769Y77471D01*
-X200153Y77471D01*
-X200153Y74742D01*
-X194498Y69087D01*
-X191769Y69087D01*
+X238759Y535177D02*
+X238759Y535177D01*
+X238759Y541027D01*
+X238776Y541027D01*
+X238876Y541021D01*
+X246762Y541021D01*
+X246762Y537384D01*
+X246589Y536737D01*
+X246254Y536158D01*
+X245781Y535685D01*
+X245202Y535350D01*
+X244555Y535177D01*
+X238759Y535177D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X166369Y94487D02*
-X166369Y94487D01*
-X166369Y102871D01*
-X174753Y102871D01*
-X174753Y100142D01*
-X169098Y94487D01*
-X166369Y94487D01*
+X274319Y535177D02*
+X274319Y535177D01*
+X274319Y541021D01*
+X282322Y541021D01*
+X282322Y537384D01*
+X282149Y536737D01*
+X281814Y536158D01*
+X281341Y535685D01*
+X280762Y535350D01*
+X280115Y535177D01*
+X274319Y535177D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X166369Y43687D02*
-X166369Y43687D01*
-X166369Y52071D01*
-X174753Y52071D01*
-X174753Y49342D01*
-X169098Y43687D01*
-X166369Y43687D01*
+X263445Y535177D02*
+X263445Y535177D01*
+X262798Y535350D01*
+X262219Y535685D01*
+X261746Y536158D01*
+X261411Y536737D01*
+X261238Y537384D01*
+X261238Y541021D01*
+X269241Y541021D01*
+X269241Y535177D01*
+X263445Y535177D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X186502Y69087D02*
-X186502Y69087D01*
-X180847Y74742D01*
-X180847Y77471D01*
-X189231Y77471D01*
-X189231Y69087D01*
-X186502Y69087D01*
+X66039Y523239D02*
+X66039Y523239D01*
+X66039Y530559D01*
+X67400Y530116D01*
+X68825Y529390D01*
+X70119Y528450D01*
+X71250Y527319D01*
+X72190Y526025D01*
+X72916Y524600D01*
+X73359Y523239D01*
+X66039Y523239D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X161102Y94487D02*
-X161102Y94487D01*
-X155447Y100142D01*
-X155447Y102871D01*
-X163831Y102871D01*
-X163831Y94487D01*
-X161102Y94487D01*
+X66039Y548639D02*
+X66039Y548639D01*
+X66039Y555959D01*
+X67400Y555516D01*
+X68825Y554790D01*
+X70119Y553850D01*
+X71250Y552719D01*
+X72190Y551425D01*
+X72916Y550000D01*
+X73359Y548639D01*
+X66039Y548639D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X161102Y43687D02*
-X161102Y43687D01*
-X155447Y49342D01*
-X155447Y52071D01*
-X163831Y52071D01*
-X163831Y43687D01*
-X161102Y43687D01*
+X294639Y638809D02*
+X294639Y638809D01*
+X294639Y646129D01*
+X296000Y645686D01*
+X297425Y644960D01*
+X298719Y644020D01*
+X299850Y642889D01*
+X300790Y641595D01*
+X301516Y640170D01*
+X301959Y638809D01*
+X294639Y638809D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X128269Y217169D02*
-X128269Y217169D01*
-X128269Y225045D01*
-X130788Y225045D01*
-X136145Y219688D01*
-X136145Y217169D01*
-X128269Y217169D01*
+X66039Y624839D02*
+X66039Y624839D01*
+X66039Y632159D01*
+X67400Y631716D01*
+X68825Y630990D01*
+X70119Y630050D01*
+X71250Y628919D01*
+X72190Y627625D01*
+X72916Y626200D01*
+X73359Y624839D01*
+X66039Y624839D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X979169Y379729D02*
-X979169Y379729D01*
-X979169Y387605D01*
-X981688Y387605D01*
-X987045Y382248D01*
-X987045Y379729D01*
-X979169Y379729D01*
+X66039Y599439D02*
+X66039Y599439D01*
+X66039Y606759D01*
+X67400Y606316D01*
+X68825Y605590D01*
+X70119Y604650D01*
+X71250Y603519D01*
+X72190Y602225D01*
+X72916Y600800D01*
+X73359Y599439D01*
+X66039Y599439D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X128269Y166369D02*
-X128269Y166369D01*
-X128269Y174245D01*
-X130788Y174245D01*
-X136145Y168888D01*
-X136145Y166369D01*
-X128269Y166369D01*
+X66039Y574039D02*
+X66039Y574039D01*
+X66039Y581359D01*
+X67400Y580916D01*
+X68825Y580190D01*
+X70119Y579250D01*
+X71250Y578119D01*
+X72190Y576825D01*
+X72916Y575400D01*
+X73359Y574039D01*
+X66039Y574039D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X52069Y242569D02*
-X52069Y242569D01*
-X52069Y250445D01*
-X54588Y250445D01*
-X59945Y245088D01*
-X59945Y242569D01*
-X52069Y242569D01*
+X53641Y548639D02*
+X53641Y548639D01*
+X54084Y550000D01*
+X54810Y551425D01*
+X55750Y552719D01*
+X56881Y553850D01*
+X58175Y554790D01*
+X59600Y555516D01*
+X60961Y555959D01*
+X60961Y548639D01*
+X53641Y548639D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X585469Y204469D02*
-X585469Y204469D01*
-X585469Y212345D01*
-X587988Y212345D01*
-X593345Y206988D01*
-X593345Y204469D01*
-X585469Y204469D01*
+X66039Y568961D02*
+X66039Y568961D01*
+X73359Y568961D01*
+X72916Y567600D01*
+X72190Y566175D01*
+X71250Y564881D01*
+X70119Y563750D01*
+X68825Y562810D01*
+X67400Y562084D01*
+X66039Y561641D01*
+X66039Y568961D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X52069Y293369D02*
-X52069Y293369D01*
-X52069Y301245D01*
-X54588Y301245D01*
-X59945Y295888D01*
-X59945Y293369D01*
-X52069Y293369D01*
+X53641Y624839D02*
+X53641Y624839D01*
+X54084Y626200D01*
+X54810Y627625D01*
+X55750Y628919D01*
+X56881Y630050D01*
+X58175Y630990D01*
+X59600Y631716D01*
+X60961Y632159D01*
+X60961Y624839D01*
+X53641Y624839D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X128269Y191769D02*
-X128269Y191769D01*
-X128269Y199645D01*
-X130788Y199645D01*
-X136145Y194288D01*
-X136145Y191769D01*
-X128269Y191769D01*
+X53641Y574039D02*
+X53641Y574039D01*
+X54084Y575400D01*
+X54810Y576825D01*
+X55750Y578119D01*
+X56881Y579250D01*
+X58175Y580190D01*
+X59600Y580916D01*
+X60961Y581359D01*
+X60961Y574039D01*
+X53641Y574039D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X280669Y356869D02*
-X280669Y356869D01*
-X280669Y364745D01*
-X283188Y364745D01*
-X288545Y359388D01*
-X288545Y356869D01*
-X280669Y356869D01*
+X66039Y594361D02*
+X66039Y594361D01*
+X73359Y594361D01*
+X72916Y593000D01*
+X72190Y591575D01*
+X71250Y590281D01*
+X70119Y589150D01*
+X68825Y588210D01*
+X67400Y587484D01*
+X66039Y587041D01*
+X66039Y594361D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X52069Y267969D02*
-X52069Y267969D01*
-X52069Y275845D01*
-X54588Y275845D01*
-X59945Y270488D01*
-X59945Y267969D01*
-X52069Y267969D01*
+X53641Y599439D02*
+X53641Y599439D01*
+X54084Y600800D01*
+X54810Y602225D01*
+X55750Y603519D01*
+X56881Y604650D01*
+X58175Y605590D01*
+X59600Y606316D01*
+X60961Y606759D01*
+X60961Y599439D01*
+X53641Y599439D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X979169Y102869D02*
-X979169Y102869D01*
-X979169Y110745D01*
-X981688Y110745D01*
-X987045Y105388D01*
-X987045Y102869D01*
-X979169Y102869D01*
+X66039Y619761D02*
+X66039Y619761D01*
+X73359Y619761D01*
+X72916Y618400D01*
+X72190Y616975D01*
+X71250Y615681D01*
+X70119Y614550D01*
+X68825Y613610D01*
+X67400Y612884D01*
+X66039Y612441D01*
+X66039Y619761D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X585469Y331469D02*
-X585469Y331469D01*
-X585469Y339345D01*
-X587988Y339345D01*
-X593345Y333988D01*
-X593345Y331469D01*
-X585469Y331469D01*
+X66039Y518161D02*
+X66039Y518161D01*
+X73359Y518161D01*
+X72916Y516800D01*
+X72190Y515375D01*
+X71250Y514081D01*
+X70119Y512950D01*
+X68825Y512010D01*
+X67400Y511284D01*
+X66039Y510841D01*
+X66039Y518161D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X968755Y102869D02*
-X968755Y102869D01*
-X968755Y105388D01*
-X974112Y110745D01*
-X976631Y110745D01*
-X976631Y102869D01*
-X968755Y102869D01*
+X53641Y523239D02*
+X53641Y523239D01*
+X54084Y524600D01*
+X54810Y526025D01*
+X55750Y527319D01*
+X56881Y528450D01*
+X58175Y529390D01*
+X59600Y530116D01*
+X60961Y530559D01*
+X60961Y523239D01*
+X53641Y523239D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X41655Y293369D02*
-X41655Y293369D01*
-X41655Y295888D01*
-X47012Y301245D01*
-X49531Y301245D01*
-X49531Y293369D01*
-X41655Y293369D01*
+X66039Y543561D02*
+X66039Y543561D01*
+X73359Y543561D01*
+X72916Y542200D01*
+X72190Y540775D01*
+X71250Y539481D01*
+X70119Y538350D01*
+X68825Y537410D01*
+X67400Y536684D01*
+X66039Y536241D01*
+X66039Y543561D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X41655Y242569D02*
-X41655Y242569D01*
-X41655Y245088D01*
-X47012Y250445D01*
-X49531Y250445D01*
-X49531Y242569D01*
-X41655Y242569D01*
+X282241Y638809D02*
+X282241Y638809D01*
+X282684Y640170D01*
+X283410Y641595D01*
+X284350Y642889D01*
+X285481Y644020D01*
+X286775Y644960D01*
+X288200Y645686D01*
+X289561Y646129D01*
+X289561Y638809D01*
+X282241Y638809D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X41655Y267969D02*
-X41655Y267969D01*
-X41655Y270488D01*
-X47012Y275845D01*
-X49531Y275845D01*
-X49531Y267969D01*
-X41655Y267969D01*
+X294639Y633731D02*
+X294639Y633731D01*
+X301959Y633731D01*
+X301516Y632370D01*
+X300790Y630945D01*
+X299850Y629651D01*
+X298719Y628520D01*
+X297425Y627580D01*
+X296000Y626854D01*
+X294639Y626411D01*
+X294639Y633731D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X575055Y331469D02*
-X575055Y331469D01*
-X575055Y333988D01*
-X580412Y339345D01*
-X582931Y339345D01*
-X582931Y331469D01*
-X575055Y331469D01*
+X396239Y633731D02*
+X396239Y633731D01*
+X403559Y633731D01*
+X403116Y632370D01*
+X402390Y630945D01*
+X401450Y629651D01*
+X400319Y628520D01*
+X399025Y627580D01*
+X397600Y626854D01*
+X396239Y626411D01*
+X396239Y633731D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X52069Y257555D02*
-X52069Y257555D01*
-X52069Y265431D01*
-X59945Y265431D01*
-X59945Y262912D01*
-X54588Y257555D01*
-X52069Y257555D01*
+X59600Y587484D02*
+X59600Y587484D01*
+X58175Y588210D01*
+X56881Y589150D01*
+X55750Y590281D01*
+X54810Y591575D01*
+X54084Y593000D01*
+X53641Y594361D01*
+X60961Y594361D01*
+X60961Y587041D01*
+X59600Y587484D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X128269Y155955D02*
-X128269Y155955D01*
-X128269Y163831D01*
-X136145Y163831D01*
-X136145Y161312D01*
-X130788Y155955D01*
-X128269Y155955D01*
+X59600Y511284D02*
+X59600Y511284D01*
+X58175Y512010D01*
+X56881Y512950D01*
+X55750Y514081D01*
+X54810Y515375D01*
+X54084Y516800D01*
+X53641Y518161D01*
+X60961Y518161D01*
+X60961Y510841D01*
+X59600Y511284D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X117855Y191769D02*
-X117855Y191769D01*
-X117855Y194288D01*
-X123212Y199645D01*
-X125731Y199645D01*
-X125731Y191769D01*
-X117855Y191769D01*
+X59600Y536684D02*
+X59600Y536684D01*
+X58175Y537410D01*
+X56881Y538350D01*
+X55750Y539481D01*
+X54810Y540775D01*
+X54084Y542200D01*
+X53641Y543561D01*
+X60961Y543561D01*
+X60961Y536241D01*
+X59600Y536684D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X280669Y346455D02*
-X280669Y346455D01*
-X280669Y354331D01*
-X288545Y354331D01*
-X288545Y351812D01*
-X283188Y346455D01*
-X280669Y346455D01*
+X59600Y612884D02*
+X59600Y612884D01*
+X58175Y613610D01*
+X56881Y614550D01*
+X55750Y615681D01*
+X54810Y616975D01*
+X54084Y618400D01*
+X53641Y619761D01*
+X60961Y619761D01*
+X60961Y612441D01*
+X59600Y612884D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X575055Y204469D02*
-X575055Y204469D01*
-X575055Y206988D01*
-X580412Y212345D01*
-X582931Y212345D01*
-X582931Y204469D01*
-X575055Y204469D01*
+X288200Y626854D02*
+X288200Y626854D01*
+X286775Y627580D01*
+X285481Y628520D01*
+X284350Y629651D01*
+X283410Y630945D01*
+X282684Y632370D01*
+X282241Y633731D01*
+X289561Y633731D01*
+X289561Y626411D01*
+X288200Y626854D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X117855Y166369D02*
-X117855Y166369D01*
-X117855Y168888D01*
-X123212Y174245D01*
-X125731Y174245D01*
-X125731Y166369D01*
-X117855Y166369D01*
+X59600Y562084D02*
+X59600Y562084D01*
+X58175Y562810D01*
+X56881Y563750D01*
+X55750Y564881D01*
+X54810Y566175D01*
+X54084Y567600D01*
+X53641Y568961D01*
+X60961Y568961D01*
+X60961Y561641D01*
+X59600Y562084D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X356869Y359155D02*
-X356869Y359155D01*
-X356869Y367031D01*
-X364745Y367031D01*
-X364745Y364512D01*
-X359388Y359155D01*
-X356869Y359155D01*
+X878799Y65999D02*
+X878799Y65999D01*
+X878799Y73287D01*
+X880170Y72842D01*
+X881583Y72122D01*
+X882867Y71189D01*
+X883989Y70067D01*
+X884922Y68783D01*
+X885642Y67370D01*
+X886087Y65999D01*
+X878799Y65999D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X585469Y194055D02*
-X585469Y194055D01*
-X585469Y201931D01*
-X593345Y201931D01*
-X593345Y199412D01*
-X587988Y194055D01*
-X585469Y194055D01*
+X853399Y65999D02*
+X853399Y65999D01*
+X853399Y73287D01*
+X854770Y72842D01*
+X856183Y72122D01*
+X857467Y71189D01*
+X858589Y70067D01*
+X859522Y68783D01*
+X860242Y67370D01*
+X860687Y65999D01*
+X853399Y65999D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X433069Y359155D02*
-X433069Y359155D01*
-X433069Y367031D01*
-X440945Y367031D01*
-X440945Y364512D01*
-X435588Y359155D01*
-X433069Y359155D01*
+X827999Y65999D02*
+X827999Y65999D01*
+X827999Y73287D01*
+X829370Y72842D01*
+X830783Y72122D01*
+X832067Y71189D01*
+X833189Y70067D01*
+X834122Y68783D01*
+X834842Y67370D01*
+X835287Y65999D01*
+X827999Y65999D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X979169Y369315D02*
-X979169Y369315D01*
-X979169Y377191D01*
-X987045Y377191D01*
-X987045Y374672D01*
-X981688Y369315D01*
-X979169Y369315D01*
+X802599Y65999D02*
+X802599Y65999D01*
+X802599Y73287D01*
+X803970Y72842D01*
+X805383Y72122D01*
+X806667Y71189D01*
+X807789Y70067D01*
+X808722Y68783D01*
+X809442Y67370D01*
+X809887Y65999D01*
+X802599Y65999D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X52069Y282955D02*
-X52069Y282955D01*
-X52069Y290831D01*
-X59945Y290831D01*
-X59945Y288312D01*
-X54588Y282955D01*
-X52069Y282955D01*
+X802599Y61001D02*
+X802599Y61001D01*
+X809887Y61001D01*
+X809442Y59630D01*
+X808722Y58217D01*
+X807789Y56933D01*
+X806667Y55811D01*
+X805383Y54878D01*
+X803970Y54158D01*
+X802599Y53713D01*
+X802599Y61001D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X968755Y379729D02*
-X968755Y379729D01*
-X968755Y382248D01*
-X974112Y387605D01*
-X976631Y387605D01*
-X976631Y379729D01*
-X968755Y379729D01*
+X878799Y61001D02*
+X878799Y61001D01*
+X886087Y61001D01*
+X885642Y59630D01*
+X884922Y58217D01*
+X883989Y56933D01*
+X882867Y55811D01*
+X881583Y54878D01*
+X880170Y54158D01*
+X878799Y53713D01*
+X878799Y61001D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X128269Y206755D02*
-X128269Y206755D01*
-X128269Y214631D01*
-X136145Y214631D01*
-X136145Y212112D01*
-X130788Y206755D01*
-X128269Y206755D01*
+X853399Y61001D02*
+X853399Y61001D01*
+X860687Y61001D01*
+X860242Y59630D01*
+X859522Y58217D01*
+X858589Y56933D01*
+X857467Y55811D01*
+X856183Y54878D01*
+X854770Y54158D01*
+X853399Y53713D01*
+X853399Y61001D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X117855Y217169D02*
-X117855Y217169D01*
-X117855Y219688D01*
-X123212Y225045D01*
-X125731Y225045D01*
-X125731Y217169D01*
-X117855Y217169D01*
+X827999Y61001D02*
+X827999Y61001D01*
+X835287Y61001D01*
+X834842Y59630D01*
+X834122Y58217D01*
+X833189Y56933D01*
+X832067Y55811D01*
+X830783Y54878D01*
+X829370Y54158D01*
+X827999Y53713D01*
+X827999Y61001D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X128269Y181355D02*
-X128269Y181355D01*
-X128269Y189231D01*
-X136145Y189231D01*
-X136145Y186712D01*
-X130788Y181355D01*
-X128269Y181355D01*
+X815713Y65999D02*
+X815713Y65999D01*
+X816158Y67370D01*
+X816878Y68783D01*
+X817811Y70067D01*
+X818933Y71189D01*
+X820217Y72122D01*
+X821630Y72842D01*
+X823001Y73287D01*
+X823001Y65999D01*
+X815713Y65999D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X979169Y92455D02*
-X979169Y92455D01*
-X979169Y100331D01*
-X987045Y100331D01*
-X987045Y97812D01*
-X981688Y92455D01*
-X979169Y92455D01*
+X841113Y65999D02*
+X841113Y65999D01*
+X841558Y67370D01*
+X842278Y68783D01*
+X843211Y70067D01*
+X844333Y71189D01*
+X845617Y72122D01*
+X847030Y72842D01*
+X848401Y73287D01*
+X848401Y65999D01*
+X841113Y65999D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X52069Y232155D02*
-X52069Y232155D01*
-X52069Y240031D01*
-X59945Y240031D01*
-X59945Y237512D01*
-X54588Y232155D01*
-X52069Y232155D01*
+X866513Y65999D02*
+X866513Y65999D01*
+X866958Y67370D01*
+X867678Y68783D01*
+X868611Y70067D01*
+X869733Y71189D01*
+X871017Y72122D01*
+X872430Y72842D01*
+X873801Y73287D01*
+X873801Y65999D01*
+X866513Y65999D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X585469Y321055D02*
-X585469Y321055D01*
-X585469Y328931D01*
-X593345Y328931D01*
-X593345Y326412D01*
-X587988Y321055D01*
-X585469Y321055D01*
+X821630Y54158D02*
+X821630Y54158D01*
+X820217Y54878D01*
+X818933Y55811D01*
+X817811Y56933D01*
+X816878Y58217D01*
+X816158Y59630D01*
+X815713Y61001D01*
+X823001Y61001D01*
+X823001Y53713D01*
+X821630Y54158D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X270255Y356869D02*
-X270255Y356869D01*
-X270255Y359388D01*
-X275612Y364745D01*
-X278131Y364745D01*
-X278131Y356869D01*
-X270255Y356869D01*
+X872430Y54158D02*
+X872430Y54158D01*
+X871017Y54878D01*
+X869733Y55811D01*
+X868611Y56933D01*
+X867678Y58217D01*
+X866958Y59630D01*
+X866513Y61001D01*
+X873801Y61001D01*
+X873801Y53713D01*
+X872430Y54158D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X275612Y346455D02*
-X275612Y346455D01*
-X270255Y351812D01*
-X270255Y354331D01*
-X278131Y354331D01*
-X278131Y346455D01*
-X275612Y346455D01*
+X847030Y54158D02*
+X847030Y54158D01*
+X845617Y54878D01*
+X844333Y55811D01*
+X843211Y56933D01*
+X842278Y58217D01*
+X841558Y59630D01*
+X841113Y61001D01*
+X848401Y61001D01*
+X848401Y53713D01*
+X847030Y54158D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X47012Y232155D02*
-X47012Y232155D01*
-X41655Y237512D01*
-X41655Y240031D01*
-X49531Y240031D01*
-X49531Y232155D01*
-X47012Y232155D01*
+X294131Y408431D02*
+X294131Y408431D01*
+X294131Y415337D01*
+X294241Y415320D01*
+X295610Y414875D01*
+X296893Y414221D01*
+X298057Y413375D01*
+X299075Y412357D01*
+X299921Y411193D01*
+X300575Y409910D01*
+X301020Y408541D01*
+X301037Y408431D01*
+X294131Y408431D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X428012Y359155D02*
-X428012Y359155D01*
-X422655Y364512D01*
-X422655Y367031D01*
-X430531Y367031D01*
-X430531Y359155D01*
-X428012Y359155D01*
+X621791Y459231D02*
+X621791Y459231D01*
+X621791Y466137D01*
+X621901Y466120D01*
+X623270Y465675D01*
+X624553Y465021D01*
+X625717Y464175D01*
+X626735Y463157D01*
+X627581Y461993D01*
+X628235Y460710D01*
+X628680Y459341D01*
+X628697Y459231D01*
+X621791Y459231D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X123212Y155955D02*
-X123212Y155955D01*
-X117855Y161312D01*
-X117855Y163831D01*
-X125731Y163831D01*
-X125731Y155955D01*
-X123212Y155955D01*
+X294131Y459231D02*
+X294131Y459231D01*
+X294131Y466137D01*
+X294241Y466120D01*
+X295610Y465675D01*
+X296893Y465021D01*
+X298057Y464175D01*
+X299075Y463157D01*
+X299921Y461993D01*
+X300575Y460710D01*
+X301020Y459341D01*
+X301037Y459231D01*
+X294131Y459231D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X974112Y92455D02*
-X974112Y92455D01*
-X968755Y97812D01*
-X968755Y100331D01*
-X976631Y100331D01*
-X976631Y92455D01*
-X974112Y92455D01*
+X586231Y14731D02*
+X586231Y14731D01*
+X586231Y21637D01*
+X586341Y21620D01*
+X587710Y21175D01*
+X588993Y20521D01*
+X590157Y19675D01*
+X591175Y18657D01*
+X592021Y17493D01*
+X592675Y16210D01*
+X593120Y14841D01*
+X593137Y14731D01*
+X586231Y14731D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X47012Y282955D02*
-X47012Y282955D01*
-X41655Y288312D01*
-X41655Y290831D01*
-X49531Y290831D01*
-X49531Y282955D01*
-X47012Y282955D01*
+X129031Y624331D02*
+X129031Y624331D01*
+X129031Y631237D01*
+X129141Y631220D01*
+X130510Y630775D01*
+X131793Y630121D01*
+X132957Y629275D01*
+X133975Y628257D01*
+X134821Y627093D01*
+X135475Y625810D01*
+X135920Y624441D01*
+X135937Y624331D01*
+X129031Y624331D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X974112Y369315D02*
-X974112Y369315D01*
-X968755Y374672D01*
-X968755Y377191D01*
-X976631Y377191D01*
-X976631Y369315D01*
-X974112Y369315D01*
+X484631Y243331D02*
+X484631Y243331D01*
+X484631Y250237D01*
+X484741Y250220D01*
+X486110Y249775D01*
+X487393Y249121D01*
+X488557Y248275D01*
+X489575Y247257D01*
+X490421Y246093D01*
+X491075Y244810D01*
+X491520Y243441D01*
+X491537Y243331D01*
+X484631Y243331D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X123212Y181355D02*
-X123212Y181355D01*
-X117855Y186712D01*
-X117855Y189231D01*
-X125731Y189231D01*
-X125731Y181355D01*
-X123212Y181355D01*
+X484631Y344931D02*
+X484631Y344931D01*
+X484631Y351837D01*
+X484741Y351820D01*
+X486110Y351375D01*
+X487393Y350721D01*
+X488557Y349875D01*
+X489575Y348857D01*
+X490421Y347693D01*
+X491075Y346410D01*
+X491520Y345041D01*
+X491537Y344931D01*
+X484631Y344931D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X47012Y257555D02*
-X47012Y257555D01*
-X41655Y262912D01*
-X41655Y265431D01*
-X49531Y265431D01*
-X49531Y257555D01*
-X47012Y257555D01*
+X329691Y560831D02*
+X329691Y560831D01*
+X329691Y567737D01*
+X329801Y567720D01*
+X331170Y567275D01*
+X332453Y566621D01*
+X333617Y565775D01*
+X334635Y564757D01*
+X335481Y563593D01*
+X336135Y562310D01*
+X336580Y560941D01*
+X336597Y560831D01*
+X329691Y560831D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X580412Y194055D02*
-X580412Y194055D01*
-X575055Y199412D01*
-X575055Y201931D01*
-X582931Y201931D01*
-X582931Y194055D01*
-X580412Y194055D01*
+X294131Y433831D02*
+X294131Y433831D01*
+X294131Y440737D01*
+X294241Y440720D01*
+X295610Y440275D01*
+X296893Y439621D01*
+X298057Y438775D01*
+X299075Y437757D01*
+X299921Y436593D01*
+X300575Y435310D01*
+X301020Y433941D01*
+X301037Y433831D01*
+X294131Y433831D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X580412Y321055D02*
-X580412Y321055D01*
-X575055Y326412D01*
-X575055Y328931D01*
-X582931Y328931D01*
-X582931Y321055D01*
-X580412Y321055D01*
+X294131Y455169D02*
+X294131Y455169D01*
+X301037Y455169D01*
+X301020Y455059D01*
+X300575Y453690D01*
+X299921Y452407D01*
+X299075Y451243D01*
+X298057Y450225D01*
+X296893Y449379D01*
+X295610Y448725D01*
+X294241Y448280D01*
+X294131Y448263D01*
+X294131Y455169D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X123212Y206755D02*
-X123212Y206755D01*
-X117855Y212112D01*
-X117855Y214631D01*
-X125731Y214631D01*
-X125731Y206755D01*
-X123212Y206755D01*
+X294131Y429769D02*
+X294131Y429769D01*
+X301037Y429769D01*
+X301020Y429659D01*
+X300575Y428290D01*
+X299921Y427007D01*
+X299075Y425843D01*
+X298057Y424825D01*
+X296893Y423979D01*
+X295610Y423325D01*
+X294241Y422880D01*
+X294131Y422863D01*
+X294131Y429769D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X351812Y359155D02*
-X351812Y359155D01*
-X346455Y364512D01*
-X346455Y367031D01*
-X354331Y367031D01*
-X354331Y359155D01*
-X351812Y359155D01*
+X610823Y459231D02*
+X610823Y459231D01*
+X610840Y459341D01*
+X611285Y460710D01*
+X611939Y461993D01*
+X612785Y463157D01*
+X613803Y464175D01*
+X614967Y465021D01*
+X616250Y465675D01*
+X617619Y466120D01*
+X617729Y466137D01*
+X617729Y459231D01*
+X610823Y459231D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X153669Y280669D02*
-X153669Y280669D01*
-X153669Y288471D01*
-X155067Y288193D01*
-X156732Y287504D01*
-X158229Y286503D01*
-X159503Y285229D01*
-X160504Y283732D01*
-X161193Y282067D01*
-X161471Y280669D01*
-X153669Y280669D01*
+X283163Y459231D02*
+X283163Y459231D01*
+X283180Y459341D01*
+X283625Y460710D01*
+X284279Y461993D01*
+X285125Y463157D01*
+X286143Y464175D01*
+X287307Y465021D01*
+X288590Y465675D01*
+X289959Y466120D01*
+X290069Y466137D01*
+X290069Y459231D01*
+X283163Y459231D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X153669Y278131D02*
-X153669Y278131D01*
-X161471Y278131D01*
-X161193Y276733D01*
-X160504Y275068D01*
-X159503Y273571D01*
-X158229Y272297D01*
-X156732Y271296D01*
-X155067Y270607D01*
-X153669Y270329D01*
-X153669Y278131D01*
+X283163Y433831D02*
+X283163Y433831D01*
+X283180Y433941D01*
+X283625Y435310D01*
+X284279Y436593D01*
+X285125Y437757D01*
+X286143Y438775D01*
+X287307Y439621D01*
+X288590Y440275D01*
+X289959Y440720D01*
+X290069Y440737D01*
+X290069Y433831D01*
+X283163Y433831D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X143329Y280669D02*
-X143329Y280669D01*
-X143607Y282067D01*
-X144296Y283732D01*
-X145297Y285229D01*
-X146571Y286503D01*
-X148068Y287504D01*
-X149733Y288193D01*
-X151131Y288471D01*
-X151131Y280669D01*
-X143329Y280669D01*
+X484631Y239269D02*
+X484631Y239269D01*
+X491537Y239269D01*
+X491520Y239159D01*
+X491075Y237790D01*
+X490421Y236507D01*
+X489575Y235343D01*
+X488557Y234325D01*
+X487393Y233479D01*
+X486110Y232825D01*
+X484741Y232380D01*
+X484631Y232363D01*
+X484631Y239269D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X149733Y270607D02*
-X149733Y270607D01*
-X148068Y271296D01*
-X146571Y272297D01*
-X145297Y273571D01*
-X144296Y275068D01*
-X143607Y276733D01*
-X143329Y278131D01*
-X151131Y278131D01*
-X151131Y270329D01*
-X149733Y270607D01*
+X129031Y620269D02*
+X129031Y620269D01*
+X135937Y620269D01*
+X135920Y620159D01*
+X135475Y618790D01*
+X134821Y617507D01*
+X133975Y616343D01*
+X132957Y615325D01*
+X131793Y614479D01*
+X130510Y613825D01*
+X129141Y613380D01*
+X129031Y613363D01*
+X129031Y620269D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X126999Y165099D02*
-X126999Y165099D01*
-X126999Y165101D01*
-X127001Y165101D01*
-X127001Y165099D01*
-X126999Y165099D01*
+X118063Y624331D02*
+X118063Y624331D01*
+X118080Y624441D01*
+X118525Y625810D01*
+X119179Y627093D01*
+X120025Y628257D01*
+X121043Y629275D01*
+X122207Y630121D01*
+X123490Y630775D01*
+X124859Y631220D01*
+X124969Y631237D01*
+X124969Y624331D01*
+X118063Y624331D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X584199Y203199D02*
-X584199Y203199D01*
-X584199Y203201D01*
-X584201Y203201D01*
-X584201Y203199D01*
-X584199Y203199D01*
+X318723Y560831D02*
+X318723Y560831D01*
+X318740Y560941D01*
+X319185Y562310D01*
+X319839Y563593D01*
+X320685Y564757D01*
+X321703Y565775D01*
+X322867Y566621D01*
+X324150Y567275D01*
+X325519Y567720D01*
+X325629Y567737D01*
+X325629Y560831D01*
+X318723Y560831D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X952499Y279399D02*
-X952499Y279399D01*
-X952499Y279401D01*
-X952501Y279401D01*
-X952501Y279399D01*
-X952499Y279399D01*
+X329691Y556769D02*
+X329691Y556769D01*
+X336597Y556769D01*
+X336580Y556659D01*
+X336135Y555290D01*
+X335481Y554007D01*
+X334635Y552843D01*
+X333617Y551825D01*
+X332453Y550979D01*
+X331170Y550325D01*
+X329801Y549880D01*
+X329691Y549863D01*
+X329691Y556769D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X152399Y279399D02*
-X152399Y279399D01*
-X152399Y279401D01*
-X152401Y279401D01*
-X152401Y279399D01*
-X152399Y279399D01*
+X294131Y404369D02*
+X294131Y404369D01*
+X301037Y404369D01*
+X301020Y404259D01*
+X300575Y402890D01*
+X299921Y401607D01*
+X299075Y400443D01*
+X298057Y399425D01*
+X296893Y398579D01*
+X295610Y397925D01*
+X294241Y397480D01*
+X294131Y397463D01*
+X294131Y404369D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X952499Y152399D02*
-X952499Y152399D01*
-X952499Y152401D01*
-X952501Y152401D01*
-X952501Y152399D01*
-X952499Y152399D01*
+X575263Y14731D02*
+X575263Y14731D01*
+X575280Y14841D01*
+X575725Y16210D01*
+X576379Y17493D01*
+X577225Y18657D01*
+X578243Y19675D01*
+X579407Y20521D01*
+X580690Y21175D01*
+X582059Y21620D01*
+X582169Y21637D01*
+X582169Y14731D01*
+X575263Y14731D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X50799Y292099D02*
-X50799Y292099D01*
-X50799Y292101D01*
-X50801Y292101D01*
-X50801Y292099D01*
-X50799Y292099D01*
+X473663Y344931D02*
+X473663Y344931D01*
+X473680Y345041D01*
+X474125Y346410D01*
+X474779Y347693D01*
+X475625Y348857D01*
+X476643Y349875D01*
+X477807Y350721D01*
+X479090Y351375D01*
+X480459Y351820D01*
+X480569Y351837D01*
+X480569Y344931D01*
+X473663Y344931D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X546099Y203199D02*
-X546099Y203199D01*
-X546099Y203201D01*
-X546101Y203201D01*
-X546101Y203199D01*
-X546099Y203199D01*
+X283163Y408431D02*
+X283163Y408431D01*
+X283180Y408541D01*
+X283625Y409910D01*
+X284279Y411193D01*
+X285125Y412357D01*
+X286143Y413375D01*
+X287307Y414221D01*
+X288590Y414875D01*
+X289959Y415320D01*
+X290069Y415337D01*
+X290069Y408431D01*
+X283163Y408431D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X165099Y104139D02*
-X165099Y104139D01*
-X165099Y104141D01*
-X165101Y104141D01*
-X165101Y104139D01*
-X165099Y104139D01*
+X473663Y243331D02*
+X473663Y243331D01*
+X473680Y243441D01*
+X474125Y244810D01*
+X474779Y246093D01*
+X475625Y247257D01*
+X476643Y248275D01*
+X477807Y249121D01*
+X479090Y249775D01*
+X480459Y250220D01*
+X480569Y250237D01*
+X480569Y243331D01*
+X473663Y243331D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X977899Y101599D02*
-X977899Y101599D01*
-X977899Y101601D01*
-X977901Y101601D01*
-X977901Y101599D01*
-X977899Y101599D01*
+X289959Y448280D02*
+X289959Y448280D01*
+X288590Y448725D01*
+X287307Y449379D01*
+X286143Y450225D01*
+X285125Y451243D01*
+X284279Y452407D01*
+X283625Y453690D01*
+X283180Y455059D01*
+X283163Y455169D01*
+X290069Y455169D01*
+X290069Y448263D01*
+X289959Y448280D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X584199Y330199D02*
-X584199Y330199D01*
-X584199Y330201D01*
-X584201Y330201D01*
-X584201Y330199D01*
-X584199Y330199D01*
+X480459Y232380D02*
+X480459Y232380D01*
+X479090Y232825D01*
+X477807Y233479D01*
+X476643Y234325D01*
+X475625Y235343D01*
+X474779Y236507D01*
+X474125Y237790D01*
+X473680Y239159D01*
+X473663Y239269D01*
+X480569Y239269D01*
+X480569Y232363D01*
+X480459Y232380D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X126999Y215899D02*
-X126999Y215899D01*
-X126999Y215901D01*
-X127001Y215901D01*
-X127001Y215899D01*
-X126999Y215899D01*
+X124859Y613380D02*
+X124859Y613380D01*
+X123490Y613825D01*
+X122207Y614479D01*
+X121043Y615325D01*
+X120025Y616343D01*
+X119179Y617507D01*
+X118525Y618790D01*
+X118080Y620159D01*
+X118063Y620269D01*
+X124969Y620269D01*
+X124969Y613363D01*
+X124859Y613380D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X50799Y266699D02*
-X50799Y266699D01*
-X50799Y266701D01*
-X50801Y266701D01*
-X50801Y266699D01*
-X50799Y266699D01*
+X289959Y397480D02*
+X289959Y397480D01*
+X288590Y397925D01*
+X287307Y398579D01*
+X286143Y399425D01*
+X285125Y400443D01*
+X284279Y401607D01*
+X283625Y402890D01*
+X283180Y404259D01*
+X283163Y404369D01*
+X290069Y404369D01*
+X290069Y397463D01*
+X289959Y397480D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X126999Y190499D02*
-X126999Y190499D01*
-X126999Y190501D01*
-X127001Y190501D01*
-X127001Y190499D01*
-X126999Y190499D01*
+X289959Y422880D02*
+X289959Y422880D01*
+X288590Y423325D01*
+X287307Y423979D01*
+X286143Y424825D01*
+X285125Y425843D01*
+X284279Y427007D01*
+X283625Y428290D01*
+X283180Y429659D01*
+X283163Y429769D01*
+X290069Y429769D01*
+X290069Y422863D01*
+X289959Y422880D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X50799Y241299D02*
-X50799Y241299D01*
-X50799Y241301D01*
-X50801Y241301D01*
-X50801Y241299D01*
-X50799Y241299D01*
+X325519Y549880D02*
+X325519Y549880D01*
+X324150Y550325D01*
+X322867Y550979D01*
+X321703Y551825D01*
+X320685Y552843D01*
+X319839Y554007D01*
+X319185Y555290D01*
+X318740Y556659D01*
+X318723Y556769D01*
+X325629Y556769D01*
+X325629Y549863D01*
+X325519Y549880D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X546099Y304799D02*
-X546099Y304799D01*
-X546099Y304801D01*
-X546101Y304801D01*
-X546101Y304799D01*
-X546099Y304799D01*
+X63499Y571499D02*
+X63499Y571499D01*
+X63499Y571501D01*
+X63501Y571501D01*
+X63501Y571499D01*
+X63499Y571499D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X190499Y78739D02*
-X190499Y78739D01*
-X190499Y78741D01*
-X190501Y78741D01*
-X190501Y78739D01*
-X190499Y78739D01*
+X63499Y622299D02*
+X63499Y622299D01*
+X63499Y622301D01*
+X63501Y622301D01*
+X63501Y622299D01*
+X63499Y622299D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X279399Y355599D02*
-X279399Y355599D01*
-X279399Y355601D01*
-X279401Y355601D01*
-X279401Y355599D01*
-X279399Y355599D01*
+X63499Y520699D02*
+X63499Y520699D01*
+X63499Y520701D01*
+X63501Y520701D01*
+X63501Y520699D01*
+X63499Y520699D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X165099Y53339D02*
-X165099Y53339D01*
-X165099Y53341D01*
-X165101Y53341D01*
-X165101Y53339D01*
-X165099Y53339D01*
+X63499Y546099D02*
+X63499Y546099D01*
+X63499Y546101D01*
+X63501Y546101D01*
+X63501Y546099D01*
+X63499Y546099D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X977899Y378459D02*
-X977899Y378459D01*
-X977899Y378461D01*
-X977901Y378461D01*
-X977901Y378459D01*
-X977899Y378459D01*
+X63499Y596899D02*
+X63499Y596899D01*
+X63499Y596901D01*
+X63501Y596901D01*
+X63501Y596899D01*
+X63499Y596899D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X25399Y165099D02*
-X25399Y165099D01*
-X25399Y165101D01*
-X25401Y165101D01*
-X25401Y165099D01*
-X25399Y165099D01*
+X292099Y636269D02*
+X292099Y636269D01*
+X292099Y636271D01*
+X292101Y636271D01*
+X292101Y636269D01*
+X292099Y636269D01*
 G37*
 %LPD*%
 D10*
-X622300Y272796D02*
-X622300Y286004D01*
-X647700Y286004D02*
-X647700Y272796D01*
-X774700Y272796D02*
-X774700Y286004D01*
-X800100Y286004D02*
-X800100Y272796D01*
-X673100Y272796D02*
-X673100Y286004D01*
-X698500Y286004D02*
-X698500Y272796D01*
-X749300Y272796D02*
-X749300Y286004D01*
-X723900Y286004D02*
-X723900Y272796D01*
-X825500Y272796D02*
-X825500Y286004D01*
-X850900Y286004D02*
-X850900Y272796D01*
-X876300Y272796D02*
-X876300Y286004D01*
-X901700Y286004D02*
-X901700Y272796D01*
-X927100Y272796D02*
-X927100Y286004D01*
-X952500Y286004D02*
-X952500Y272796D01*
-X952500Y348996D02*
-X952500Y362204D01*
-X927100Y362204D02*
-X927100Y348996D01*
-X901700Y348996D02*
-X901700Y362204D01*
-X876300Y362204D02*
-X876300Y348996D01*
-X850900Y348996D02*
-X850900Y362204D01*
-X825500Y362204D02*
-X825500Y348996D01*
-X800100Y348996D02*
-X800100Y362204D01*
-X774700Y362204D02*
-X774700Y348996D01*
-X749300Y348996D02*
-X749300Y362204D01*
-X723900Y362204D02*
-X723900Y348996D01*
-X698500Y348996D02*
-X698500Y362204D01*
-X673100Y362204D02*
-X673100Y348996D01*
-X647700Y348996D02*
-X647700Y362204D01*
-X622300Y362204D02*
-X622300Y348996D01*
+X152400Y622300D03*
+X152400Y546100D03*
+X127000Y622300D03*
+X127000Y546100D03*
 D11*
-X952500Y27940D03*
+X165100Y457200D03*
+X190500Y457200D03*
+X165100Y431800D03*
+X190500Y431800D03*
+X165100Y406400D03*
+X190500Y406400D03*
+D10*
+X292100Y457200D03*
+X215900Y457200D03*
+X292100Y431800D03*
+X215900Y431800D03*
+X292100Y406400D03*
+X215900Y406400D03*
+X619760Y457200D03*
+X599440Y457200D03*
+X327660Y558800D03*
+X307340Y558800D03*
 D12*
-X901700Y53340D03*
-X876300Y53340D03*
-X850900Y53340D03*
-X825500Y53340D03*
-X800100Y53340D03*
-X774700Y53340D03*
-X749300Y53340D03*
-X723900Y53340D03*
-X698500Y53340D03*
-X673100Y53340D03*
-X647700Y53340D03*
-X622300Y53340D03*
-X596900Y53340D03*
-X571500Y53340D03*
-X546100Y53340D03*
-X520700Y53340D03*
-X495300Y53340D03*
-X469900Y53340D03*
-X444500Y53340D03*
-X419100Y53340D03*
-X393700Y53340D03*
-X368300Y53340D03*
-X342900Y53340D03*
-X317500Y53340D03*
-X292100Y53340D03*
-X266700Y53340D03*
-X241300Y53340D03*
-X215900Y53340D03*
-X190500Y53340D03*
-X165100Y53340D03*
-X139700Y53340D03*
-X114300Y53340D03*
-X901700Y104140D03*
-X876300Y104140D03*
-X850900Y104140D03*
-X825500Y104140D03*
-X800100Y104140D03*
-X774700Y104140D03*
-X749300Y104140D03*
-X723900Y104140D03*
-X698500Y104140D03*
-X673100Y104140D03*
-X647700Y104140D03*
-X622300Y104140D03*
-X596900Y104140D03*
-X571500Y104140D03*
-X546100Y104140D03*
-X520700Y104140D03*
-X495300Y104140D03*
-X469900Y104140D03*
-X444500Y104140D03*
-X419100Y104140D03*
-X393700Y104140D03*
-X368300Y104140D03*
-X342900Y104140D03*
-X317500Y104140D03*
-X292100Y104140D03*
-X266700Y104140D03*
-X241300Y104140D03*
-X215900Y104140D03*
-X190500Y104140D03*
-X165100Y104140D03*
-X139700Y104140D03*
-X114300Y104140D03*
-D11*
-X63500Y27940D03*
-D12*
-X901700Y78740D03*
-X876300Y78740D03*
-X850900Y78740D03*
-X825500Y78740D03*
-X800100Y78740D03*
-X774700Y78740D03*
-X749300Y78740D03*
-X723900Y78740D03*
-X698500Y78740D03*
-X673100Y78740D03*
-X647700Y78740D03*
-X622300Y78740D03*
-X596900Y78740D03*
-X571500Y78740D03*
-X546100Y78740D03*
-X520700Y78740D03*
-X495300Y78740D03*
-X469900Y78740D03*
-X444500Y78740D03*
-X419100Y78740D03*
-X393700Y78740D03*
-X368300Y78740D03*
-X342900Y78740D03*
-X317500Y78740D03*
-X292100Y78740D03*
-X266700Y78740D03*
-X241300Y78740D03*
-X215900Y78740D03*
-X190500Y78740D03*
-X165100Y78740D03*
-X139700Y78740D03*
-X114300Y78740D03*
-D13*
-X152400Y355600D03*
-X152400Y279400D03*
-X228600Y279400D03*
-X228600Y355600D03*
-D14*
-X50800Y165100D03*
-X101600Y165100D03*
-X50800Y190500D03*
-X101600Y190500D03*
-X50800Y215900D03*
-X101600Y215900D03*
-X50800Y241300D03*
+X393700Y661670D03*
+X393700Y636270D03*
+X368300Y661670D03*
+X368300Y636270D03*
+X342900Y661670D03*
+X342900Y636270D03*
+X317500Y661670D03*
+X317500Y636270D03*
+X292100Y661670D03*
+X292100Y636270D03*
+X88900Y520700D03*
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+X63500Y546100D03*
+X88900Y571500D03*
+X63500Y571500D03*
+X88900Y596900D03*
+X63500Y596900D03*
+X88900Y622300D03*
+X63500Y622300D03*
+D10*
+X863600Y241300D03*
+X838200Y241300D03*
+X812800Y241300D03*
+X787400Y241300D03*
+X762000Y241300D03*
+X736600Y241300D03*
+X711200Y241300D03*
+X685800Y241300D03*
+X660400Y241300D03*
+X635000Y241300D03*
+X609600Y241300D03*
+X584200Y241300D03*
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+X482600Y241300D03*
+X457200Y241300D03*
+X431800Y241300D03*
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+X558800Y12700D03*
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+X177800Y241300D03*
+X152400Y241300D03*
+X127000Y241300D03*
 X101600Y241300D03*
-X50800Y266700D03*
-X101600Y266700D03*
-X50800Y292100D03*
-X101600Y292100D03*
-D10*
-X622300Y159004D02*
-X622300Y145796D01*
-X647700Y145796D02*
-X647700Y159004D01*
-X774700Y159004D02*
-X774700Y145796D01*
-X800100Y145796D02*
-X800100Y159004D01*
-X673100Y159004D02*
-X673100Y145796D01*
-X698500Y145796D02*
-X698500Y159004D01*
-X749300Y159004D02*
-X749300Y145796D01*
-X723900Y145796D02*
-X723900Y159004D01*
-X825500Y159004D02*
-X825500Y145796D01*
-X850900Y145796D02*
-X850900Y159004D01*
-X876300Y159004D02*
-X876300Y145796D01*
-X901700Y145796D02*
-X901700Y159004D01*
-X927100Y159004D02*
-X927100Y145796D01*
-X952500Y145796D02*
-X952500Y159004D01*
-X952500Y221996D02*
-X952500Y235204D01*
-X927100Y235204D02*
-X927100Y221996D01*
-X901700Y221996D02*
-X901700Y235204D01*
-X876300Y235204D02*
-X876300Y221996D01*
-X850900Y221996D02*
-X850900Y235204D01*
-X825500Y235204D02*
-X825500Y221996D01*
-X800100Y221996D02*
-X800100Y235204D01*
-X774700Y235204D02*
-X774700Y221996D01*
-X749300Y221996D02*
-X749300Y235204D01*
-X723900Y235204D02*
-X723900Y221996D01*
-X698500Y221996D02*
-X698500Y235204D01*
-X673100Y235204D02*
-X673100Y221996D01*
-X647700Y221996D02*
-X647700Y235204D01*
-X622300Y235204D02*
-X622300Y221996D01*
-D15*
-X228600Y165100D03*
-X203200Y165100D03*
-X228600Y190500D03*
-X203200Y190500D03*
-X228600Y215900D03*
-X203200Y215900D03*
+X381000Y12700D03*
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+X330200Y12700D03*
+X304800Y12700D03*
+X279400Y12700D03*
+X254000Y12700D03*
+X228600Y12700D03*
+X203200Y12700D03*
+X177800Y12700D03*
+X152400Y12700D03*
+X127000Y12700D03*
+X101600Y12700D03*
+D13*
+X203200Y571500D03*
+X203200Y546100D03*
 D14*
-X127000Y165100D03*
-X177800Y165100D03*
-X127000Y190500D03*
-X177800Y190500D03*
-X127000Y215900D03*
-X177800Y215900D03*
+X271780Y543560D03*
+X271780Y558800D03*
+X271780Y574040D03*
+D15*
+X271780Y571500D02*
+X271780Y558800D01*
+D14*
+X236220Y574040D03*
+X236220Y558800D03*
+X236220Y543560D03*
+D15*
+X236220Y546100D02*
+X236220Y558800D01*
 D10*
-X32004Y292100D02*
-X18796Y292100D01*
-X18796Y266700D02*
-X32004Y266700D01*
-X32004Y241300D02*
-X18796Y241300D01*
-X18796Y215900D02*
-X32004Y215900D01*
-X32004Y190500D02*
-X18796Y190500D01*
-X18796Y165100D02*
-X32004Y165100D01*
+X863600Y342900D03*
+X838200Y342900D03*
+X812800Y342900D03*
+X787400Y342900D03*
+X762000Y342900D03*
+X736600Y342900D03*
+X711200Y342900D03*
+X685800Y342900D03*
+X660400Y342900D03*
+X635000Y342900D03*
+X609600Y342900D03*
+X584200Y342900D03*
+X558800Y342900D03*
+X533400Y342900D03*
+X508000Y342900D03*
+X482600Y342900D03*
+X457200Y342900D03*
+X431800Y342900D03*
+X406400Y342900D03*
+X76200Y342900D03*
+X76200Y114300D03*
+X406400Y114300D03*
+X431800Y114300D03*
+X457200Y114300D03*
+X482600Y114300D03*
+X508000Y114300D03*
+X533400Y114300D03*
+X558800Y114300D03*
+X584200Y114300D03*
+X609600Y114300D03*
+X635000Y114300D03*
+X660400Y114300D03*
+X685800Y114300D03*
+X711200Y114300D03*
+X736600Y114300D03*
+X762000Y114300D03*
+X787400Y114300D03*
+X812800Y114300D03*
+X838200Y114300D03*
+X863600Y114300D03*
+X381000Y342900D03*
+X355600Y342900D03*
+X330200Y342900D03*
+X304800Y342900D03*
+X279400Y342900D03*
+X254000Y342900D03*
+X228600Y342900D03*
+X203200Y342900D03*
+X177800Y342900D03*
+X152400Y342900D03*
+X127000Y342900D03*
+X101600Y342900D03*
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+X177800Y114300D03*
+X152400Y114300D03*
+X127000Y114300D03*
+X101600Y114300D03*
 D16*
-X584200Y228600D03*
-X584200Y177800D03*
-X584200Y203200D03*
-X584200Y355600D03*
-X584200Y304800D03*
-X584200Y330200D03*
-X279400Y381000D03*
-X279400Y330200D03*
-X279400Y355600D03*
+X876300Y38100D03*
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+X825500Y38100D03*
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+X520700Y38100D03*
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+X444500Y38100D03*
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+X114300Y38100D03*
+X88900Y38100D03*
+X876300Y88900D03*
+X850900Y88900D03*
+X825500Y88900D03*
+X800100Y88900D03*
+X774700Y88900D03*
+X749300Y88900D03*
+X723900Y88900D03*
+X698500Y88900D03*
+X673100Y88900D03*
+X647700Y88900D03*
+X622300Y88900D03*
+X596900Y88900D03*
+X571500Y88900D03*
+X546100Y88900D03*
+X520700Y88900D03*
+X495300Y88900D03*
+X469900Y88900D03*
+X444500Y88900D03*
+X419100Y88900D03*
+X393700Y88900D03*
+X368300Y88900D03*
+X342900Y88900D03*
+X317500Y88900D03*
+X292100Y88900D03*
+X266700Y88900D03*
+X241300Y88900D03*
+X215900Y88900D03*
+X190500Y88900D03*
+X165100Y88900D03*
+X139700Y88900D03*
+X114300Y88900D03*
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 M02*
diff --git a/Gerbers/copper_top.gbr b/Gerbers/copper_top.gbr
index 37a1d19..85310cd 100644
--- a/Gerbers/copper_top.gbr
+++ b/Gerbers/copper_top.gbr
@@ -12,19139 +12,42069 @@ G01*
 %ADD11R,1.500000X0.350000*%
 %ADD12R,0.350000X1.500000*%
 %ADD13C,1.320800*%
-%ADD14C,5.080000*%
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-%ADD18P,1.539592X8X112.500000*%
-%ADD19P,1.429621X8X292.500000*%
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-%ADD21P,1.649562X8X292.500000*%
-%ADD22C,0.406400*%
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+%ADD14C,1.422400*%
+%ADD15R,1.600000X1.300000*%
+%ADD16R,1.300000X1.600000*%
+%ADD17C,1.524000*%
+%ADD18C,0.908000*%
+%ADD19R,0.300000X1.000000*%
+%ADD20R,1.300000X1.500000*%
+%ADD21R,1.500000X1.300000*%
+%ADD22C,1.508000*%
+%ADD23R,0.660400X2.032000*%
+%ADD24C,0.254000*%
+%ADD25C,0.304800*%
+%ADD26C,0.812800*%
+%ADD27C,0.604800*%
+%ADD28C,0.127000*%
 
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+X841929Y69307D01*
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+X845617Y54878D01*
+X844333Y55811D01*
+X843211Y56933D01*
+X843037Y57172D01*
+X842982Y57230D01*
+X842936Y57295D01*
+X842874Y57346D01*
+X842819Y57404D01*
+X842752Y57447D01*
+X842691Y57498D01*
+X842618Y57532D01*
+X842551Y57575D01*
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+X841085Y57296D01*
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+X840984Y57173D01*
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+X840898Y57039D01*
+X840869Y56965D01*
+X840830Y56895D01*
+X840810Y56818D01*
+X840781Y56743D01*
+X840771Y56664D01*
+X840751Y56587D01*
+X840741Y56429D01*
+X840741Y56428D01*
+X840741Y56427D01*
+X840741Y56426D01*
+X840741Y42978D01*
+X840749Y42909D01*
+X840748Y42839D01*
+X840769Y42751D01*
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+X840865Y42450D01*
+X840898Y42367D01*
+X840939Y42310D01*
+X840971Y42248D01*
+X841032Y42182D01*
+X841084Y42109D01*
+X841138Y42065D01*
+X841185Y42013D01*
+X841260Y41964D01*
+X841329Y41906D01*
+X841393Y41877D01*
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+X841536Y41809D01*
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+X841686Y41758D01*
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+X841841Y41728D01*
+X841929Y41711D01*
+X841999Y41715D01*
+X842069Y41710D01*
+X842157Y41725D01*
 G37*
-%LPD*%
 %LPC*%
 G36*
-X720428Y95757D02*
-X720428Y95757D01*
-X715517Y100668D01*
-X715517Y107612D01*
-X720428Y112523D01*
-X727372Y112523D01*
-X732283Y107612D01*
-X732283Y100668D01*
-X727372Y95757D01*
-X720428Y95757D01*
+X341131Y652779D02*
+X341131Y652779D01*
+X337864Y654133D01*
+X335363Y656634D01*
+X334009Y659901D01*
+X334009Y663439D01*
+X335363Y666706D01*
+X337864Y669207D01*
+X341131Y670561D01*
+X344669Y670561D01*
+X347936Y669207D01*
+X350437Y666706D01*
+X351791Y663439D01*
+X351791Y659901D01*
+X350437Y656634D01*
+X347936Y654133D01*
+X344669Y652779D01*
+X341131Y652779D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X695028Y95757D02*
-X695028Y95757D01*
-X690117Y100668D01*
-X690117Y107612D01*
-X695028Y112523D01*
-X701972Y112523D01*
-X706883Y107612D01*
-X706883Y100668D01*
-X701972Y95757D01*
-X695028Y95757D01*
+X290331Y652779D02*
+X290331Y652779D01*
+X287064Y654133D01*
+X284563Y656634D01*
+X283209Y659901D01*
+X283209Y663439D01*
+X284563Y666706D01*
+X287064Y669207D01*
+X290331Y670561D01*
+X293869Y670561D01*
+X297136Y669207D01*
+X299637Y666706D01*
+X300991Y663439D01*
+X300991Y659901D01*
+X299637Y656634D01*
+X297136Y654133D01*
+X293869Y652779D01*
+X290331Y652779D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X669628Y95757D02*
-X669628Y95757D01*
-X664717Y100668D01*
-X664717Y107612D01*
-X669628Y112523D01*
-X676572Y112523D01*
-X681483Y107612D01*
-X681483Y100668D01*
-X676572Y95757D01*
-X669628Y95757D01*
+X315731Y652779D02*
+X315731Y652779D01*
+X312464Y654133D01*
+X309963Y656634D01*
+X308609Y659901D01*
+X308609Y663439D01*
+X309963Y666706D01*
+X312464Y669207D01*
+X315731Y670561D01*
+X319269Y670561D01*
+X322536Y669207D01*
+X325037Y666706D01*
+X326391Y663439D01*
+X326391Y659901D01*
+X325037Y656634D01*
+X322536Y654133D01*
+X319269Y652779D01*
+X315731Y652779D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X568028Y70357D02*
-X568028Y70357D01*
-X563117Y75268D01*
-X563117Y82212D01*
-X568028Y87123D01*
-X574972Y87123D01*
-X579883Y82212D01*
-X579883Y75268D01*
-X574972Y70357D01*
-X568028Y70357D01*
+X366531Y652779D02*
+X366531Y652779D01*
+X363264Y654133D01*
+X360763Y656634D01*
+X359409Y659901D01*
+X359409Y663439D01*
+X360763Y666706D01*
+X363264Y669207D01*
+X366531Y670561D01*
+X370069Y670561D01*
+X373336Y669207D01*
+X375837Y666706D01*
+X377191Y663439D01*
+X377191Y659901D01*
+X375837Y656634D01*
+X373336Y654133D01*
+X370069Y652779D01*
+X366531Y652779D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X110828Y70357D02*
-X110828Y70357D01*
-X105917Y75268D01*
-X105917Y82212D01*
-X110828Y87123D01*
-X117772Y87123D01*
-X122683Y82212D01*
-X122683Y75268D01*
-X117772Y70357D01*
-X110828Y70357D01*
+X391931Y652779D02*
+X391931Y652779D01*
+X388664Y654133D01*
+X386163Y656634D01*
+X384809Y659901D01*
+X384809Y663439D01*
+X386163Y666706D01*
+X388664Y669207D01*
+X391931Y670561D01*
+X395469Y670561D01*
+X398736Y669207D01*
+X401237Y666706D01*
+X402591Y663439D01*
+X402591Y659901D01*
+X401237Y656634D01*
+X398736Y654133D01*
+X395469Y652779D01*
+X391931Y652779D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X771228Y95757D02*
-X771228Y95757D01*
-X766317Y100668D01*
-X766317Y107612D01*
-X771228Y112523D01*
-X778172Y112523D01*
-X783083Y107612D01*
-X783083Y100668D01*
-X778172Y95757D01*
-X771228Y95757D01*
+X315731Y627379D02*
+X315731Y627379D01*
+X312464Y628733D01*
+X309963Y631234D01*
+X308609Y634501D01*
+X308609Y638039D01*
+X309963Y641306D01*
+X312464Y643807D01*
+X315731Y645161D01*
+X319269Y645161D01*
+X322536Y643807D01*
+X325037Y641306D01*
+X326391Y638039D01*
+X326391Y634501D01*
+X325037Y631234D01*
+X322536Y628733D01*
+X319269Y627379D01*
+X315731Y627379D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X136228Y70357D02*
-X136228Y70357D01*
-X131317Y75268D01*
-X131317Y82212D01*
-X136228Y87123D01*
-X143172Y87123D01*
-X148083Y82212D01*
-X148083Y75268D01*
-X143172Y70357D01*
-X136228Y70357D01*
+X366531Y627379D02*
+X366531Y627379D01*
+X363264Y628733D01*
+X360763Y631234D01*
+X359409Y634501D01*
+X359409Y638039D01*
+X360763Y641306D01*
+X363264Y643807D01*
+X366531Y645161D01*
+X370069Y645161D01*
+X373336Y643807D01*
+X375837Y641306D01*
+X377191Y638039D01*
+X377191Y634501D01*
+X375837Y631234D01*
+X373336Y628733D01*
+X370069Y627379D01*
+X366531Y627379D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X212428Y70357D02*
-X212428Y70357D01*
-X207517Y75268D01*
-X207517Y82212D01*
-X212428Y87123D01*
-X219372Y87123D01*
-X224283Y82212D01*
-X224283Y75268D01*
-X219372Y70357D01*
-X212428Y70357D01*
+X341131Y627379D02*
+X341131Y627379D01*
+X337864Y628733D01*
+X335363Y631234D01*
+X334009Y634501D01*
+X334009Y638039D01*
+X335363Y641306D01*
+X337864Y643807D01*
+X341131Y645161D01*
+X344669Y645161D01*
+X347936Y643807D01*
+X350437Y641306D01*
+X351791Y638039D01*
+X351791Y634501D01*
+X350437Y631234D01*
+X347936Y628733D01*
+X344669Y627379D01*
+X341131Y627379D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X618828Y70357D02*
-X618828Y70357D01*
-X613917Y75268D01*
-X613917Y82212D01*
-X618828Y87123D01*
-X625772Y87123D01*
-X630683Y82212D01*
-X630683Y75268D01*
-X625772Y70357D01*
-X618828Y70357D01*
+X468147Y29289D02*
+X468147Y29289D01*
+X464909Y30631D01*
+X462431Y33109D01*
+X461089Y36347D01*
+X461089Y39853D01*
+X462431Y43091D01*
+X464909Y45569D01*
+X468147Y46911D01*
+X471653Y46911D01*
+X474891Y45569D01*
+X477369Y43091D01*
+X478711Y39853D01*
+X478711Y36347D01*
+X477369Y33109D01*
+X474891Y30631D01*
+X471653Y29289D01*
+X468147Y29289D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X593428Y70357D02*
-X593428Y70357D01*
-X588517Y75268D01*
-X588517Y82212D01*
-X593428Y87123D01*
-X600372Y87123D01*
-X605283Y82212D01*
-X605283Y75268D01*
-X600372Y70357D01*
-X593428Y70357D01*
+X112547Y29289D02*
+X112547Y29289D01*
+X109309Y30631D01*
+X106831Y33109D01*
+X105489Y36347D01*
+X105489Y39853D01*
+X106831Y43091D01*
+X109309Y45569D01*
+X112547Y46911D01*
+X116053Y46911D01*
+X119291Y45569D01*
+X121769Y43091D01*
+X123111Y39853D01*
+X123111Y36347D01*
+X121769Y33109D01*
+X119291Y30631D01*
+X116053Y29289D01*
+X112547Y29289D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X237828Y70357D02*
-X237828Y70357D01*
-X232917Y75268D01*
-X232917Y82212D01*
-X237828Y87123D01*
-X244772Y87123D01*
-X249683Y82212D01*
-X249683Y75268D01*
-X244772Y70357D01*
-X237828Y70357D01*
+X188747Y29289D02*
+X188747Y29289D01*
+X185509Y30631D01*
+X183031Y33109D01*
+X181689Y36347D01*
+X181689Y39853D01*
+X183031Y43091D01*
+X185509Y45569D01*
+X188747Y46911D01*
+X192253Y46911D01*
+X195491Y45569D01*
+X197969Y43091D01*
+X199311Y39853D01*
+X199311Y36347D01*
+X197969Y33109D01*
+X195491Y30631D01*
+X192253Y29289D01*
+X188747Y29289D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X314028Y70357D02*
-X314028Y70357D01*
-X309117Y75268D01*
-X309117Y82212D01*
-X314028Y87123D01*
-X320972Y87123D01*
-X325883Y82212D01*
-X325883Y75268D01*
-X320972Y70357D01*
-X314028Y70357D01*
+X214147Y29289D02*
+X214147Y29289D01*
+X210909Y30631D01*
+X208431Y33109D01*
+X207089Y36347D01*
+X207089Y39853D01*
+X208431Y43091D01*
+X210909Y45569D01*
+X214147Y46911D01*
+X217653Y46911D01*
+X220891Y45569D01*
+X223369Y43091D01*
+X224711Y39853D01*
+X224711Y36347D01*
+X223369Y33109D01*
+X220891Y30631D01*
+X217653Y29289D01*
+X214147Y29289D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X212428Y95757D02*
-X212428Y95757D01*
-X207517Y100668D01*
-X207517Y107612D01*
-X212428Y112523D01*
-X219372Y112523D01*
-X224283Y107612D01*
-X224283Y100668D01*
-X219372Y95757D01*
-X212428Y95757D01*
+X87147Y29289D02*
+X87147Y29289D01*
+X83909Y30631D01*
+X81431Y33109D01*
+X80089Y36347D01*
+X80089Y39853D01*
+X81431Y43091D01*
+X83909Y45569D01*
+X87147Y46911D01*
+X90653Y46911D01*
+X93891Y45569D01*
+X96369Y43091D01*
+X97711Y39853D01*
+X97711Y36347D01*
+X96369Y33109D01*
+X93891Y30631D01*
+X90653Y29289D01*
+X87147Y29289D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X187028Y95757D02*
-X187028Y95757D01*
-X182117Y100668D01*
-X182117Y107612D01*
-X187028Y112523D01*
-X193972Y112523D01*
-X198883Y107612D01*
-X198883Y100668D01*
-X193972Y95757D01*
-X187028Y95757D01*
+X87147Y80089D02*
+X87147Y80089D01*
+X83909Y81431D01*
+X81431Y83909D01*
+X80089Y87147D01*
+X80089Y90653D01*
+X81431Y93891D01*
+X83909Y96369D01*
+X87147Y97711D01*
+X90653Y97711D01*
+X93891Y96369D01*
+X96369Y93891D01*
+X97711Y90653D01*
+X97711Y87147D01*
+X96369Y83909D01*
+X93891Y81431D01*
+X90653Y80089D01*
+X87147Y80089D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X364828Y70357D02*
-X364828Y70357D01*
-X359917Y75268D01*
-X359917Y82212D01*
-X364828Y87123D01*
-X371772Y87123D01*
-X376683Y82212D01*
-X376683Y75268D01*
-X371772Y70357D01*
-X364828Y70357D01*
+X163347Y29289D02*
+X163347Y29289D01*
+X160109Y30631D01*
+X157631Y33109D01*
+X156289Y36347D01*
+X156289Y39853D01*
+X157631Y43091D01*
+X160109Y45569D01*
+X163347Y46911D01*
+X166853Y46911D01*
+X170091Y45569D01*
+X172569Y43091D01*
+X173911Y39853D01*
+X173911Y36347D01*
+X172569Y33109D01*
+X170091Y30631D01*
+X166853Y29289D01*
+X163347Y29289D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X390228Y70357D02*
-X390228Y70357D01*
-X385317Y75268D01*
-X385317Y82212D01*
-X390228Y87123D01*
-X397172Y87123D01*
-X402083Y82212D01*
-X402083Y75268D01*
-X397172Y70357D01*
-X390228Y70357D01*
+X137947Y54689D02*
+X137947Y54689D01*
+X134709Y56031D01*
+X132231Y58509D01*
+X130889Y61747D01*
+X130889Y65253D01*
+X132231Y68491D01*
+X134709Y70969D01*
+X137947Y72311D01*
+X141453Y72311D01*
+X144691Y70969D01*
+X147169Y68491D01*
+X148511Y65253D01*
+X148511Y61747D01*
+X147169Y58509D01*
+X144691Y56031D01*
+X141453Y54689D01*
+X137947Y54689D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X415628Y70357D02*
-X415628Y70357D01*
-X410717Y75268D01*
-X410717Y82212D01*
-X415628Y87123D01*
-X422572Y87123D01*
-X427483Y82212D01*
-X427483Y75268D01*
-X422572Y70357D01*
-X415628Y70357D01*
+X188747Y54689D02*
+X188747Y54689D01*
+X185509Y56031D01*
+X183031Y58509D01*
+X181689Y61747D01*
+X181689Y65253D01*
+X183031Y68491D01*
+X185509Y70969D01*
+X188747Y72311D01*
+X192253Y72311D01*
+X195491Y70969D01*
+X197969Y68491D01*
+X199311Y65253D01*
+X199311Y61747D01*
+X197969Y58509D01*
+X195491Y56031D01*
+X192253Y54689D01*
+X188747Y54689D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X136228Y95757D02*
-X136228Y95757D01*
-X131317Y100668D01*
-X131317Y107612D01*
-X136228Y112523D01*
-X143172Y112523D01*
-X148083Y107612D01*
-X148083Y100668D01*
-X143172Y95757D01*
-X136228Y95757D01*
+X112547Y54689D02*
+X112547Y54689D01*
+X109309Y56031D01*
+X106831Y58509D01*
+X105489Y61747D01*
+X105489Y65253D01*
+X106831Y68491D01*
+X109309Y70969D01*
+X112547Y72311D01*
+X116053Y72311D01*
+X119291Y70969D01*
+X121769Y68491D01*
+X123111Y65253D01*
+X123111Y61747D01*
+X121769Y58509D01*
+X119291Y56031D01*
+X116053Y54689D01*
+X112547Y54689D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X517228Y70357D02*
-X517228Y70357D01*
-X512317Y75268D01*
-X512317Y82212D01*
-X517228Y87123D01*
-X524172Y87123D01*
-X529083Y82212D01*
-X529083Y75268D01*
-X524172Y70357D01*
-X517228Y70357D01*
+X87147Y54689D02*
+X87147Y54689D01*
+X83909Y56031D01*
+X81431Y58509D01*
+X80089Y61747D01*
+X80089Y65253D01*
+X81431Y68491D01*
+X83909Y70969D01*
+X87147Y72311D01*
+X90653Y72311D01*
+X93891Y70969D01*
+X96369Y68491D01*
+X97711Y65253D01*
+X97711Y61747D01*
+X96369Y58509D01*
+X93891Y56031D01*
+X90653Y54689D01*
+X87147Y54689D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X898228Y44957D02*
-X898228Y44957D01*
-X893317Y49868D01*
-X893317Y56812D01*
-X898228Y61723D01*
-X905172Y61723D01*
-X910083Y56812D01*
-X910083Y49868D01*
-X905172Y44957D01*
-X898228Y44957D01*
+X214147Y54689D02*
+X214147Y54689D01*
+X210909Y56031D01*
+X208431Y58509D01*
+X207089Y61747D01*
+X207089Y65253D01*
+X208431Y68491D01*
+X210909Y70969D01*
+X214147Y72311D01*
+X217653Y72311D01*
+X220891Y70969D01*
+X223369Y68491D01*
+X224711Y65253D01*
+X224711Y61747D01*
+X223369Y58509D01*
+X220891Y56031D01*
+X217653Y54689D01*
+X214147Y54689D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X110828Y95757D02*
-X110828Y95757D01*
-X105917Y100668D01*
-X105917Y107612D01*
-X110828Y112523D01*
-X117772Y112523D01*
-X122683Y107612D01*
-X122683Y100668D01*
-X117772Y95757D01*
-X110828Y95757D01*
+X112547Y80089D02*
+X112547Y80089D01*
+X109309Y81431D01*
+X106831Y83909D01*
+X105489Y87147D01*
+X105489Y90653D01*
+X106831Y93891D01*
+X109309Y96369D01*
+X112547Y97711D01*
+X116053Y97711D01*
+X119291Y96369D01*
+X121769Y93891D01*
+X123111Y90653D01*
+X123111Y87147D01*
+X121769Y83909D01*
+X119291Y81431D01*
+X116053Y80089D01*
+X112547Y80089D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X898228Y95757D02*
-X898228Y95757D01*
-X893317Y100668D01*
-X893317Y107612D01*
-X898228Y112523D01*
-X905172Y112523D01*
-X910083Y107612D01*
-X910083Y100668D01*
-X905172Y95757D01*
-X898228Y95757D01*
+X243822Y578103D02*
+X243822Y578103D01*
+X243077Y578848D01*
+X243077Y600220D01*
+X243822Y600965D01*
+X251478Y600965D01*
+X252223Y600220D01*
+X252223Y578848D01*
+X251478Y578103D01*
+X243822Y578103D01*
 G37*
 %LPD*%
-%LPC*%
 G36*
-X542628Y70357D02*
-X542628Y70357D01*
-X537717Y75268D01*
-X537717Y82212D01*
-X542628Y87123D01*
-X549572Y87123D01*
-X554483Y82212D01*
-X554483Y75268D01*
-X549572Y70357D01*
-X542628Y70357D01*
+X617319Y245356D02*
+X617319Y245356D01*
+X617457Y245365D01*
+X617476Y245371D01*
+X617496Y245373D01*
+X617628Y245420D01*
+X617759Y245463D01*
+X617777Y245473D01*
+X617796Y245480D01*
+X617911Y245558D01*
+X618028Y245633D01*
+X618042Y245648D01*
+X618059Y245659D01*
+X618151Y245763D01*
+X618246Y245864D01*
+X618256Y245882D01*
+X618269Y245897D01*
+X618333Y246021D01*
+X618400Y246143D01*
+X618405Y246162D01*
+X618414Y246181D01*
+X618444Y246316D01*
+X618479Y246451D01*
+X618481Y246479D01*
+X618484Y246491D01*
+X618483Y246511D01*
+X618489Y246612D01*
+X618489Y276611D01*
+X618477Y276710D01*
+X618474Y276809D01*
+X618457Y276867D01*
+X618449Y276927D01*
+X618413Y277019D01*
+X618385Y277114D01*
+X618355Y277166D01*
+X618332Y277223D01*
+X618274Y277303D01*
+X618224Y277388D01*
+X618158Y277463D01*
+X618146Y277480D01*
+X618136Y277488D01*
+X618118Y277509D01*
+X616847Y278779D01*
+X616738Y278864D01*
+X616631Y278953D01*
+X616612Y278961D01*
+X616596Y278974D01*
+X616469Y279029D01*
+X616343Y279088D01*
+X616323Y279092D01*
+X616304Y279100D01*
+X616166Y279122D01*
+X616030Y279148D01*
+X616010Y279147D01*
+X615990Y279150D01*
+X615851Y279137D01*
+X615713Y279128D01*
+X615694Y279122D01*
+X615674Y279120D01*
+X615542Y279073D01*
+X615411Y279030D01*
+X615393Y279019D01*
+X615374Y279013D01*
+X615259Y278935D01*
+X615142Y278860D01*
+X615128Y278845D01*
+X615111Y278834D01*
+X615019Y278730D01*
+X614924Y278629D01*
+X614914Y278611D01*
+X614901Y278596D01*
+X614837Y278471D01*
+X614770Y278350D01*
+X614765Y278330D01*
+X614756Y278312D01*
+X614726Y278177D01*
+X614691Y278042D01*
+X614689Y278014D01*
+X614686Y278002D01*
+X614687Y277982D01*
+X614681Y277881D01*
+X614681Y270728D01*
+X611242Y267289D01*
+X611182Y267211D01*
+X611114Y267139D01*
+X611085Y267086D01*
+X611048Y267038D01*
+X611008Y266947D01*
+X610960Y266860D01*
+X610945Y266802D01*
+X610921Y266746D01*
+X610906Y266648D01*
+X610881Y266553D01*
+X610875Y266452D01*
+X610871Y266432D01*
+X610873Y266420D01*
+X610871Y266392D01*
+X610871Y250145D01*
+X610874Y250116D01*
+X610872Y250087D01*
+X610894Y249958D01*
+X610911Y249830D01*
+X610921Y249802D01*
+X610926Y249773D01*
+X610980Y249655D01*
+X611028Y249534D01*
+X611045Y249510D01*
+X611057Y249483D01*
+X611138Y249382D01*
+X611214Y249277D01*
+X611237Y249258D01*
+X611256Y249235D01*
+X611359Y249157D01*
+X611459Y249074D01*
+X611486Y249061D01*
+X611510Y249044D01*
+X611654Y248973D01*
+X614061Y247976D01*
+X616323Y245714D01*
+X616432Y245629D01*
+X616539Y245540D01*
+X616558Y245532D01*
+X616574Y245519D01*
+X616702Y245464D01*
+X616827Y245405D01*
+X616847Y245401D01*
+X616866Y245393D01*
+X617004Y245371D01*
+X617140Y245345D01*
+X617160Y245346D01*
+X617180Y245343D01*
+X617319Y245356D01*
 G37*
-%LPD*%
 %LPC*%
 G36*
-X872828Y44957D02*
-X872828Y44957D01*
-X867917Y49868D01*
-X867917Y56812D01*
-X872828Y61723D01*
-X879772Y61723D01*
-X884683Y56812D01*
-X884683Y49868D01*
-X879772Y44957D01*
-X872828Y44957D01*
+X506434Y106425D02*
+X506434Y106425D01*
+X503539Y107624D01*
+X501324Y109839D01*
+X500125Y112734D01*
+X500125Y115866D01*
+X501324Y118761D01*
+X503539Y120976D01*
+X506434Y122175D01*
+X509566Y122175D01*
+X512461Y120976D01*
+X514676Y118761D01*
+X515875Y115866D01*
+X515875Y112734D01*
+X514676Y109839D01*
+X512461Y107624D01*
+X509566Y106425D01*
+X506434Y106425D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X847428Y44957D02*
-X847428Y44957D01*
-X842517Y49868D01*
-X842517Y56812D01*
-X847428Y61723D01*
-X854372Y61723D01*
-X859283Y56812D01*
-X859283Y49868D01*
-X854372Y44957D01*
-X847428Y44957D01*
+X531834Y4825D02*
+X531834Y4825D01*
+X528939Y6024D01*
+X526724Y8239D01*
+X525525Y11134D01*
+X525525Y14266D01*
+X526724Y17161D01*
+X528939Y19376D01*
+X531834Y20575D01*
+X534966Y20575D01*
+X537861Y19376D01*
+X540076Y17161D01*
+X541275Y14266D01*
+X541275Y11134D01*
+X540076Y8239D01*
+X537861Y6024D01*
+X534966Y4825D01*
+X531834Y4825D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X237828Y44957D02*
-X237828Y44957D01*
-X232917Y49868D01*
-X232917Y56812D01*
-X237828Y61723D01*
-X244772Y61723D01*
-X249683Y56812D01*
-X249683Y49868D01*
-X244772Y44957D01*
-X237828Y44957D01*
+X125434Y106425D02*
+X125434Y106425D01*
+X122539Y107624D01*
+X120324Y109839D01*
+X119125Y112734D01*
+X119125Y115866D01*
+X120324Y118761D01*
+X122539Y120976D01*
+X125434Y122175D01*
+X128566Y122175D01*
+X131461Y120976D01*
+X133676Y118761D01*
+X134875Y115866D01*
+X134875Y112734D01*
+X133676Y109839D01*
+X131461Y107624D01*
+X128566Y106425D01*
+X125434Y106425D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X212428Y44957D02*
-X212428Y44957D01*
-X207517Y49868D01*
-X207517Y56812D01*
-X212428Y61723D01*
-X219372Y61723D01*
-X224283Y56812D01*
-X224283Y49868D01*
-X219372Y44957D01*
-X212428Y44957D01*
+X201634Y4825D02*
+X201634Y4825D01*
+X198739Y6024D01*
+X196524Y8239D01*
+X195325Y11134D01*
+X195325Y14266D01*
+X196524Y17161D01*
+X198739Y19376D01*
+X201634Y20575D01*
+X204766Y20575D01*
+X207661Y19376D01*
+X209876Y17161D01*
+X211075Y14266D01*
+X211075Y11134D01*
+X209876Y8239D01*
+X207661Y6024D01*
+X204766Y4825D01*
+X201634Y4825D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X187028Y44957D02*
-X187028Y44957D01*
-X182117Y49868D01*
-X182117Y56812D01*
-X187028Y61723D01*
-X193972Y61723D01*
-X198883Y56812D01*
-X198883Y49868D01*
-X193972Y44957D01*
-X187028Y44957D01*
+X506434Y4825D02*
+X506434Y4825D01*
+X503539Y6024D01*
+X501324Y8239D01*
+X500125Y11134D01*
+X500125Y14266D01*
+X501324Y17161D01*
+X503539Y19376D01*
+X506434Y20575D01*
+X509566Y20575D01*
+X512461Y19376D01*
+X514676Y17161D01*
+X515875Y14266D01*
+X515875Y11134D01*
+X514676Y8239D01*
+X512461Y6024D01*
+X509566Y4825D01*
+X506434Y4825D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X136228Y44957D02*
-X136228Y44957D01*
-X131317Y49868D01*
-X131317Y56812D01*
-X136228Y61723D01*
-X143172Y61723D01*
-X148083Y56812D01*
-X148083Y49868D01*
-X143172Y44957D01*
-X136228Y44957D01*
+X303234Y4825D02*
+X303234Y4825D01*
+X300339Y6024D01*
+X298124Y8239D01*
+X296925Y11134D01*
+X296925Y14266D01*
+X298124Y17161D01*
+X300339Y19376D01*
+X303234Y20575D01*
+X306366Y20575D01*
+X309261Y19376D01*
+X311476Y17161D01*
+X312675Y14266D01*
+X312675Y11134D01*
+X311476Y8239D01*
+X309261Y6024D01*
+X306366Y4825D01*
+X303234Y4825D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X110828Y44957D02*
-X110828Y44957D01*
-X105917Y49868D01*
-X105917Y56812D01*
-X110828Y61723D01*
-X117772Y61723D01*
-X122683Y56812D01*
-X122683Y49868D01*
-X117772Y44957D01*
-X110828Y44957D01*
+X597874Y449325D02*
+X597874Y449325D01*
+X594979Y450524D01*
+X592764Y452739D01*
+X591565Y455634D01*
+X591565Y458766D01*
+X592764Y461661D01*
+X594979Y463876D01*
+X597874Y465075D01*
+X601006Y465075D01*
+X603901Y463876D01*
+X606116Y461661D01*
+X607315Y458766D01*
+X607315Y455634D01*
+X606116Y452739D01*
+X603901Y450524D01*
+X601006Y449325D01*
+X597874Y449325D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X225128Y156717D02*
-X225128Y156717D01*
-X220217Y161628D01*
-X220217Y168572D01*
-X225128Y173483D01*
-X232072Y173483D01*
-X236983Y168572D01*
-X236983Y161628D01*
-X232072Y156717D01*
-X225128Y156717D01*
+X277834Y4825D02*
+X277834Y4825D01*
+X274939Y6024D01*
+X272724Y8239D01*
+X271525Y11134D01*
+X271525Y14266D01*
+X272724Y17161D01*
+X274939Y19376D01*
+X277834Y20575D01*
+X280966Y20575D01*
+X283861Y19376D01*
+X286076Y17161D01*
+X287275Y14266D01*
+X287275Y11134D01*
+X286076Y8239D01*
+X283861Y6024D01*
+X280966Y4825D01*
+X277834Y4825D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X491828Y70357D02*
-X491828Y70357D01*
-X486917Y75268D01*
-X486917Y82212D01*
-X491828Y87123D01*
-X498772Y87123D01*
-X503683Y82212D01*
-X503683Y75268D01*
-X498772Y70357D01*
-X491828Y70357D01*
+X252434Y4825D02*
+X252434Y4825D01*
+X249539Y6024D01*
+X247324Y8239D01*
+X246125Y11134D01*
+X246125Y14266D01*
+X247324Y17161D01*
+X249539Y19376D01*
+X252434Y20575D01*
+X255566Y20575D01*
+X258461Y19376D01*
+X260676Y17161D01*
+X261875Y14266D01*
+X261875Y11134D01*
+X260676Y8239D01*
+X258461Y6024D01*
+X255566Y4825D01*
+X252434Y4825D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X872828Y95757D02*
-X872828Y95757D01*
-X867917Y100668D01*
-X867917Y107612D01*
-X872828Y112523D01*
-X879772Y112523D01*
-X884683Y107612D01*
-X884683Y100668D01*
-X879772Y95757D01*
-X872828Y95757D01*
+X227034Y4825D02*
+X227034Y4825D01*
+X224139Y6024D01*
+X221924Y8239D01*
+X220725Y11134D01*
+X220725Y14266D01*
+X221924Y17161D01*
+X224139Y19376D01*
+X227034Y20575D01*
+X230166Y20575D01*
+X233061Y19376D01*
+X235276Y17161D01*
+X236475Y14266D01*
+X236475Y11134D01*
+X235276Y8239D01*
+X233061Y6024D01*
+X230166Y4825D01*
+X227034Y4825D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X225128Y207517D02*
-X225128Y207517D01*
-X220217Y212428D01*
-X220217Y219372D01*
-X225128Y224283D01*
-X232072Y224283D01*
-X236983Y219372D01*
-X236983Y212428D01*
-X232072Y207517D01*
-X225128Y207517D01*
+X176234Y4825D02*
+X176234Y4825D01*
+X173339Y6024D01*
+X171124Y8239D01*
+X169925Y11134D01*
+X169925Y14266D01*
+X171124Y17161D01*
+X173339Y19376D01*
+X176234Y20575D01*
+X179366Y20575D01*
+X182261Y19376D01*
+X184476Y17161D01*
+X185675Y14266D01*
+X185675Y11134D01*
+X184476Y8239D01*
+X182261Y6024D01*
+X179366Y4825D01*
+X176234Y4825D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X225128Y182117D02*
-X225128Y182117D01*
-X220217Y187028D01*
-X220217Y193972D01*
-X225128Y198883D01*
-X232072Y198883D01*
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-X236983Y187028D01*
-X232072Y182117D01*
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+X150834Y4825D02*
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+X159076Y8239D01*
+X156861Y6024D01*
+X153966Y4825D01*
+X150834Y4825D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X796628Y95757D02*
-X796628Y95757D01*
-X791717Y100668D01*
-X791717Y107612D01*
-X796628Y112523D01*
-X803572Y112523D01*
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-X803572Y95757D01*
-X796628Y95757D01*
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+X94924Y118761D01*
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+X108276Y109839D01*
+X106061Y107624D01*
+X103166Y106425D01*
+X100034Y106425D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X822028Y95757D02*
-X822028Y95757D01*
-X817117Y100668D01*
-X817117Y107612D01*
-X822028Y112523D01*
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-X828972Y95757D01*
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+X133676Y8239D01*
+X131461Y6024D01*
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+X125434Y4825D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X847428Y95757D02*
-X847428Y95757D01*
-X842517Y100668D01*
-X842517Y107612D01*
-X847428Y112523D01*
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-X847428Y95757D01*
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 G37*
 %LPD*%
 %LPC*%
 G36*
-X161628Y70357D02*
-X161628Y70357D01*
-X156717Y75268D01*
-X156717Y82212D01*
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-X161628Y70357D01*
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+X74634Y4825D01*
 G37*
 %LPD*%
+%LPC*%
 G36*
-X432500Y368313D02*
-X432500Y368313D01*
-X432565Y368314D01*
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-X433061Y368881D01*
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+X311801Y552124D01*
+X308906Y550925D01*
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 G37*
+%LPD*%
+%LPC*%
 G36*
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-X541081Y192422D01*
-X541170Y192431D01*
-X541191Y192441D01*
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 G37*
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 %LPC*%
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+X763139Y638295D01*
+X761933Y636206D01*
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+X757046Y634999D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X98338Y157225D02*
-X98338Y157225D01*
-X93725Y161838D01*
-X93725Y168362D01*
-X98338Y172975D01*
-X104862Y172975D01*
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+X554722Y68783D01*
+X555442Y67370D01*
+X555933Y65860D01*
+X556105Y64769D01*
+X547369Y64769D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X98338Y182625D02*
-X98338Y182625D01*
-X93725Y187238D01*
-X93725Y193762D01*
-X98338Y198375D01*
-X104862Y198375D01*
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-X104862Y182625D01*
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+X529322Y68783D01*
+X530042Y67370D01*
+X530533Y65860D01*
+X530705Y64769D01*
+X521969Y64769D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X276138Y322325D02*
-X276138Y322325D01*
-X271525Y326938D01*
-X271525Y333462D01*
-X276138Y338075D01*
-X282662Y338075D01*
-X287275Y333462D01*
-X287275Y326938D01*
-X282662Y322325D01*
-X276138Y322325D01*
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+X503922Y68783D01*
+X504642Y67370D01*
+X505133Y65860D01*
+X505305Y64769D01*
+X496569Y64769D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X98338Y208025D02*
-X98338Y208025D01*
-X93725Y212638D01*
-X93725Y219162D01*
-X98338Y223775D01*
-X104862Y223775D01*
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-X109475Y212638D01*
-X104862Y208025D01*
-X98338Y208025D01*
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+X479242Y67370D01*
+X479733Y65860D01*
+X479905Y64769D01*
+X471169Y64769D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X996654Y370585D02*
-X996654Y370585D01*
-X993759Y371784D01*
-X991544Y373999D01*
-X990345Y376894D01*
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-X1004896Y382921D01*
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+X549970Y54158D01*
+X548460Y53667D01*
+X547369Y53495D01*
+X547369Y62231D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X227034Y347725D02*
-X227034Y347725D01*
-X224139Y348924D01*
-X221924Y351139D01*
-X220725Y354034D01*
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-X221924Y360061D01*
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-X227034Y363475D01*
-X230166Y363475D01*
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-X236475Y357166D01*
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-X235276Y351139D01*
-X233061Y348924D01*
-X230166Y347725D01*
-X227034Y347725D01*
+X510695Y64769D02*
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+X518340Y73333D01*
+X519431Y73505D01*
+X519431Y64769D01*
+X510695Y64769D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X150834Y347725D02*
-X150834Y347725D01*
-X147939Y348924D01*
-X145724Y351139D01*
-X144525Y354034D01*
-X144525Y357166D01*
-X145724Y360061D01*
-X147939Y362276D01*
-X150834Y363475D01*
-X153966Y363475D01*
-X156861Y362276D01*
-X159076Y360061D01*
-X160275Y357166D01*
-X160275Y354034D01*
-X159076Y351139D01*
-X156861Y348924D01*
-X153966Y347725D01*
-X150834Y347725D01*
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+X543740Y73333D01*
+X544831Y73505D01*
+X544831Y64769D01*
+X536095Y64769D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X996654Y93725D02*
-X996654Y93725D01*
-X993759Y94924D01*
-X991544Y97139D01*
-X990345Y100034D01*
-X990345Y103166D01*
-X991544Y106061D01*
-X993759Y108276D01*
-X996654Y109475D01*
-X999786Y109475D01*
-X1002681Y108276D01*
-X1004896Y106061D01*
-X1006095Y103166D01*
-X1006095Y100034D01*
-X1004896Y97139D01*
-X1002681Y94924D01*
-X999786Y93725D01*
-X996654Y93725D01*
+X561495Y64769D02*
+X561495Y64769D01*
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+X563811Y70067D01*
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+X567630Y72842D01*
+X569140Y73333D01*
+X570231Y73505D01*
+X570231Y64769D01*
+X561495Y64769D01*
 G37*
 %LPD*%
+%LPC*%
 G36*
-X406573Y342786D02*
-X406573Y342786D01*
-X406661Y342796D01*
-X406682Y342806D01*
-X406706Y342810D01*
-X406782Y342856D01*
-X406862Y342895D01*
-X406879Y342912D01*
-X406899Y342925D01*
-X406955Y342994D01*
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-X407025Y343080D01*
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-X407105Y343289D01*
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-X407110Y343400D01*
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-X406987Y343781D01*
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-X406325Y349503D01*
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-X390293Y365573D01*
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-X388882Y365510D01*
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-X393954Y343274D01*
-X393972Y343231D01*
-X393980Y343184D01*
-X394014Y343127D01*
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-X394070Y343032D01*
-X394095Y342991D01*
-X394146Y342949D01*
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-X394232Y342879D01*
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-X394390Y342798D01*
-X394444Y342790D01*
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-X394521Y342779D01*
-X394575Y342771D01*
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+X492940Y73333D01*
+X494031Y73505D01*
+X494031Y64769D01*
+X485295Y64769D01*
 G37*
+%LPD*%
+%LPC*%
 G36*
-X538541Y296562D02*
-X538541Y296562D01*
-X538630Y296571D01*
-X538651Y296581D01*
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-X539014Y297478D01*
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-X538990Y297518D01*
-X538956Y297556D01*
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-X535939Y300591D01*
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-X546086Y305565D01*
-X546068Y305609D01*
-X546059Y305656D01*
-X546026Y305713D01*
-X546001Y305773D01*
-X545969Y305808D01*
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-X545894Y305890D01*
-X545850Y305939D01*
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-X545709Y306011D01*
-X545650Y306042D01*
-X545596Y306050D01*
-X545559Y306062D01*
-X545519Y306061D01*
-X545465Y306069D01*
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-X539017Y312136D01*
-X539030Y312156D01*
-X539052Y312242D01*
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-X539063Y312596D01*
-X539023Y312676D01*
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-X538974Y312776D01*
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-X538899Y312858D01*
-X538839Y312924D01*
-X538817Y312935D01*
-X538800Y312951D01*
-X538718Y312986D01*
-X538639Y313027D01*
-X538613Y313030D01*
-X538594Y313039D01*
-X538543Y313041D01*
-X538454Y313054D01*
-X526550Y313054D01*
-X526463Y313038D01*
-X526374Y313029D01*
-X526353Y313019D01*
-X526329Y313015D01*
-X526253Y312969D01*
-X526173Y312930D01*
-X526157Y312913D01*
-X526136Y312900D01*
-X526080Y312831D01*
-X526019Y312767D01*
-X526010Y312745D01*
-X525995Y312726D01*
-X525966Y312642D01*
-X525932Y312560D01*
-X525931Y312536D01*
-X525923Y312514D01*
-X525926Y312425D01*
-X525922Y312336D01*
-X525929Y312313D01*
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-X525918Y297227D01*
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-X525930Y297049D01*
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-X525941Y297004D01*
-X525981Y296924D01*
-X526014Y296842D01*
-X526030Y296824D01*
-X526040Y296803D01*
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-X526365Y296573D01*
-X526391Y296570D01*
-X526410Y296561D01*
-X526461Y296559D01*
-X526550Y296546D01*
-X538454Y296546D01*
-X538541Y296562D01*
+X471169Y62231D02*
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+X475183Y54878D01*
+X473770Y54158D01*
+X472260Y53667D01*
+X471169Y53495D01*
+X471169Y62231D01*
 G37*
+%LPD*%
+%LPC*%
 G36*
-X429367Y343331D02*
-X429367Y343331D01*
-X429391Y343331D01*
-X429473Y343365D01*
-X429558Y343392D01*
-X429579Y343408D01*
-X429598Y343416D01*
-X429636Y343450D01*
-X429708Y343504D01*
-X429733Y343538D01*
-X429764Y343567D01*
-X429796Y343630D01*
-X429837Y343688D01*
-X429847Y343729D01*
-X429867Y343767D01*
-X429880Y343856D01*
-X429893Y343905D01*
-X429890Y343926D01*
-X429894Y343952D01*
-X429894Y351309D01*
-X431196Y352611D01*
-X431196Y352612D01*
-X439868Y361284D01*
-X439893Y361318D01*
-X439924Y361347D01*
-X439956Y361410D01*
-X439997Y361468D01*
-X440007Y361509D01*
-X440027Y361547D01*
-X440040Y361636D01*
-X440053Y361685D01*
-X440050Y361706D01*
-X440054Y361732D01*
-X440054Y362090D01*
-X440038Y362178D01*
-X440029Y362267D01*
-X440019Y362288D01*
-X440015Y362311D01*
-X439969Y362388D01*
-X439930Y362468D01*
-X439913Y362484D01*
-X439900Y362505D01*
-X439831Y362561D01*
-X439767Y362622D01*
-X439745Y362631D01*
-X439726Y362646D01*
-X439642Y362674D01*
-X439560Y362709D01*
-X439536Y362710D01*
-X439514Y362718D01*
-X439425Y362715D01*
-X439336Y362719D01*
-X439313Y362712D01*
-X439289Y362711D01*
-X439207Y362678D01*
-X439122Y362650D01*
-X439101Y362635D01*
-X439082Y362627D01*
-X439044Y362593D01*
-X438972Y362539D01*
-X435588Y359155D01*
-X433069Y359155D01*
-X433069Y367665D01*
-X433058Y367730D01*
-X433056Y367795D01*
-X433038Y367839D01*
-X433030Y367886D01*
-X432996Y367942D01*
-X432971Y368003D01*
-X432939Y368038D01*
-X432915Y368079D01*
-X432864Y368120D01*
-X432820Y368169D01*
-X432778Y368191D01*
-X432741Y368220D01*
-X432679Y368241D01*
-X432620Y368271D01*
-X432566Y368280D01*
-X432529Y368292D01*
-X432489Y368291D01*
-X432435Y368299D01*
-X431165Y368299D01*
-X431100Y368287D01*
-X431034Y368286D01*
-X430991Y368268D01*
-X430944Y368259D01*
-X430887Y368226D01*
-X430827Y368201D01*
-X430792Y368169D01*
-X430751Y368145D01*
-X430710Y368094D01*
-X430661Y368050D01*
-X430639Y368008D01*
-X430610Y367971D01*
-X430589Y367909D01*
-X430558Y367850D01*
-X430550Y367796D01*
-X430538Y367759D01*
-X430539Y367719D01*
-X430531Y367665D01*
-X430531Y359155D01*
-X428012Y359155D01*
-X424628Y362539D01*
-X424555Y362590D01*
-X424486Y362646D01*
-X424464Y362653D01*
-X424444Y362667D01*
-X424358Y362689D01*
-X424274Y362718D01*
-X424250Y362717D01*
-X424227Y362723D01*
-X424138Y362714D01*
-X424049Y362711D01*
-X424027Y362702D01*
-X424004Y362700D01*
-X423924Y362660D01*
-X423842Y362627D01*
-X423824Y362611D01*
-X423803Y362600D01*
-X423742Y362536D01*
-X423676Y362475D01*
-X423665Y362454D01*
-X423649Y362437D01*
-X423614Y362355D01*
-X423573Y362276D01*
-X423570Y362250D01*
-X423561Y362230D01*
-X423559Y362180D01*
-X423546Y362090D01*
-X423546Y359192D01*
-X423553Y359150D01*
-X423551Y359108D01*
-X423573Y359041D01*
-X423585Y358971D01*
-X423607Y358935D01*
-X423620Y358894D01*
-X423674Y358822D01*
-X423700Y358778D01*
-X423716Y358765D01*
-X423732Y358744D01*
-X428626Y353849D01*
-X428626Y343952D01*
-X428642Y343864D01*
-X428651Y343776D01*
-X428661Y343755D01*
-X428665Y343731D01*
-X428711Y343655D01*
-X428750Y343575D01*
-X428767Y343558D01*
-X428780Y343538D01*
-X428849Y343482D01*
-X428913Y343421D01*
-X428935Y343412D01*
-X428954Y343397D01*
-X429038Y343368D01*
-X429120Y343333D01*
-X429144Y343332D01*
-X429166Y343325D01*
-X429255Y343327D01*
-X429344Y343323D01*
-X429367Y343331D01*
+X496569Y62231D02*
+X496569Y62231D01*
+X505305Y62231D01*
+X505133Y61140D01*
+X504642Y59630D01*
+X503922Y58217D01*
+X502989Y56933D01*
+X501867Y55811D01*
+X500583Y54878D01*
+X499170Y54158D01*
+X497660Y53667D01*
+X496569Y53495D01*
+X496569Y62231D01*
 G37*
+%LPD*%
 %LPC*%
 G36*
-X953769Y153669D02*
-X953769Y153669D01*
-X953769Y168075D01*
-X955167Y167797D01*
-X956832Y167108D01*
-X958329Y166107D01*
-X959603Y164833D01*
-X960604Y163336D01*
-X961293Y161671D01*
-X961645Y159905D01*
-X961645Y153669D01*
-X953769Y153669D01*
+X521969Y62231D02*
+X521969Y62231D01*
+X530705Y62231D01*
+X530533Y61140D01*
+X530042Y59630D01*
+X529322Y58217D01*
+X528389Y56933D01*
+X527267Y55811D01*
+X525983Y54878D01*
+X524570Y54158D01*
+X523060Y53667D01*
+X521969Y53495D01*
+X521969Y62231D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X953769Y280669D02*
-X953769Y280669D01*
-X953769Y295075D01*
-X955167Y294797D01*
-X956832Y294108D01*
-X958329Y293107D01*
-X959603Y291833D01*
-X960604Y290336D01*
-X961293Y288671D01*
-X961645Y286905D01*
-X961645Y280669D01*
-X953769Y280669D01*
+X569140Y53667D02*
+X569140Y53667D01*
+X567630Y54158D01*
+X566217Y54878D01*
+X564933Y55811D01*
+X563811Y56933D01*
+X562878Y58217D01*
+X562158Y59630D01*
+X561667Y61140D01*
+X561495Y62231D01*
+X570231Y62231D01*
+X570231Y53495D01*
+X569140Y53667D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X26669Y166369D02*
-X26669Y166369D01*
-X26669Y174245D01*
-X32905Y174245D01*
-X34671Y173893D01*
-X36336Y173204D01*
-X37833Y172203D01*
-X39107Y170929D01*
-X40108Y169432D01*
-X40797Y167767D01*
-X41075Y166369D01*
-X26669Y166369D01*
+X492940Y53667D02*
+X492940Y53667D01*
+X491430Y54158D01*
+X490017Y54878D01*
+X488733Y55811D01*
+X487611Y56933D01*
+X486678Y58217D01*
+X485958Y59630D01*
+X485467Y61140D01*
+X485295Y62231D01*
+X494031Y62231D01*
+X494031Y53495D01*
+X492940Y53667D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X953769Y278131D02*
-X953769Y278131D01*
-X961645Y278131D01*
-X961645Y271895D01*
-X961293Y270129D01*
-X960604Y268464D01*
-X959603Y266967D01*
-X958329Y265693D01*
-X956832Y264692D01*
-X955167Y264003D01*
-X953769Y263725D01*
-X953769Y278131D01*
+X518340Y53667D02*
+X518340Y53667D01*
+X516830Y54158D01*
+X515417Y54878D01*
+X514133Y55811D01*
+X513011Y56933D01*
+X512078Y58217D01*
+X511358Y59630D01*
+X510867Y61140D01*
+X510695Y62231D01*
+X519431Y62231D01*
+X519431Y53495D01*
+X518340Y53667D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X953769Y151131D02*
-X953769Y151131D01*
-X961645Y151131D01*
-X961645Y144895D01*
-X961293Y143129D01*
-X960604Y141464D01*
-X959603Y139967D01*
-X958329Y138693D01*
-X956832Y137692D01*
-X955167Y137003D01*
-X953769Y136725D01*
-X953769Y151131D01*
+X569140Y79067D02*
+X569140Y79067D01*
+X567630Y79558D01*
+X566217Y80278D01*
+X564933Y81211D01*
+X563811Y82333D01*
+X562878Y83617D01*
+X562158Y85030D01*
+X561667Y86540D01*
+X561495Y87631D01*
+X570231Y87631D01*
+X570231Y78895D01*
+X569140Y79067D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X9725Y166369D02*
-X9725Y166369D01*
-X10003Y167767D01*
-X10692Y169432D01*
-X11693Y170929D01*
-X12967Y172203D01*
-X14464Y173204D01*
-X16129Y173893D01*
-X17895Y174245D01*
-X24131Y174245D01*
-X24131Y166369D01*
-X9725Y166369D01*
+X543740Y53667D02*
+X543740Y53667D01*
+X542230Y54158D01*
+X540817Y54878D01*
+X539533Y55811D01*
+X538411Y56933D01*
+X537478Y58217D01*
+X536758Y59630D01*
+X536267Y61140D01*
+X536095Y62231D01*
+X544831Y62231D01*
+X544831Y53495D01*
+X543740Y53667D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X943355Y153669D02*
-X943355Y153669D01*
-X943355Y159905D01*
-X943707Y161671D01*
-X944396Y163336D01*
-X945397Y164833D01*
-X946671Y166107D01*
-X948168Y167108D01*
-X949833Y167797D01*
-X951231Y168075D01*
-X951231Y153669D01*
-X943355Y153669D01*
+X739139Y541179D02*
+X739139Y541179D01*
+X739139Y547681D01*
+X744934Y547681D01*
+X745581Y547508D01*
+X746160Y547173D01*
+X746633Y546700D01*
+X746968Y546121D01*
+X747141Y545474D01*
+X747141Y541179D01*
+X739139Y541179D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X943355Y280669D02*
-X943355Y280669D01*
-X943355Y286905D01*
-X943707Y288671D01*
-X944396Y290336D01*
-X945397Y291833D01*
-X946671Y293107D01*
-X948168Y294108D01*
-X949833Y294797D01*
-X951231Y295075D01*
-X951231Y280669D01*
-X943355Y280669D01*
+X205739Y497999D02*
+X205739Y497999D01*
+X205739Y504501D01*
+X211534Y504501D01*
+X212181Y504328D01*
+X212760Y503993D01*
+X213233Y503520D01*
+X213568Y502941D01*
+X213741Y502294D01*
+X213741Y497999D01*
+X205739Y497999D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X26669Y155955D02*
-X26669Y155955D01*
-X26669Y163831D01*
-X41075Y163831D01*
-X40797Y162433D01*
-X40108Y160768D01*
-X39107Y159271D01*
-X37833Y157997D01*
-X36336Y156996D01*
-X34671Y156307D01*
-X32905Y155955D01*
-X26669Y155955D01*
+X205739Y624679D02*
+X205739Y624679D01*
+X205739Y631181D01*
+X211534Y631181D01*
+X212181Y631008D01*
+X212760Y630673D01*
+X213233Y630200D01*
+X213568Y629621D01*
+X213741Y628974D01*
+X213741Y624679D01*
+X205739Y624679D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X949833Y264003D02*
-X949833Y264003D01*
-X948168Y264692D01*
-X946671Y265693D01*
-X945397Y266967D01*
-X944396Y268464D01*
-X943707Y270129D01*
-X943355Y271895D01*
-X943355Y278131D01*
-X951231Y278131D01*
-X951231Y263725D01*
-X949833Y264003D01*
+X726059Y541179D02*
+X726059Y541179D01*
+X726059Y545474D01*
+X726232Y546121D01*
+X726567Y546700D01*
+X727040Y547173D01*
+X727619Y547508D01*
+X728266Y547681D01*
+X734061Y547681D01*
+X734061Y541179D01*
+X726059Y541179D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X949833Y137003D02*
-X949833Y137003D01*
-X948168Y137692D01*
-X946671Y138693D01*
-X945397Y139967D01*
-X944396Y141464D01*
-X943707Y143129D01*
-X943355Y144895D01*
-X943355Y151131D01*
-X951231Y151131D01*
-X951231Y136725D01*
-X949833Y137003D01*
+X840359Y541179D02*
+X840359Y541179D01*
+X840359Y545474D01*
+X840532Y546121D01*
+X840867Y546700D01*
+X841340Y547173D01*
+X841919Y547508D01*
+X842566Y547681D01*
+X848361Y547681D01*
+X848361Y541179D01*
+X840359Y541179D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X17895Y155955D02*
-X17895Y155955D01*
-X16129Y156307D01*
-X14464Y156996D01*
-X12967Y157997D01*
-X11693Y159271D01*
-X10692Y160768D01*
-X10003Y162433D01*
-X9725Y163831D01*
-X24131Y163831D01*
-X24131Y155955D01*
-X17895Y155955D01*
+X555879Y500539D02*
+X555879Y500539D01*
+X555879Y504834D01*
+X556052Y505481D01*
+X556387Y506060D01*
+X556860Y506533D01*
+X557439Y506868D01*
+X558086Y507041D01*
+X563881Y507041D01*
+X563881Y500539D01*
+X555879Y500539D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X10286Y358139D02*
-X10286Y358139D01*
-X7348Y359363D01*
-X6228Y360493D01*
-X5820Y360904D01*
-X5825Y362062D01*
-X6647Y362877D01*
-X7805Y362873D01*
-X8213Y362461D01*
-X8235Y362446D01*
-X8259Y362419D01*
-X8946Y361851D01*
-X8948Y361850D01*
-X9107Y361754D01*
-X10745Y361071D01*
-X10748Y361071D01*
-X10927Y361026D01*
-X11814Y360938D01*
-X11842Y360940D01*
-X11877Y360935D01*
-X11912Y360941D01*
-X11960Y360940D01*
-X12237Y360977D01*
-X12266Y360986D01*
-X12297Y360988D01*
-X12389Y361024D01*
-X12401Y361026D01*
-X12412Y361033D01*
-X12451Y361045D01*
-X12459Y361051D01*
-X12472Y361056D01*
-X12952Y361334D01*
-X13007Y361380D01*
-X13068Y361419D01*
-X13097Y361456D01*
-X13124Y361479D01*
-X13145Y361516D01*
-X13184Y361566D01*
-X13462Y362047D01*
-X13473Y362076D01*
-X13490Y362101D01*
-X13523Y362215D01*
-X13538Y362258D01*
-X13538Y362269D01*
-X13542Y362281D01*
-X13578Y362559D01*
-X13576Y362594D01*
-X13584Y362641D01*
-X13577Y362676D01*
-X13578Y362724D01*
-X13541Y363011D01*
-X13532Y363039D01*
-X13530Y363069D01*
-X13486Y363183D01*
-X13473Y363225D01*
-X13467Y363233D01*
-X13462Y363244D01*
-X13177Y363743D01*
-X13158Y363766D01*
-X13145Y363793D01*
-X13061Y363881D01*
-X13033Y363915D01*
-X13024Y363920D01*
-X13016Y363929D01*
-X12793Y364103D01*
-X12755Y364123D01*
-X12707Y364160D01*
-X9196Y366075D01*
-X9165Y366085D01*
-X9139Y366102D01*
-X9068Y366118D01*
-X8480Y366465D01*
-X8471Y366468D01*
-X8462Y366475D01*
-X7877Y366794D01*
-X7816Y366843D01*
-X7782Y366876D01*
-X7771Y366880D01*
-X7759Y366889D01*
-X7410Y367096D01*
-X6211Y369194D01*
-X6211Y371609D01*
-X7417Y373698D01*
-X9506Y374905D01*
-X9871Y374905D01*
-X11884Y374905D01*
-X14107Y374164D01*
-X15044Y373461D01*
-X15507Y373114D01*
-X15671Y371967D01*
-X14976Y371041D01*
-X13830Y370877D01*
-X13367Y371225D01*
-X13346Y371235D01*
-X13325Y371254D01*
-X12810Y371579D01*
-X12763Y371597D01*
-X12672Y371644D01*
-X11520Y372028D01*
-X11471Y372035D01*
-X11371Y372058D01*
-X10764Y372107D01*
-X10742Y372105D01*
-X10713Y372109D01*
-X10678Y372103D01*
-X10630Y372104D01*
-X10352Y372067D01*
-X10323Y372058D01*
-X10292Y372056D01*
-X10182Y372013D01*
-X10139Y371999D01*
-X10130Y371993D01*
-X10118Y371988D01*
-X9637Y371710D01*
-X9582Y371664D01*
-X9522Y371625D01*
-X9492Y371588D01*
-X9466Y371565D01*
-X9445Y371528D01*
-X9405Y371478D01*
-X9127Y370997D01*
-X9117Y370968D01*
-X9100Y370943D01*
-X9067Y370829D01*
-X9051Y370786D01*
-X9052Y370775D01*
-X9048Y370763D01*
-X9011Y370485D01*
-X9014Y370440D01*
-X9011Y370320D01*
-X9049Y370033D01*
-X9058Y370005D01*
-X9059Y369975D01*
-X9103Y369861D01*
-X9117Y369819D01*
-X9123Y369811D01*
-X9127Y369800D01*
-X9413Y369301D01*
-X9432Y369278D01*
-X9444Y369251D01*
-X9528Y369162D01*
-X9557Y369129D01*
-X9565Y369124D01*
-X9573Y369115D01*
-X9796Y368941D01*
-X9834Y368921D01*
-X9883Y368884D01*
-X13394Y366969D01*
-X13424Y366959D01*
-X13451Y366942D01*
-X13522Y366926D01*
-X14110Y366579D01*
-X14119Y366576D01*
-X14128Y366569D01*
-X14712Y366250D01*
-X14757Y366214D01*
-X14778Y366190D01*
-X14791Y366184D01*
-X14808Y366168D01*
-X14819Y366164D01*
-X14830Y366155D01*
-X15180Y365948D01*
-X16379Y363850D01*
-X16379Y361435D01*
-X15173Y359346D01*
-X13083Y358139D01*
-X10286Y358139D01*
+X317119Y500539D02*
+X317119Y500539D01*
+X317119Y504834D01*
+X317292Y505481D01*
+X317627Y506060D01*
+X318100Y506533D01*
+X318679Y506868D01*
+X319326Y507041D01*
+X325121Y507041D01*
+X325121Y500539D01*
+X317119Y500539D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X21552Y358139D02*
-X21552Y358139D01*
-X20733Y358958D01*
-X20733Y374086D01*
-X21552Y374905D01*
-X28919Y374905D01*
-X29738Y374086D01*
-X29738Y372928D01*
-X28919Y372109D01*
-X24163Y372109D01*
-X24098Y372098D01*
-X24032Y372096D01*
-X23989Y372078D01*
-X23942Y372070D01*
-X23885Y372036D01*
-X23824Y372011D01*
-X23790Y371980D01*
-X23749Y371955D01*
-X23707Y371904D01*
-X23659Y371860D01*
-X23637Y371818D01*
-X23608Y371781D01*
-X23586Y371719D01*
-X23556Y371660D01*
-X23548Y371606D01*
-X23536Y371569D01*
-X23537Y371529D01*
-X23529Y371475D01*
-X23529Y369330D01*
-X23540Y369265D01*
-X23542Y369200D01*
-X23560Y369156D01*
-X23568Y369109D01*
-X23602Y369052D01*
-X23627Y368992D01*
-X23658Y368957D01*
-X23682Y368916D01*
-X23734Y368875D01*
-X23778Y368826D01*
-X23820Y368804D01*
-X23857Y368775D01*
-X23919Y368754D01*
-X23978Y368724D01*
-X24032Y368715D01*
-X24069Y368703D01*
-X24108Y368704D01*
-X24163Y368696D01*
-X27367Y368696D01*
-X28185Y367877D01*
-X28185Y366719D01*
-X27367Y365900D01*
-X24163Y365900D01*
-X24098Y365889D01*
-X24032Y365887D01*
-X23989Y365869D01*
-X23942Y365861D01*
-X23885Y365827D01*
-X23824Y365802D01*
-X23790Y365771D01*
-X23749Y365747D01*
-X23707Y365695D01*
-X23659Y365651D01*
-X23637Y365609D01*
-X23608Y365572D01*
-X23586Y365510D01*
-X23556Y365451D01*
-X23548Y365397D01*
-X23536Y365360D01*
-X23537Y365321D01*
-X23529Y365266D01*
-X23529Y361569D01*
-X23540Y361504D01*
-X23542Y361438D01*
-X23560Y361395D01*
-X23568Y361348D01*
-X23602Y361291D01*
-X23627Y361231D01*
-X23658Y361196D01*
-X23682Y361155D01*
-X23734Y361113D01*
-X23778Y361065D01*
-X23820Y361043D01*
-X23857Y361014D01*
-X23919Y360993D01*
-X23978Y360962D01*
-X24032Y360954D01*
-X24069Y360942D01*
-X24108Y360943D01*
-X24163Y360935D01*
-X28919Y360935D01*
-X29738Y360116D01*
-X29738Y358958D01*
-X28919Y358139D01*
-X21552Y358139D01*
+X192659Y497999D02*
+X192659Y497999D01*
+X192659Y502294D01*
+X192832Y502941D01*
+X193167Y503520D01*
+X193640Y503993D01*
+X194219Y504328D01*
+X194866Y504501D01*
+X200661Y504501D01*
+X200661Y497999D01*
+X192659Y497999D01*
 G37*
 %LPD*%
+%LPC*%
 G36*
-X578078Y194962D02*
-X578078Y194962D01*
-X578167Y194971D01*
-X578188Y194981D01*
-X578211Y194985D01*
-X578288Y195031D01*
-X578368Y195070D01*
-X578384Y195087D01*
-X578405Y195100D01*
-X578461Y195169D01*
-X578522Y195233D01*
-X578531Y195255D01*
-X578546Y195274D01*
-X578574Y195358D01*
-X578609Y195440D01*
-X578610Y195464D01*
-X578618Y195486D01*
-X578615Y195575D01*
-X578619Y195664D01*
-X578612Y195687D01*
-X578611Y195711D01*
-X578578Y195793D01*
-X578550Y195878D01*
-X578535Y195899D01*
-X578527Y195918D01*
-X578493Y195956D01*
-X578439Y196028D01*
-X575055Y199412D01*
-X575055Y201931D01*
-X583565Y201931D01*
-X583630Y201942D01*
-X583695Y201944D01*
-X583739Y201962D01*
-X583786Y201970D01*
-X583842Y202004D01*
-X583903Y202029D01*
-X583938Y202060D01*
-X583979Y202085D01*
-X584020Y202136D01*
-X584069Y202180D01*
-X584091Y202222D01*
-X584120Y202259D01*
-X584141Y202321D01*
-X584171Y202380D01*
-X584180Y202434D01*
-X584192Y202471D01*
-X584191Y202511D01*
-X584199Y202565D01*
-X584199Y203835D01*
-X584187Y203900D01*
-X584186Y203965D01*
-X584168Y204009D01*
-X584159Y204056D01*
-X584126Y204113D01*
-X584101Y204173D01*
-X584069Y204208D01*
-X584045Y204249D01*
-X583994Y204290D01*
-X583950Y204339D01*
-X583908Y204361D01*
-X583871Y204390D01*
-X583809Y204411D01*
-X583750Y204442D01*
-X583696Y204450D01*
-X583659Y204462D01*
-X583619Y204461D01*
-X583565Y204469D01*
-X574457Y204469D01*
-X574415Y204462D01*
-X574373Y204464D01*
-X574306Y204442D01*
-X574236Y204430D01*
-X574200Y204408D01*
-X574159Y204395D01*
-X574086Y204341D01*
-X574043Y204315D01*
-X574030Y204299D01*
-X574009Y204283D01*
-X565754Y196028D01*
-X565703Y195955D01*
-X565647Y195886D01*
-X565639Y195864D01*
-X565625Y195844D01*
-X565603Y195758D01*
-X565575Y195674D01*
-X565575Y195650D01*
-X565570Y195627D01*
-X565579Y195538D01*
-X565581Y195449D01*
-X565590Y195427D01*
-X565593Y195404D01*
-X565632Y195324D01*
-X565666Y195242D01*
-X565682Y195224D01*
-X565692Y195203D01*
-X565757Y195142D01*
-X565817Y195076D01*
-X565838Y195065D01*
-X565855Y195049D01*
-X565937Y195014D01*
-X566017Y194973D01*
-X566043Y194970D01*
-X566062Y194961D01*
-X566112Y194959D01*
-X566202Y194946D01*
-X577990Y194946D01*
-X578078Y194962D01*
+X266539Y492379D02*
+X266539Y492379D01*
+X266539Y500381D01*
+X273041Y500381D01*
+X273041Y494586D01*
+X272868Y493939D01*
+X272533Y493360D01*
+X272060Y492887D01*
+X271481Y492552D01*
+X270834Y492379D01*
+X266539Y492379D01*
 G37*
+%LPD*%
 %LPC*%
 G36*
-X852169Y80009D02*
-X852169Y80009D01*
-X852169Y88393D01*
-X854898Y88393D01*
-X860553Y82738D01*
-X860553Y80009D01*
-X852169Y80009D01*
+X192659Y624679D02*
+X192659Y624679D01*
+X192659Y628974D01*
+X192832Y629621D01*
+X193167Y630200D01*
+X193640Y630673D01*
+X194219Y631008D01*
+X194866Y631181D01*
+X200661Y631181D01*
+X200661Y624679D01*
+X192659Y624679D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X826769Y80009D02*
-X826769Y80009D01*
-X826769Y88393D01*
-X829498Y88393D01*
-X835153Y82738D01*
-X835153Y80009D01*
-X826769Y80009D01*
+X205739Y613099D02*
+X205739Y613099D01*
+X205739Y619601D01*
+X213741Y619601D01*
+X213741Y615306D01*
+X213568Y614659D01*
+X213233Y614080D01*
+X212760Y613607D01*
+X212181Y613272D01*
+X211534Y613099D01*
+X205739Y613099D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X166369Y54609D02*
-X166369Y54609D01*
-X166369Y62993D01*
-X169098Y62993D01*
-X174753Y57338D01*
-X174753Y54609D01*
-X166369Y54609D01*
+X739139Y529599D02*
+X739139Y529599D01*
+X739139Y536101D01*
+X747141Y536101D01*
+X747141Y531806D01*
+X746968Y531159D01*
+X746633Y530580D01*
+X746160Y530107D01*
+X745581Y529772D01*
+X744934Y529599D01*
+X739139Y529599D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X166369Y105409D02*
-X166369Y105409D01*
-X166369Y113793D01*
-X169098Y113793D01*
-X174753Y108138D01*
-X174753Y105409D01*
-X166369Y105409D01*
+X205739Y486419D02*
+X205739Y486419D01*
+X205739Y492921D01*
+X213741Y492921D01*
+X213741Y488626D01*
+X213568Y487979D01*
+X213233Y487400D01*
+X212760Y486927D01*
+X212181Y486592D01*
+X211534Y486419D01*
+X205739Y486419D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X191769Y80009D02*
-X191769Y80009D01*
-X191769Y88393D01*
-X194498Y88393D01*
-X200153Y82738D01*
-X200153Y80009D01*
-X191769Y80009D01*
+X319326Y488959D02*
+X319326Y488959D01*
+X318679Y489132D01*
+X318100Y489467D01*
+X317627Y489940D01*
+X317292Y490519D01*
+X317119Y491166D01*
+X317119Y495461D01*
+X325121Y495461D01*
+X325121Y488959D01*
+X319326Y488959D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X902969Y80009D02*
-X902969Y80009D01*
-X902969Y88393D01*
-X905698Y88393D01*
-X911353Y82738D01*
-X911353Y80009D01*
-X902969Y80009D01*
+X728266Y529599D02*
+X728266Y529599D01*
+X727619Y529772D01*
+X727040Y530107D01*
+X726567Y530580D01*
+X726232Y531159D01*
+X726059Y531806D01*
+X726059Y536101D01*
+X734061Y536101D01*
+X734061Y529599D01*
+X728266Y529599D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X877569Y80009D02*
-X877569Y80009D01*
-X877569Y88393D01*
-X880298Y88393D01*
-X885953Y82738D01*
-X885953Y80009D01*
-X877569Y80009D01*
+X194866Y486419D02*
+X194866Y486419D01*
+X194219Y486592D01*
+X193640Y486927D01*
+X193167Y487400D01*
+X192832Y487979D01*
+X192659Y488626D01*
+X192659Y492921D01*
+X200661Y492921D01*
+X200661Y486419D01*
+X194866Y486419D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X866647Y80009D02*
-X866647Y80009D01*
-X866647Y82738D01*
-X872302Y88393D01*
-X875031Y88393D01*
-X875031Y80009D01*
-X866647Y80009D01*
+X257166Y492379D02*
+X257166Y492379D01*
+X256519Y492552D01*
+X255940Y492887D01*
+X255467Y493360D01*
+X255132Y493939D01*
+X254959Y494586D01*
+X254959Y500381D01*
+X261461Y500381D01*
+X261461Y492379D01*
+X257166Y492379D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X841247Y80009D02*
-X841247Y80009D01*
-X841247Y82738D01*
-X846902Y88393D01*
-X849631Y88393D01*
-X849631Y80009D01*
-X841247Y80009D01*
+X842566Y529599D02*
+X842566Y529599D01*
+X841919Y529772D01*
+X841340Y530107D01*
+X840867Y530580D01*
+X840532Y531159D01*
+X840359Y531806D01*
+X840359Y536101D01*
+X848361Y536101D01*
+X848361Y529599D01*
+X842566Y529599D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X155447Y105409D02*
-X155447Y105409D01*
-X155447Y108138D01*
-X161102Y113793D01*
-X163831Y113793D01*
-X163831Y105409D01*
-X155447Y105409D01*
+X194866Y613099D02*
+X194866Y613099D01*
+X194219Y613272D01*
+X193640Y613607D01*
+X193167Y614080D01*
+X192832Y614659D01*
+X192659Y615306D01*
+X192659Y619601D01*
+X200661Y619601D01*
+X200661Y613099D01*
+X194866Y613099D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X155447Y54609D02*
-X155447Y54609D01*
-X155447Y57338D01*
-X161102Y62993D01*
-X163831Y62993D01*
-X163831Y54609D01*
-X155447Y54609D01*
+X129539Y596239D02*
+X129539Y596239D01*
+X129539Y602741D01*
+X134834Y602741D01*
+X135481Y602568D01*
+X136060Y602233D01*
+X136533Y601760D01*
+X136868Y601181D01*
+X137041Y600534D01*
+X137041Y596239D01*
+X129539Y596239D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X180847Y80009D02*
-X180847Y80009D01*
-X180847Y82738D01*
-X186502Y88393D01*
-X189231Y88393D01*
-X189231Y80009D01*
-X180847Y80009D01*
+X116959Y596239D02*
+X116959Y596239D01*
+X116959Y600534D01*
+X117132Y601181D01*
+X117467Y601760D01*
+X117940Y602233D01*
+X118519Y602568D01*
+X119166Y602741D01*
+X124461Y602741D01*
+X124461Y596239D01*
+X116959Y596239D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X892047Y80009D02*
-X892047Y80009D01*
-X892047Y82738D01*
-X897702Y88393D01*
-X900431Y88393D01*
-X900431Y80009D01*
-X892047Y80009D01*
+X483869Y13969D02*
+X483869Y13969D01*
+X483869Y21771D01*
+X485267Y21493D01*
+X486932Y20804D01*
+X488429Y19803D01*
+X489703Y18529D01*
+X490704Y17032D01*
+X491393Y15367D01*
+X491671Y13969D01*
+X483869Y13969D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X191769Y69087D02*
-X191769Y69087D01*
-X191769Y77471D01*
-X200153Y77471D01*
-X200153Y74742D01*
-X194498Y69087D01*
-X191769Y69087D01*
+X473529Y13969D02*
+X473529Y13969D01*
+X473807Y15367D01*
+X474496Y17032D01*
+X475497Y18529D01*
+X476771Y19803D01*
+X478268Y20804D01*
+X479933Y21493D01*
+X481331Y21771D01*
+X481331Y13969D01*
+X473529Y13969D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X902969Y69087D02*
-X902969Y69087D01*
-X902969Y77471D01*
-X911353Y77471D01*
-X911353Y74742D01*
-X905698Y69087D01*
-X902969Y69087D01*
+X483869Y11431D02*
+X483869Y11431D01*
+X491671Y11431D01*
+X491393Y10033D01*
+X490704Y8368D01*
+X489703Y6871D01*
+X488429Y5597D01*
+X486932Y4596D01*
+X485267Y3907D01*
+X483869Y3629D01*
+X483869Y11431D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X877569Y69087D02*
-X877569Y69087D01*
-X877569Y77471D01*
-X885953Y77471D01*
-X885953Y74742D01*
-X880298Y69087D01*
-X877569Y69087D01*
+X479933Y3907D02*
+X479933Y3907D01*
+X478268Y4596D01*
+X476771Y5597D01*
+X475497Y6871D01*
+X474496Y8368D01*
+X473807Y10033D01*
+X473529Y11431D01*
+X481331Y11431D01*
+X481331Y3629D01*
+X479933Y3907D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X852169Y69087D02*
-X852169Y69087D01*
-X852169Y77471D01*
-X860553Y77471D01*
-X860553Y74742D01*
-X854898Y69087D01*
-X852169Y69087D01*
+X66039Y574039D02*
+X66039Y574039D01*
+X66039Y581359D01*
+X67400Y580916D01*
+X68825Y580190D01*
+X70119Y579250D01*
+X71250Y578119D01*
+X72190Y576825D01*
+X72916Y575400D01*
+X73359Y574039D01*
+X66039Y574039D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X166369Y43687D02*
-X166369Y43687D01*
-X166369Y52071D01*
-X174753Y52071D01*
-X174753Y49342D01*
-X169098Y43687D01*
-X166369Y43687D01*
+X66039Y523239D02*
+X66039Y523239D01*
+X66039Y530559D01*
+X67400Y530116D01*
+X68825Y529390D01*
+X70119Y528450D01*
+X71250Y527319D01*
+X72190Y526025D01*
+X72916Y524600D01*
+X73359Y523239D01*
+X66039Y523239D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X826769Y69087D02*
-X826769Y69087D01*
-X826769Y77471D01*
-X835153Y77471D01*
-X835153Y74742D01*
-X829498Y69087D01*
-X826769Y69087D01*
+X66039Y548639D02*
+X66039Y548639D01*
+X66039Y555959D01*
+X67400Y555516D01*
+X68825Y554790D01*
+X70119Y553850D01*
+X71250Y552719D01*
+X72190Y551425D01*
+X72916Y550000D01*
+X73359Y548639D01*
+X66039Y548639D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X166369Y94487D02*
-X166369Y94487D01*
-X166369Y102871D01*
-X174753Y102871D01*
-X174753Y100142D01*
-X169098Y94487D01*
-X166369Y94487D01*
+X294639Y638809D02*
+X294639Y638809D01*
+X294639Y646129D01*
+X296000Y645686D01*
+X297425Y644960D01*
+X298719Y644020D01*
+X299850Y642889D01*
+X300790Y641595D01*
+X301516Y640170D01*
+X301959Y638809D01*
+X294639Y638809D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X161102Y43687D02*
-X161102Y43687D01*
-X155447Y49342D01*
-X155447Y52071D01*
-X163831Y52071D01*
-X163831Y43687D01*
-X161102Y43687D01*
+X396239Y638809D02*
+X396239Y638809D01*
+X396239Y646129D01*
+X397600Y645686D01*
+X399025Y644960D01*
+X400319Y644020D01*
+X401450Y642889D01*
+X402390Y641595D01*
+X403116Y640170D01*
+X403559Y638809D01*
+X396239Y638809D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X872302Y69087D02*
-X872302Y69087D01*
-X866647Y74742D01*
-X866647Y77471D01*
-X875031Y77471D01*
-X875031Y69087D01*
-X872302Y69087D01*
+X53641Y599439D02*
+X53641Y599439D01*
+X54084Y600800D01*
+X54810Y602225D01*
+X55750Y603519D01*
+X56881Y604650D01*
+X58175Y605590D01*
+X59600Y606316D01*
+X60961Y606759D01*
+X60961Y599439D01*
+X53641Y599439D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X846902Y69087D02*
-X846902Y69087D01*
-X841247Y74742D01*
-X841247Y77471D01*
-X849631Y77471D01*
-X849631Y69087D01*
-X846902Y69087D01*
+X294639Y633731D02*
+X294639Y633731D01*
+X301959Y633731D01*
+X301516Y632370D01*
+X300790Y630945D01*
+X299850Y629651D01*
+X298719Y628520D01*
+X297425Y627580D01*
+X296000Y626854D01*
+X294639Y626411D01*
+X294639Y633731D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X186502Y69087D02*
-X186502Y69087D01*
-X180847Y74742D01*
-X180847Y77471D01*
-X189231Y77471D01*
-X189231Y69087D01*
-X186502Y69087D01*
+X53641Y523239D02*
+X53641Y523239D01*
+X54084Y524600D01*
+X54810Y526025D01*
+X55750Y527319D01*
+X56881Y528450D01*
+X58175Y529390D01*
+X59600Y530116D01*
+X60961Y530559D01*
+X60961Y523239D01*
+X53641Y523239D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X161102Y94487D02*
-X161102Y94487D01*
-X155447Y100142D01*
-X155447Y102871D01*
-X163831Y102871D01*
-X163831Y94487D01*
-X161102Y94487D01*
+X66039Y543561D02*
+X66039Y543561D01*
+X73359Y543561D01*
+X72916Y542200D01*
+X72190Y540775D01*
+X71250Y539481D01*
+X70119Y538350D01*
+X68825Y537410D01*
+X67400Y536684D01*
+X66039Y536241D01*
+X66039Y543561D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X897702Y69087D02*
-X897702Y69087D01*
-X892047Y74742D01*
-X892047Y77471D01*
-X900431Y77471D01*
-X900431Y69087D01*
-X897702Y69087D01*
+X282241Y638809D02*
+X282241Y638809D01*
+X282684Y640170D01*
+X283410Y641595D01*
+X284350Y642889D01*
+X285481Y644020D01*
+X286775Y644960D01*
+X288200Y645686D01*
+X289561Y646129D01*
+X289561Y638809D01*
+X282241Y638809D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X128269Y166369D02*
-X128269Y166369D01*
-X128269Y174245D01*
-X130788Y174245D01*
-X136145Y168888D01*
-X136145Y166369D01*
-X128269Y166369D01*
+X66039Y518161D02*
+X66039Y518161D01*
+X73359Y518161D01*
+X72916Y516800D01*
+X72190Y515375D01*
+X71250Y514081D01*
+X70119Y512950D01*
+X68825Y512010D01*
+X67400Y511284D01*
+X66039Y510841D01*
+X66039Y518161D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X979169Y379729D02*
-X979169Y379729D01*
-X979169Y387605D01*
-X981688Y387605D01*
-X987045Y382248D01*
-X987045Y379729D01*
-X979169Y379729D01*
+X53641Y574039D02*
+X53641Y574039D01*
+X54084Y575400D01*
+X54810Y576825D01*
+X55750Y578119D01*
+X56881Y579250D01*
+X58175Y580190D01*
+X59600Y580916D01*
+X60961Y581359D01*
+X60961Y574039D01*
+X53641Y574039D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X52069Y293369D02*
-X52069Y293369D01*
-X52069Y301245D01*
-X54588Y301245D01*
-X59945Y295888D01*
-X59945Y293369D01*
-X52069Y293369D01*
+X383841Y638809D02*
+X383841Y638809D01*
+X384284Y640170D01*
+X385010Y641595D01*
+X385950Y642889D01*
+X387081Y644020D01*
+X388375Y644960D01*
+X389800Y645686D01*
+X391161Y646129D01*
+X391161Y638809D01*
+X383841Y638809D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X52069Y267969D02*
-X52069Y267969D01*
-X52069Y275845D01*
-X54588Y275845D01*
-X59945Y270488D01*
-X59945Y267969D01*
-X52069Y267969D01*
+X53641Y624839D02*
+X53641Y624839D01*
+X54084Y626200D01*
+X54810Y627625D01*
+X55750Y628919D01*
+X56881Y630050D01*
+X58175Y630990D01*
+X59600Y631716D01*
+X60961Y632159D01*
+X60961Y624839D01*
+X53641Y624839D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X52069Y242569D02*
-X52069Y242569D01*
-X52069Y250445D01*
-X54588Y250445D01*
-X59945Y245088D01*
-X59945Y242569D01*
-X52069Y242569D01*
+X396239Y633731D02*
+X396239Y633731D01*
+X403559Y633731D01*
+X403116Y632370D01*
+X402390Y630945D01*
+X401450Y629651D01*
+X400319Y628520D01*
+X399025Y627580D01*
+X397600Y626854D01*
+X396239Y626411D01*
+X396239Y633731D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X128269Y217169D02*
-X128269Y217169D01*
-X128269Y225045D01*
-X130788Y225045D01*
-X136145Y219688D01*
-X136145Y217169D01*
-X128269Y217169D01*
+X53641Y548639D02*
+X53641Y548639D01*
+X54084Y550000D01*
+X54810Y551425D01*
+X55750Y552719D01*
+X56881Y553850D01*
+X58175Y554790D01*
+X59600Y555516D01*
+X60961Y555959D01*
+X60961Y548639D01*
+X53641Y548639D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X979169Y102869D02*
-X979169Y102869D01*
-X979169Y110745D01*
-X981688Y110745D01*
-X987045Y105388D01*
-X987045Y102869D01*
-X979169Y102869D01*
+X66039Y568961D02*
+X66039Y568961D01*
+X73359Y568961D01*
+X72916Y567599D01*
+X72190Y566175D01*
+X71250Y564881D01*
+X70119Y563750D01*
+X68825Y562810D01*
+X67400Y562084D01*
+X66039Y561641D01*
+X66039Y568961D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X128269Y191769D02*
-X128269Y191769D01*
-X128269Y199645D01*
-X130788Y199645D01*
-X136145Y194288D01*
-X136145Y191769D01*
-X128269Y191769D01*
+X59600Y587484D02*
+X59600Y587484D01*
+X58175Y588210D01*
+X56881Y589150D01*
+X55750Y590281D01*
+X54810Y591575D01*
+X54084Y593000D01*
+X53641Y594361D01*
+X60961Y594361D01*
+X60961Y587041D01*
+X59600Y587484D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X117855Y217169D02*
-X117855Y217169D01*
-X117855Y219688D01*
-X123212Y225045D01*
-X125731Y225045D01*
-X125731Y217169D01*
-X117855Y217169D01*
+X389800Y626854D02*
+X389800Y626854D01*
+X388375Y627580D01*
+X387081Y628520D01*
+X385950Y629651D01*
+X385010Y630945D01*
+X384284Y632370D01*
+X383841Y633731D01*
+X391161Y633731D01*
+X391161Y626411D01*
+X389800Y626854D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X117855Y166369D02*
-X117855Y166369D01*
-X117855Y168888D01*
-X123212Y174245D01*
-X125731Y174245D01*
-X125731Y166369D01*
-X117855Y166369D01*
+X59600Y511284D02*
+X59600Y511284D01*
+X58175Y512010D01*
+X56881Y512950D01*
+X55750Y514081D01*
+X54810Y515375D01*
+X54084Y516800D01*
+X53641Y518161D01*
+X60961Y518161D01*
+X60961Y510841D01*
+X59600Y511284D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X968755Y379729D02*
-X968755Y379729D01*
-X968755Y382248D01*
-X974112Y387605D01*
-X976631Y387605D01*
-X976631Y379729D01*
-X968755Y379729D01*
+X288200Y626854D02*
+X288200Y626854D01*
+X286775Y627580D01*
+X285481Y628520D01*
+X284350Y629651D01*
+X283410Y630945D01*
+X282684Y632370D01*
+X282241Y633731D01*
+X289561Y633731D01*
+X289561Y626411D01*
+X288200Y626854D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X41655Y242569D02*
-X41655Y242569D01*
-X41655Y245088D01*
-X47012Y250445D01*
-X49531Y250445D01*
-X49531Y242569D01*
-X41655Y242569D01*
+X59600Y536684D02*
+X59600Y536684D01*
+X58175Y537410D01*
+X56881Y538350D01*
+X55750Y539481D01*
+X54810Y540775D01*
+X54084Y542200D01*
+X53641Y543561D01*
+X60961Y543561D01*
+X60961Y536241D01*
+X59600Y536684D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X979169Y369315D02*
-X979169Y369315D01*
-X979169Y377191D01*
-X987045Y377191D01*
-X987045Y374672D01*
-X981688Y369315D01*
-X979169Y369315D01*
+X59600Y612884D02*
+X59600Y612884D01*
+X58175Y613610D01*
+X56881Y614550D01*
+X55750Y615681D01*
+X54810Y616975D01*
+X54084Y618400D01*
+X53641Y619761D01*
+X60961Y619761D01*
+X60961Y612441D01*
+X59600Y612884D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X52069Y282955D02*
-X52069Y282955D01*
-X52069Y290831D01*
-X59945Y290831D01*
-X59945Y288312D01*
-X54588Y282955D01*
-X52069Y282955D01*
+X59600Y562084D02*
+X59600Y562084D01*
+X58175Y562810D01*
+X56881Y563750D01*
+X55750Y564881D01*
+X54810Y566175D01*
+X54084Y567599D01*
+X53641Y568961D01*
+X60961Y568961D01*
+X60961Y561641D01*
+X59600Y562084D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X41655Y267969D02*
-X41655Y267969D01*
-X41655Y270488D01*
-X47012Y275845D01*
-X49531Y275845D01*
-X49531Y267969D01*
-X41655Y267969D01*
+X167599Y65999D02*
+X167599Y65999D01*
+X167599Y73287D01*
+X168970Y72842D01*
+X170383Y72122D01*
+X171667Y71189D01*
+X172789Y70067D01*
+X173722Y68783D01*
+X174442Y67370D01*
+X174887Y65999D01*
+X167599Y65999D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X128269Y155955D02*
-X128269Y155955D01*
-X128269Y163831D01*
-X136145Y163831D01*
-X136145Y161312D01*
-X130788Y155955D01*
-X128269Y155955D01*
+X878799Y65999D02*
+X878799Y65999D01*
+X878799Y73287D01*
+X880170Y72842D01*
+X881583Y72122D01*
+X882867Y71189D01*
+X883989Y70067D01*
+X884922Y68783D01*
+X885642Y67370D01*
+X886087Y65999D01*
+X878799Y65999D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X52069Y257555D02*
-X52069Y257555D01*
-X52069Y265431D01*
-X59945Y265431D01*
-X59945Y262912D01*
-X54588Y257555D01*
-X52069Y257555D01*
+X142199Y91399D02*
+X142199Y91399D01*
+X142199Y98687D01*
+X143570Y98242D01*
+X144983Y97522D01*
+X146267Y96589D01*
+X147389Y95467D01*
+X148322Y94183D01*
+X149042Y92770D01*
+X149487Y91399D01*
+X142199Y91399D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X356869Y359155D02*
-X356869Y359155D01*
-X356869Y367031D01*
-X364745Y367031D01*
-X364745Y364512D01*
-X359388Y359155D01*
-X356869Y359155D01*
+X142199Y40599D02*
+X142199Y40599D01*
+X142199Y47887D01*
+X143570Y47442D01*
+X144983Y46722D01*
+X146267Y45789D01*
+X147389Y44667D01*
+X148322Y43383D01*
+X149042Y41970D01*
+X149487Y40599D01*
+X142199Y40599D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X41655Y293369D02*
-X41655Y293369D01*
-X41655Y295888D01*
-X47012Y301245D01*
-X49531Y301245D01*
-X49531Y293369D01*
-X41655Y293369D01*
+X167599Y61001D02*
+X167599Y61001D01*
+X174887Y61001D01*
+X174442Y59630D01*
+X173722Y58217D01*
+X172789Y56933D01*
+X171667Y55811D01*
+X170383Y54878D01*
+X168970Y54158D01*
+X167599Y53713D01*
+X167599Y61001D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X280669Y346455D02*
-X280669Y346455D01*
-X280669Y354331D01*
-X288545Y354331D01*
-X288545Y351812D01*
-X283188Y346455D01*
-X280669Y346455D01*
+X878799Y61001D02*
+X878799Y61001D01*
+X886087Y61001D01*
+X885642Y59630D01*
+X884922Y58217D01*
+X883989Y56933D01*
+X882867Y55811D01*
+X881583Y54878D01*
+X880170Y54158D01*
+X878799Y53713D01*
+X878799Y61001D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X979169Y92455D02*
-X979169Y92455D01*
-X979169Y100331D01*
-X987045Y100331D01*
-X987045Y97812D01*
-X981688Y92455D01*
-X979169Y92455D01*
+X129913Y91399D02*
+X129913Y91399D01*
+X130358Y92770D01*
+X131078Y94183D01*
+X132011Y95467D01*
+X133133Y96589D01*
+X134417Y97522D01*
+X135830Y98242D01*
+X137201Y98687D01*
+X137201Y91399D01*
+X129913Y91399D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X117855Y191769D02*
-X117855Y191769D01*
-X117855Y194288D01*
-X123212Y199645D01*
-X125731Y199645D01*
-X125731Y191769D01*
-X117855Y191769D01*
+X142199Y86401D02*
+X142199Y86401D01*
+X149487Y86401D01*
+X149042Y85030D01*
+X148322Y83617D01*
+X147389Y82333D01*
+X146267Y81211D01*
+X144983Y80278D01*
+X143570Y79558D01*
+X142199Y79113D01*
+X142199Y86401D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X968755Y102869D02*
-X968755Y102869D01*
-X968755Y105388D01*
-X974112Y110745D01*
-X976631Y110745D01*
-X976631Y102869D01*
-X968755Y102869D01*
+X155313Y65999D02*
+X155313Y65999D01*
+X155758Y67370D01*
+X156478Y68783D01*
+X157411Y70067D01*
+X158533Y71189D01*
+X159817Y72122D01*
+X161230Y72842D01*
+X162601Y73287D01*
+X162601Y65999D01*
+X155313Y65999D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X52069Y232155D02*
-X52069Y232155D01*
-X52069Y240031D01*
-X59945Y240031D01*
-X59945Y237512D01*
-X54588Y232155D01*
-X52069Y232155D01*
+X142199Y35601D02*
+X142199Y35601D01*
+X149487Y35601D01*
+X149042Y34230D01*
+X148322Y32817D01*
+X147389Y31533D01*
+X146267Y30411D01*
+X144983Y29478D01*
+X143570Y28758D01*
+X142199Y28313D01*
+X142199Y35601D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X128269Y181355D02*
-X128269Y181355D01*
-X128269Y189231D01*
-X136145Y189231D01*
-X136145Y186712D01*
-X130788Y181355D01*
-X128269Y181355D01*
+X129913Y40599D02*
+X129913Y40599D01*
+X130358Y41970D01*
+X131078Y43383D01*
+X132011Y44667D01*
+X133133Y45789D01*
+X134417Y46722D01*
+X135830Y47442D01*
+X137201Y47887D01*
+X137201Y40599D01*
+X129913Y40599D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X128269Y206755D02*
-X128269Y206755D01*
-X128269Y214631D01*
-X136145Y214631D01*
-X136145Y212112D01*
-X130788Y206755D01*
-X128269Y206755D01*
+X135830Y28758D02*
+X135830Y28758D01*
+X134417Y29478D01*
+X133133Y30411D01*
+X132011Y31533D01*
+X131078Y32817D01*
+X130358Y34230D01*
+X129913Y35601D01*
+X137201Y35601D01*
+X137201Y28313D01*
+X135830Y28758D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X47012Y232155D02*
-X47012Y232155D01*
-X41655Y237512D01*
-X41655Y240031D01*
-X49531Y240031D01*
-X49531Y232155D01*
-X47012Y232155D01*
+X161230Y54158D02*
+X161230Y54158D01*
+X159817Y54878D01*
+X158533Y55811D01*
+X157411Y56933D01*
+X156478Y58217D01*
+X155758Y59630D01*
+X155313Y61001D01*
+X162601Y61001D01*
+X162601Y53713D01*
+X161230Y54158D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X974112Y369315D02*
-X974112Y369315D01*
-X968755Y374672D01*
-X968755Y377191D01*
-X976631Y377191D01*
-X976631Y369315D01*
-X974112Y369315D01*
+X135830Y79558D02*
+X135830Y79558D01*
+X134417Y80278D01*
+X133133Y81211D01*
+X132011Y82333D01*
+X131078Y83617D01*
+X130358Y85030D01*
+X129913Y86401D01*
+X137201Y86401D01*
+X137201Y79113D01*
+X135830Y79558D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X47012Y257555D02*
-X47012Y257555D01*
-X41655Y262912D01*
-X41655Y265431D01*
-X49531Y265431D01*
-X49531Y257555D01*
-X47012Y257555D01*
+X294131Y429769D02*
+X294131Y429769D01*
+X301037Y429769D01*
+X301020Y429659D01*
+X300575Y428290D01*
+X300002Y427166D01*
+X299968Y427070D01*
+X299965Y427067D01*
+X299964Y427066D01*
+X299964Y427065D01*
+X299963Y427065D01*
+X299075Y425843D01*
+X298057Y424825D01*
+X296893Y423979D01*
+X295610Y423325D01*
+X294241Y422880D01*
+X294131Y422863D01*
+X294131Y429769D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X123212Y181355D02*
-X123212Y181355D01*
-X117855Y186712D01*
-X117855Y189231D01*
-X125731Y189231D01*
-X125731Y181355D01*
-X123212Y181355D01*
+X294131Y459231D02*
+X294131Y459231D01*
+X294131Y466137D01*
+X294241Y466120D01*
+X295610Y465675D01*
+X296893Y465021D01*
+X298057Y464175D01*
+X299075Y463157D01*
+X299921Y461993D01*
+X300575Y460710D01*
+X301020Y459341D01*
+X301037Y459231D01*
+X294131Y459231D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X123212Y206755D02*
-X123212Y206755D01*
-X117855Y212112D01*
-X117855Y214631D01*
-X125731Y214631D01*
-X125731Y206755D01*
-X123212Y206755D01*
+X586231Y14731D02*
+X586231Y14731D01*
+X586231Y21637D01*
+X586341Y21620D01*
+X587710Y21175D01*
+X588993Y20521D01*
+X590157Y19675D01*
+X591175Y18657D01*
+X592021Y17493D01*
+X592675Y16210D01*
+X593120Y14841D01*
+X593137Y14731D01*
+X586231Y14731D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X123212Y155955D02*
-X123212Y155955D01*
-X117855Y161312D01*
-X117855Y163831D01*
-X125731Y163831D01*
-X125731Y155955D01*
-X123212Y155955D01*
+X621791Y459231D02*
+X621791Y459231D01*
+X621791Y466137D01*
+X621901Y466120D01*
+X623270Y465675D01*
+X624553Y465021D01*
+X625717Y464175D01*
+X626735Y463157D01*
+X627581Y461993D01*
+X628235Y460710D01*
+X628680Y459341D01*
+X628697Y459231D01*
+X621791Y459231D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X974112Y92455D02*
-X974112Y92455D01*
-X968755Y97812D01*
-X968755Y100331D01*
-X976631Y100331D01*
-X976631Y92455D01*
-X974112Y92455D01*
+X329691Y560831D02*
+X329691Y560831D01*
+X329691Y567737D01*
+X329801Y567720D01*
+X331170Y567275D01*
+X332453Y566621D01*
+X333617Y565775D01*
+X334635Y564757D01*
+X335481Y563593D01*
+X336135Y562310D01*
+X336580Y560941D01*
+X336597Y560831D01*
+X329691Y560831D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X351812Y359155D02*
-X351812Y359155D01*
-X346455Y364512D01*
-X346455Y367031D01*
-X354331Y367031D01*
-X354331Y359155D01*
-X351812Y359155D01*
+X575263Y14731D02*
+X575263Y14731D01*
+X575280Y14841D01*
+X575725Y16210D01*
+X576379Y17493D01*
+X577225Y18657D01*
+X578243Y19675D01*
+X579407Y20521D01*
+X580690Y21175D01*
+X582059Y21620D01*
+X582169Y21637D01*
+X582169Y14731D01*
+X575263Y14731D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X47012Y282955D02*
-X47012Y282955D01*
-X41655Y288312D01*
-X41655Y290831D01*
-X49531Y290831D01*
-X49531Y282955D01*
-X47012Y282955D01*
+X129031Y620269D02*
+X129031Y620269D01*
+X135937Y620269D01*
+X135920Y620159D01*
+X135475Y618790D01*
+X134821Y617507D01*
+X133975Y616343D01*
+X132957Y615325D01*
+X131793Y614479D01*
+X130510Y613825D01*
+X129141Y613380D01*
+X129031Y613363D01*
+X129031Y620269D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X275612Y346455D02*
-X275612Y346455D01*
-X270255Y351812D01*
-X270255Y354331D01*
-X278131Y354331D01*
-X278131Y346455D01*
-X275612Y346455D01*
+X621791Y455169D02*
+X621791Y455169D01*
+X628697Y455169D01*
+X628680Y455059D01*
+X628235Y453690D01*
+X627581Y452407D01*
+X626735Y451243D01*
+X625717Y450225D01*
+X624553Y449379D01*
+X623270Y448725D01*
+X621901Y448280D01*
+X621791Y448263D01*
+X621791Y455169D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X153669Y280669D02*
-X153669Y280669D01*
-X153669Y288471D01*
-X155067Y288193D01*
-X156732Y287504D01*
-X158229Y286503D01*
-X159503Y285229D01*
-X160504Y283732D01*
-X161193Y282067D01*
-X161471Y280669D01*
-X153669Y280669D01*
+X473663Y243331D02*
+X473663Y243331D01*
+X473680Y243441D01*
+X474125Y244810D01*
+X474779Y246093D01*
+X475625Y247257D01*
+X476643Y248275D01*
+X477807Y249121D01*
+X479090Y249775D01*
+X480459Y250220D01*
+X480569Y250237D01*
+X480569Y243331D01*
+X473663Y243331D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X143329Y280669D02*
-X143329Y280669D01*
-X143607Y282067D01*
-X144296Y283732D01*
-X145297Y285229D01*
-X146571Y286503D01*
-X148068Y287504D01*
-X149733Y288193D01*
-X151131Y288471D01*
-X151131Y280669D01*
-X143329Y280669D01*
+X283163Y459231D02*
+X283163Y459231D01*
+X283180Y459341D01*
+X283625Y460710D01*
+X284279Y461993D01*
+X285125Y463157D01*
+X286143Y464175D01*
+X287307Y465021D01*
+X288590Y465675D01*
+X289959Y466120D01*
+X290069Y466137D01*
+X290069Y459231D01*
+X283163Y459231D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X153669Y278131D02*
-X153669Y278131D01*
-X161471Y278131D01*
-X161193Y276733D01*
-X160504Y275068D01*
-X159503Y273571D01*
-X158229Y272297D01*
-X156732Y271296D01*
-X155067Y270607D01*
-X153669Y270329D01*
-X153669Y278131D01*
+X575263Y116331D02*
+X575263Y116331D01*
+X575280Y116441D01*
+X575725Y117810D01*
+X576379Y119093D01*
+X577225Y120257D01*
+X578243Y121275D01*
+X579407Y122121D01*
+X580690Y122775D01*
+X582059Y123220D01*
+X582169Y123237D01*
+X582169Y116331D01*
+X575263Y116331D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X149733Y270607D02*
-X149733Y270607D01*
-X148068Y271296D01*
-X146571Y272297D01*
-X145297Y273571D01*
-X144296Y275068D01*
-X143607Y276733D01*
-X143329Y278131D01*
-X151131Y278131D01*
-X151131Y270329D01*
-X149733Y270607D01*
+X610823Y459231D02*
+X610823Y459231D01*
+X610840Y459341D01*
+X611285Y460710D01*
+X611939Y461993D01*
+X612785Y463157D01*
+X613803Y464175D01*
+X614967Y465021D01*
+X616250Y465675D01*
+X617619Y466120D01*
+X617729Y466137D01*
+X617729Y459231D01*
+X610823Y459231D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X342109Y174874D02*
-X342109Y174874D01*
-X342109Y181835D01*
-X342282Y182481D01*
-X342617Y183060D01*
-X343090Y183533D01*
-X343669Y183868D01*
-X344315Y184041D01*
-X345526Y184041D01*
-X345526Y174874D01*
-X342109Y174874D01*
+X318723Y560831D02*
+X318723Y560831D01*
+X318740Y560941D01*
+X319185Y562310D01*
+X319839Y563593D01*
+X320685Y564757D01*
+X321703Y565775D01*
+X322867Y566621D01*
+X324150Y567275D01*
+X325519Y567720D01*
+X325629Y567737D01*
+X325629Y560831D01*
+X318723Y560831D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X344315Y163959D02*
-X344315Y163959D01*
-X343669Y164132D01*
-X343090Y164467D01*
-X342617Y164940D01*
-X342282Y165519D01*
-X342109Y166165D01*
-X342109Y173126D01*
-X345526Y173126D01*
-X345526Y163959D01*
-X344315Y163959D01*
+X329691Y556769D02*
+X329691Y556769D01*
+X336597Y556769D01*
+X336580Y556659D01*
+X336135Y555290D01*
+X335481Y554007D01*
+X334635Y552843D01*
+X333617Y551825D01*
+X332453Y550979D01*
+X331170Y550325D01*
+X329801Y549880D01*
+X329691Y549863D01*
+X329691Y556769D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X50799Y241299D02*
-X50799Y241299D01*
-X50799Y241301D01*
-X50801Y241301D01*
-X50801Y241299D01*
-X50799Y241299D01*
+X480459Y232380D02*
+X480459Y232380D01*
+X479090Y232825D01*
+X477807Y233479D01*
+X476643Y234325D01*
+X475625Y235343D01*
+X474779Y236507D01*
+X474125Y237790D01*
+X473680Y239159D01*
+X473663Y239269D01*
+X480569Y239269D01*
+X480569Y232363D01*
+X480459Y232380D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X25399Y165099D02*
-X25399Y165099D01*
-X25399Y165101D01*
-X25401Y165101D01*
-X25401Y165099D01*
-X25399Y165099D01*
+X617619Y448280D02*
+X617619Y448280D01*
+X616250Y448725D01*
+X614967Y449379D01*
+X613803Y450225D01*
+X612785Y451243D01*
+X611939Y452407D01*
+X611285Y453690D01*
+X610840Y455059D01*
+X610823Y455169D01*
+X617729Y455169D01*
+X617729Y448263D01*
+X617619Y448280D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X50799Y266699D02*
-X50799Y266699D01*
-X50799Y266701D01*
-X50801Y266701D01*
-X50801Y266699D01*
-X50799Y266699D01*
+X582059Y105380D02*
+X582059Y105380D01*
+X580690Y105825D01*
+X579407Y106479D01*
+X578243Y107325D01*
+X577225Y108343D01*
+X576379Y109507D01*
+X575725Y110790D01*
+X575280Y112159D01*
+X575263Y112269D01*
+X582169Y112269D01*
+X582169Y105363D01*
+X582059Y105380D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X952499Y152399D02*
-X952499Y152399D01*
-X952499Y152401D01*
-X952501Y152401D01*
-X952501Y152399D01*
-X952499Y152399D01*
+X325519Y549880D02*
+X325519Y549880D01*
+X324150Y550325D01*
+X322867Y550979D01*
+X321703Y551825D01*
+X320685Y552843D01*
+X319839Y554007D01*
+X319185Y555290D01*
+X318740Y556659D01*
+X318723Y556769D01*
+X325629Y556769D01*
+X325629Y549863D01*
+X325519Y549880D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X190499Y78739D02*
-X190499Y78739D01*
-X190499Y78741D01*
-X190501Y78741D01*
-X190501Y78739D01*
-X190499Y78739D01*
+X124859Y613380D02*
+X124859Y613380D01*
+X123490Y613825D01*
+X122207Y614479D01*
+X121043Y615325D01*
+X120025Y616343D01*
+X119179Y617507D01*
+X118525Y618790D01*
+X118080Y620159D01*
+X118063Y620269D01*
+X124969Y620269D01*
+X124969Y613363D01*
+X124859Y613380D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X901699Y78739D02*
-X901699Y78739D01*
-X901699Y78741D01*
-X901701Y78741D01*
-X901701Y78739D01*
-X901699Y78739D01*
+X63499Y546099D02*
+X63499Y546099D01*
+X63499Y546101D01*
+X63501Y546101D01*
+X63501Y546099D01*
+X63499Y546099D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X977899Y378459D02*
-X977899Y378459D01*
-X977899Y378461D01*
-X977901Y378461D01*
-X977901Y378459D01*
-X977899Y378459D01*
+X546099Y63499D02*
+X546099Y63499D01*
+X546099Y63501D01*
+X546101Y63501D01*
+X546101Y63499D01*
+X546099Y63499D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X152399Y279399D02*
-X152399Y279399D01*
-X152399Y279401D01*
-X152401Y279401D01*
-X152401Y279399D01*
-X152399Y279399D01*
+X292099Y636269D02*
+X292099Y636269D01*
+X292099Y636271D01*
+X292101Y636271D01*
+X292101Y636269D01*
+X292099Y636269D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X952499Y279399D02*
-X952499Y279399D01*
-X952499Y279401D01*
-X952501Y279401D01*
-X952501Y279399D01*
-X952499Y279399D01*
+X393699Y636269D02*
+X393699Y636269D01*
+X393699Y636271D01*
+X393701Y636271D01*
+X393701Y636269D01*
+X393699Y636269D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X126999Y190499D02*
-X126999Y190499D01*
-X126999Y190501D01*
-X127001Y190501D01*
-X127001Y190499D01*
-X126999Y190499D01*
+X495299Y63499D02*
+X495299Y63499D01*
+X495299Y63501D01*
+X495301Y63501D01*
+X495301Y63499D01*
+X495299Y63499D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X165099Y104139D02*
-X165099Y104139D01*
-X165099Y104141D01*
-X165101Y104141D01*
-X165101Y104139D01*
-X165099Y104139D01*
+X520699Y63499D02*
+X520699Y63499D01*
+X520699Y63501D01*
+X520701Y63501D01*
+X520701Y63499D01*
+X520699Y63499D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X876299Y78739D02*
-X876299Y78739D01*
-X876299Y78741D01*
-X876301Y78741D01*
-X876301Y78739D01*
-X876299Y78739D01*
+X63499Y571499D02*
+X63499Y571499D01*
+X63499Y571501D01*
+X63501Y571501D01*
+X63501Y571499D01*
+X63499Y571499D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X850899Y78739D02*
-X850899Y78739D01*
-X850899Y78741D01*
-X850901Y78741D01*
-X850901Y78739D01*
-X850899Y78739D01*
+X482599Y12699D02*
+X482599Y12699D01*
+X482599Y12701D01*
+X482601Y12701D01*
+X482601Y12699D01*
+X482599Y12699D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X977899Y101599D02*
-X977899Y101599D01*
-X977899Y101601D01*
-X977901Y101601D01*
-X977901Y101599D01*
-X977899Y101599D01*
+X63499Y520699D02*
+X63499Y520699D01*
+X63499Y520701D01*
+X63501Y520701D01*
+X63501Y520699D01*
+X63499Y520699D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X126999Y165099D02*
-X126999Y165099D01*
-X126999Y165101D01*
-X127001Y165101D01*
-X127001Y165099D01*
-X126999Y165099D01*
+X203199Y495459D02*
+X203199Y495459D01*
+X203199Y495461D01*
+X203201Y495461D01*
+X203201Y495459D01*
+X203199Y495459D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X165099Y53339D02*
-X165099Y53339D01*
-X165099Y53341D01*
-X165101Y53341D01*
-X165101Y53339D01*
-X165099Y53339D01*
+X736599Y538639D02*
+X736599Y538639D01*
+X736599Y538641D01*
+X736601Y538641D01*
+X736601Y538639D01*
+X736599Y538639D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X126999Y215899D02*
-X126999Y215899D01*
-X126999Y215901D01*
-X127001Y215901D01*
-X127001Y215899D01*
-X126999Y215899D01*
+X327659Y497999D02*
+X327659Y497999D01*
+X327659Y498001D01*
+X327661Y498001D01*
+X327661Y497999D01*
+X327659Y497999D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X50799Y292099D02*
-X50799Y292099D01*
-X50799Y292101D01*
-X50801Y292101D01*
-X50801Y292099D01*
-X50799Y292099D01*
+X203199Y622139D02*
+X203199Y622139D01*
+X203199Y622141D01*
+X203201Y622141D01*
+X203201Y622139D01*
+X203199Y622139D01*
 G37*
 %LPD*%
 D10*
-X30671Y393573D02*
-X41593Y360807D01*
-X52515Y393573D01*
-X74761Y379010D02*
-X80222Y379010D01*
-X80222Y360807D01*
-X69300Y360807D01*
-X69124Y360809D01*
-X68948Y360816D01*
-X68773Y360826D01*
-X68597Y360841D01*
-X68422Y360860D01*
-X68248Y360883D01*
-X68074Y360911D01*
-X67901Y360943D01*
-X67729Y360979D01*
-X67558Y361019D01*
-X67387Y361063D01*
-X67218Y361111D01*
-X67050Y361163D01*
-X66883Y361220D01*
-X66718Y361280D01*
-X66554Y361345D01*
-X66392Y361413D01*
-X66232Y361485D01*
-X66073Y361561D01*
-X65916Y361641D01*
-X65762Y361725D01*
-X65609Y361812D01*
-X65458Y361903D01*
-X65310Y361998D01*
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-X64879Y362303D01*
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-X64605Y362523D01*
-X64472Y362638D01*
-X64342Y362756D01*
-X64214Y362878D01*
-X64090Y363002D01*
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-X63850Y363260D01*
-X63735Y363393D01*
-X63623Y363529D01*
-X63515Y363667D01*
-X63410Y363808D01*
-X63308Y363952D01*
-X63210Y364098D01*
-X63115Y364246D01*
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-X62937Y364550D01*
-X62853Y364704D01*
-X62773Y364861D01*
-X62697Y365020D01*
-X62625Y365180D01*
-X62557Y365342D01*
-X62492Y365506D01*
-X62432Y365671D01*
-X62375Y365838D01*
-X62323Y366006D01*
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-X62231Y366346D01*
-X62191Y366517D01*
-X62155Y366689D01*
-X62123Y366862D01*
-X62095Y367036D01*
-X62072Y367210D01*
-X62053Y367385D01*
-X62038Y367561D01*
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-X62021Y367912D01*
-X62019Y368088D01*
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-X62018Y386292D01*
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-X62126Y387537D01*
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-X62237Y388061D01*
-X62283Y388234D01*
-X62333Y388406D01*
-X62386Y388576D01*
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-X62573Y389078D01*
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-X62718Y389405D01*
-X62796Y389566D01*
-X62879Y389724D01*
-X62965Y389881D01*
-X63055Y390035D01*
-X63149Y390187D01*
-X63246Y390337D01*
-X63347Y390484D01*
-X63452Y390629D01*
-X63560Y390771D01*
-X63672Y390911D01*
-X63787Y391048D01*
-X63905Y391182D01*
-X64027Y391313D01*
-X64152Y391440D01*
-X64279Y391565D01*
-X64410Y391687D01*
-X64544Y391805D01*
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-X64820Y392032D01*
-X64963Y392140D01*
-X65108Y392245D01*
-X65255Y392346D01*
-X65405Y392443D01*
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-X66026Y392796D01*
-X66187Y392874D01*
-X66349Y392948D01*
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-X66680Y393085D01*
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-X67016Y393206D01*
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-X67358Y393309D01*
-X67531Y393355D01*
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-X68232Y393494D01*
-X68409Y393518D01*
-X68586Y393538D01*
-X68764Y393553D01*
-X68943Y393564D01*
-X69121Y393571D01*
-X69300Y393573D01*
-X80222Y393573D01*
-X100648Y393573D02*
-X89726Y360807D01*
-X111570Y360807D02*
-X100648Y393573D01*
-X108839Y368999D02*
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+X777431Y670433D02*
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+X813946Y670119D01*
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+X814291Y670215D01*
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+X814640Y670293D01*
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+X858330Y637667D02*
+X847408Y670433D01*
+X855599Y645859D02*
+X839216Y645859D01*
 D11*
-X326400Y314000D03*
-X326400Y309000D03*
-X326400Y304000D03*
-X326400Y299000D03*
-X326400Y294000D03*
-X326400Y289000D03*
-X326400Y284000D03*
-X326400Y279000D03*
-X326400Y274000D03*
-X326400Y269000D03*
-X326400Y264000D03*
-X326400Y259000D03*
-X326400Y254000D03*
-X326400Y249000D03*
-X326400Y244000D03*
-X326400Y239000D03*
-X326400Y234000D03*
-X326400Y229000D03*
-X326400Y224000D03*
-X326400Y219000D03*
-X326400Y214000D03*
-X326400Y209000D03*
-X326400Y204000D03*
-X326400Y199000D03*
-X326400Y194000D03*
+G36*
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+G37*
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+G37*
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+G37*
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+G37*
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+G36*
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+G37*
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+G37*
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+G37*
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+G37*
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+G37*
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+G37*
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+G37*
 D12*
-X346400Y174000D03*
-X351400Y174000D03*
-X356400Y174000D03*
-X361400Y174000D03*
-X366400Y174000D03*
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-X421400Y174000D03*
-X426400Y174000D03*
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-X436400Y174000D03*
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-X446400Y174000D03*
-X451400Y174000D03*
-X456400Y174000D03*
-X461400Y174000D03*
-X466400Y174000D03*
+G36*
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+G37*
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+G37*
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+G37*
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+G37*
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+X547560Y487318D01*
+X536955Y497923D01*
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+X550035Y489793D01*
+G37*
 D11*
-X486400Y194000D03*
-X486400Y199000D03*
-X486400Y204000D03*
-X486400Y209000D03*
-X486400Y214000D03*
-X486400Y219000D03*
-X486400Y224000D03*
-X486400Y229000D03*
-X486400Y234000D03*
-X486400Y239000D03*
-X486400Y244000D03*
-X486400Y249000D03*
-X486400Y254000D03*
-X486400Y259000D03*
-X486400Y264000D03*
-X486400Y269000D03*
-X486400Y274000D03*
-X486400Y279000D03*
-X486400Y284000D03*
-X486400Y289000D03*
-X486400Y294000D03*
-X486400Y299000D03*
-X486400Y304000D03*
-X486400Y309000D03*
-X486400Y314000D03*
+G36*
+X550035Y526207D02*
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+X547560Y528682D01*
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+G37*
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+X535894Y519138D01*
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+G37*
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+G37*
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+G37*
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+X476849Y599393D01*
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+G37*
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+G37*
+G36*
+X472253Y603989D02*
+X461648Y593384D01*
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+G37*
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+G37*
 D12*
-X466400Y334000D03*
-X461400Y334000D03*
-X456400Y334000D03*
-X451400Y334000D03*
-X446400Y334000D03*
-X441400Y334000D03*
-X436400Y334000D03*
-X431400Y334000D03*
-X426400Y334000D03*
-X421400Y334000D03*
-X416400Y334000D03*
-X411400Y334000D03*
-X406400Y334000D03*
-X401400Y334000D03*
-X396400Y334000D03*
-X391400Y334000D03*
-X386400Y334000D03*
-X381400Y334000D03*
-X376400Y334000D03*
-X371400Y334000D03*
-X366400Y334000D03*
-X361400Y334000D03*
-X356400Y334000D03*
-X351400Y334000D03*
-X346400Y334000D03*
+G36*
+X436898Y602930D02*
+X434423Y600455D01*
+X423818Y611060D01*
+X426293Y613535D01*
+X436898Y602930D01*
+G37*
+G36*
+X433362Y599394D02*
+X430887Y596919D01*
+X420282Y607524D01*
+X422757Y609999D01*
+X433362Y599394D01*
+G37*
+G36*
+X429827Y595859D02*
+X427352Y593384D01*
+X416747Y603989D01*
+X419222Y606464D01*
+X429827Y595859D01*
+G37*
+G36*
+X426291Y592323D02*
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+G37*
+G36*
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+X420281Y586313D01*
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+G37*
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+G37*
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+G37*
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+G37*
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+G37*
 D13*
-X622300Y286004D02*
-X622300Y272796D01*
-X647700Y272796D02*
-X647700Y286004D01*
-X774700Y286004D02*
-X774700Y272796D01*
-X800100Y272796D02*
-X800100Y286004D01*
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-X673100Y272796D01*
-X698500Y272796D02*
-X698500Y286004D01*
-X749300Y286004D02*
-X749300Y272796D01*
-X723900Y272796D02*
-X723900Y286004D01*
-X825500Y286004D02*
-X825500Y272796D01*
-X850900Y272796D02*
-X850900Y286004D01*
-X876300Y286004D02*
-X876300Y272796D01*
-X901700Y272796D02*
-X901700Y286004D01*
-X927100Y286004D02*
-X927100Y272796D01*
-X952500Y272796D02*
-X952500Y286004D01*
-X952500Y348996D02*
-X952500Y362204D01*
-X927100Y362204D02*
-X927100Y348996D01*
-X901700Y348996D02*
-X901700Y362204D01*
-X876300Y362204D02*
-X876300Y348996D01*
-X850900Y348996D02*
-X850900Y362204D01*
-X825500Y362204D02*
-X825500Y348996D01*
-X800100Y348996D02*
-X800100Y362204D01*
-X774700Y362204D02*
-X774700Y348996D01*
-X749300Y348996D02*
-X749300Y362204D01*
-X723900Y362204D02*
-X723900Y348996D01*
-X698500Y348996D02*
-X698500Y362204D01*
-X673100Y362204D02*
-X673100Y348996D01*
-X647700Y348996D02*
-X647700Y362204D01*
-X622300Y362204D02*
-X622300Y348996D01*
+X152400Y622300D03*
+X152400Y546100D03*
+X127000Y622300D03*
+X127000Y546100D03*
 D14*
-X952500Y27940D03*
+X165100Y457200D03*
+X190500Y457200D03*
+X165100Y431800D03*
+X190500Y431800D03*
+X165100Y406400D03*
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+D13*
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+X292100Y431800D03*
+X215900Y431800D03*
+X292100Y406400D03*
+X215900Y406400D03*
 D15*
-X901700Y53340D03*
-X876300Y53340D03*
-X850900Y53340D03*
-X825500Y53340D03*
-X800100Y53340D03*
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-X673100Y53340D03*
-X647700Y53340D03*
-X622300Y53340D03*
-X596900Y53340D03*
-X571500Y53340D03*
-X546100Y53340D03*
-X520700Y53340D03*
-X495300Y53340D03*
-X469900Y53340D03*
-X444500Y53340D03*
-X419100Y53340D03*
-X393700Y53340D03*
-X368300Y53340D03*
-X342900Y53340D03*
-X317500Y53340D03*
-X292100Y53340D03*
-X266700Y53340D03*
-X241300Y53340D03*
-X215900Y53340D03*
-X190500Y53340D03*
-X165100Y53340D03*
-X139700Y53340D03*
-X114300Y53340D03*
-X901700Y104140D03*
-X876300Y104140D03*
-X850900Y104140D03*
-X825500Y104140D03*
-X800100Y104140D03*
-X774700Y104140D03*
-X749300Y104140D03*
-X723900Y104140D03*
-X698500Y104140D03*
-X673100Y104140D03*
-X647700Y104140D03*
-X622300Y104140D03*
-X596900Y104140D03*
-X571500Y104140D03*
-X546100Y104140D03*
-X520700Y104140D03*
-X495300Y104140D03*
-X469900Y104140D03*
-X444500Y104140D03*
-X419100Y104140D03*
-X393700Y104140D03*
-X368300Y104140D03*
-X342900Y104140D03*
-X317500Y104140D03*
-X292100Y104140D03*
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-X241300Y104140D03*
-X215900Y104140D03*
-X190500Y104140D03*
-X165100Y104140D03*
-X139700Y104140D03*
-X114300Y104140D03*
-D14*
-X63500Y27940D03*
-D15*
-X901700Y78740D03*
-X876300Y78740D03*
-X850900Y78740D03*
-X825500Y78740D03*
-X800100Y78740D03*
-X774700Y78740D03*
-X749300Y78740D03*
-X723900Y78740D03*
-X698500Y78740D03*
-X673100Y78740D03*
-X647700Y78740D03*
-X622300Y78740D03*
-X596900Y78740D03*
-X571500Y78740D03*
-X546100Y78740D03*
-X520700Y78740D03*
-X495300Y78740D03*
-X469900Y78740D03*
-X444500Y78740D03*
-X419100Y78740D03*
-X393700Y78740D03*
-X368300Y78740D03*
-X342900Y78740D03*
-X317500Y78740D03*
-X292100Y78740D03*
-X266700Y78740D03*
-X241300Y78740D03*
-X215900Y78740D03*
-X190500Y78740D03*
-X165100Y78740D03*
-X139700Y78740D03*
-X114300Y78740D03*
+X736600Y558640D03*
+X736600Y538640D03*
+X850900Y558640D03*
+X850900Y538640D03*
 D16*
-X152400Y355600D03*
-X152400Y279400D03*
-X228600Y279400D03*
-X228600Y355600D03*
+X244000Y502920D03*
+X264000Y502920D03*
+D15*
+X327660Y518000D03*
+X327660Y498000D03*
+X566420Y518000D03*
+X566420Y498000D03*
+D13*
+X619760Y457200D03*
+X599440Y457200D03*
+X327660Y558800D03*
+X307340Y558800D03*
 D17*
-X50800Y165100D03*
-X101600Y165100D03*
-X50800Y190500D03*
-X101600Y190500D03*
-X50800Y215900D03*
-X101600Y215900D03*
-X50800Y241300D03*
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+X393700Y636270D03*
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+X368300Y636270D03*
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+X342900Y636270D03*
+X317500Y661670D03*
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+X292100Y661670D03*
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+X63500Y546100D03*
+X88900Y571500D03*
+X63500Y571500D03*
+X88900Y596900D03*
+X63500Y596900D03*
+X88900Y622300D03*
+X63500Y622300D03*
+D13*
+X863600Y241300D03*
+X838200Y241300D03*
+X812800Y241300D03*
+X787400Y241300D03*
+X762000Y241300D03*
+X736600Y241300D03*
+X711200Y241300D03*
+X685800Y241300D03*
+X660400Y241300D03*
+X635000Y241300D03*
+X609600Y241300D03*
+X584200Y241300D03*
+X558800Y241300D03*
+X533400Y241300D03*
+X508000Y241300D03*
+X482600Y241300D03*
+X457200Y241300D03*
+X431800Y241300D03*
+X406400Y241300D03*
+X76200Y241300D03*
+X76200Y12700D03*
+X406400Y12700D03*
+X431800Y12700D03*
+X457200Y12700D03*
+X482600Y12700D03*
+X508000Y12700D03*
+X533400Y12700D03*
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+X584200Y12700D03*
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+X635000Y12700D03*
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+X863600Y12700D03*
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+X254000Y241300D03*
+X228600Y241300D03*
+X203200Y241300D03*
+X177800Y241300D03*
+X152400Y241300D03*
+X127000Y241300D03*
 X101600Y241300D03*
-X50800Y266700D03*
-X101600Y266700D03*
-X50800Y292100D03*
-X101600Y292100D03*
-D13*
-X622300Y159004D02*
-X622300Y145796D01*
-X647700Y145796D02*
-X647700Y159004D01*
-X774700Y159004D02*
-X774700Y145796D01*
-X800100Y145796D02*
-X800100Y159004D01*
-X673100Y159004D02*
-X673100Y145796D01*
-X698500Y145796D02*
-X698500Y159004D01*
-X749300Y159004D02*
-X749300Y145796D01*
-X723900Y145796D02*
-X723900Y159004D01*
-X825500Y159004D02*
-X825500Y145796D01*
-X850900Y145796D02*
-X850900Y159004D01*
-X876300Y159004D02*
-X876300Y145796D01*
-X901700Y145796D02*
-X901700Y159004D01*
-X927100Y159004D02*
-X927100Y145796D01*
-X952500Y145796D02*
-X952500Y159004D01*
-X952500Y221996D02*
-X952500Y235204D01*
-X927100Y235204D02*
-X927100Y221996D01*
-X901700Y221996D02*
-X901700Y235204D01*
-X876300Y235204D02*
-X876300Y221996D01*
-X850900Y221996D02*
-X850900Y235204D01*
-X825500Y235204D02*
-X825500Y221996D01*
-X800100Y221996D02*
-X800100Y235204D01*
-X774700Y235204D02*
-X774700Y221996D01*
-X749300Y221996D02*
-X749300Y235204D01*
-X723900Y235204D02*
-X723900Y221996D01*
-X698500Y221996D02*
-X698500Y235204D01*
-X673100Y235204D02*
-X673100Y221996D01*
-X647700Y221996D02*
-X647700Y235204D01*
-X622300Y235204D02*
-X622300Y221996D01*
+X381000Y12700D03*
+X355600Y12700D03*
+X330200Y12700D03*
+X304800Y12700D03*
+X279400Y12700D03*
+X254000Y12700D03*
+X228600Y12700D03*
+X203200Y12700D03*
+X177800Y12700D03*
+X152400Y12700D03*
+X127000Y12700D03*
+X101600Y12700D03*
 D18*
-X228600Y165100D03*
-X203200Y165100D03*
-X228600Y190500D03*
-X203200Y190500D03*
-X228600Y215900D03*
-X203200Y215900D03*
-D17*
-X127000Y165100D03*
-X177800Y165100D03*
-X127000Y190500D03*
-X177800Y190500D03*
-X127000Y215900D03*
-X177800Y215900D03*
-D13*
-X32004Y292100D02*
-X18796Y292100D01*
-X18796Y266700D02*
-X32004Y266700D01*
-X32004Y241300D02*
-X18796Y241300D01*
-X18796Y215900D02*
-X32004Y215900D01*
-X32004Y190500D02*
-X18796Y190500D01*
-X18796Y165100D02*
-X32004Y165100D01*
+X203200Y571500D03*
+X203200Y546100D03*
+D15*
+X203200Y515460D03*
+X203200Y495460D03*
+X203200Y602140D03*
+X203200Y622140D03*
 D19*
-X584200Y228600D03*
-X584200Y177800D03*
-X584200Y203200D03*
-X584200Y355600D03*
-X584200Y304800D03*
-X584200Y330200D03*
-X279400Y381000D03*
-X279400Y330200D03*
-X279400Y355600D03*
+X683050Y573000D03*
+X677550Y573000D03*
+X672050Y573000D03*
+X666550Y573000D03*
+X661050Y573000D03*
+X655550Y573000D03*
+X650050Y573000D03*
+X650050Y443000D03*
+X655550Y443000D03*
+X661050Y443000D03*
+X666550Y443000D03*
+X672050Y443000D03*
+X677550Y443000D03*
+X683050Y443000D03*
+X688550Y443000D03*
+X694050Y443000D03*
+X699550Y443000D03*
+X705050Y443000D03*
+X710550Y443000D03*
+X716050Y443000D03*
+X721550Y443000D03*
+X721550Y573000D03*
+X716050Y573000D03*
+X710550Y573000D03*
+X705050Y573000D03*
+X699550Y573000D03*
+X694050Y573000D03*
+X688550Y573000D03*
+X797350Y573000D03*
+X791850Y573000D03*
+X786350Y573000D03*
+X780850Y573000D03*
+X775350Y573000D03*
+X769850Y573000D03*
+X764350Y573000D03*
+X764350Y443000D03*
+X769850Y443000D03*
+X775350Y443000D03*
+X780850Y443000D03*
+X786350Y443000D03*
+X791850Y443000D03*
+X797350Y443000D03*
+X802850Y443000D03*
+X808350Y443000D03*
+X813850Y443000D03*
+X819350Y443000D03*
+X824850Y443000D03*
+X830350Y443000D03*
+X835850Y443000D03*
+X835850Y573000D03*
+X830350Y573000D03*
+X824850Y573000D03*
+X819350Y573000D03*
+X813850Y573000D03*
+X808350Y573000D03*
+X802850Y573000D03*
 D20*
-X457200Y368300D03*
-X406400Y368300D03*
-X431800Y368300D03*
-X381000Y368300D03*
-X330200Y368300D03*
-X355600Y368300D03*
-X977900Y101600D03*
-D16*
-X998220Y101600D03*
-D20*
-X977900Y378460D03*
-D16*
-X998220Y378460D03*
+X244500Y457200D03*
+X263500Y457200D03*
+X244500Y431800D03*
+X263500Y431800D03*
+X244500Y406400D03*
+X263500Y406400D03*
 D21*
-X520700Y304800D03*
-X546100Y304800D03*
-X520700Y279400D03*
-X546100Y279400D03*
-X520700Y254000D03*
-X546100Y254000D03*
-X520700Y228600D03*
-X546100Y228600D03*
-X520700Y203200D03*
-X546100Y203200D03*
+X152400Y574700D03*
+X152400Y593700D03*
+X127000Y574700D03*
+X127000Y593700D03*
+D13*
+X863600Y342900D03*
+X838200Y342900D03*
+X812800Y342900D03*
+X787400Y342900D03*
+X762000Y342900D03*
+X736600Y342900D03*
+X711200Y342900D03*
+X685800Y342900D03*
+X660400Y342900D03*
+X635000Y342900D03*
+X609600Y342900D03*
+X584200Y342900D03*
+X558800Y342900D03*
+X533400Y342900D03*
+X508000Y342900D03*
+X482600Y342900D03*
+X457200Y342900D03*
+X431800Y342900D03*
+X406400Y342900D03*
+X76200Y342900D03*
+X76200Y114300D03*
+X406400Y114300D03*
+X431800Y114300D03*
+X457200Y114300D03*
+X482600Y114300D03*
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+X533400Y114300D03*
+X558800Y114300D03*
+X584200Y114300D03*
+X609600Y114300D03*
+X635000Y114300D03*
+X660400Y114300D03*
+X685800Y114300D03*
+X711200Y114300D03*
+X736600Y114300D03*
+X762000Y114300D03*
+X787400Y114300D03*
+X812800Y114300D03*
+X838200Y114300D03*
+X863600Y114300D03*
+X381000Y342900D03*
+X355600Y342900D03*
+X330200Y342900D03*
+X304800Y342900D03*
+X279400Y342900D03*
+X254000Y342900D03*
+X228600Y342900D03*
+X203200Y342900D03*
+X177800Y342900D03*
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+X177800Y114300D03*
+X152400Y114300D03*
+X127000Y114300D03*
+X101600Y114300D03*
 D22*
-X584200Y228600D02*
-X622300Y228600D01*
-X622300Y355600D02*
-X584200Y355600D01*
+X876300Y38100D03*
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+X800100Y38100D03*
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+X571500Y38100D03*
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+X469900Y38100D03*
+X444500Y38100D03*
+X419100Y38100D03*
+X393700Y38100D03*
+X368300Y38100D03*
+X342900Y38100D03*
+X317500Y38100D03*
+X292100Y38100D03*
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+X241300Y38100D03*
+X215900Y38100D03*
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+X139700Y38100D03*
+X114300Y38100D03*
+X88900Y38100D03*
+X876300Y88900D03*
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+X825500Y88900D03*
+X800100Y88900D03*
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+X749300Y88900D03*
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+X546100Y88900D03*
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+X444500Y88900D03*
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+X241300Y88900D03*
+X215900Y88900D03*
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+X139700Y88900D03*
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+X88900Y88900D03*
+X876300Y63500D03*
+X850900Y63500D03*
+X825500Y63500D03*
+X800100Y63500D03*
+X774700Y63500D03*
+X749300Y63500D03*
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+X698500Y63500D03*
+X673100Y63500D03*
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+X622300Y63500D03*
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+X571500Y63500D03*
+X546100Y63500D03*
+X520700Y63500D03*
+X495300Y63500D03*
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+X190500Y63500D03*
+X165100Y63500D03*
+X139700Y63500D03*
+X114300Y63500D03*
+X88900Y63500D03*
 D23*
-X391400Y357900D02*
-X391400Y334000D01*
-X391400Y357900D02*
-X381000Y368300D01*
-X436400Y347500D02*
-X436400Y334000D01*
-X436400Y347500D02*
-X457200Y368300D01*
-X462520Y269000D02*
-X486400Y269000D01*
-X436400Y295120D02*
-X436400Y312420D01*
-X436400Y334000D01*
-X444500Y287020D02*
-X462520Y269000D01*
-X444500Y287020D02*
-X436400Y295120D01*
-X391400Y317260D02*
-X391400Y334000D01*
-X391400Y317260D02*
-X396240Y312420D01*
-X436400Y312420D01*
-X341160Y304000D02*
-X326400Y304000D01*
-X341160Y304000D02*
-X350520Y294640D01*
-X340760Y229000D02*
-X326400Y229000D01*
-X340760Y229000D02*
-X350520Y238760D01*
-X375920Y213360D02*
-X387350Y213360D01*
-X375920Y213360D02*
-X350520Y238760D01*
-X387350Y213360D02*
-X408940Y213360D01*
-X431800Y213360D01*
-X439420Y220980D01*
-X444500Y226060D01*
-X444500Y287020D01*
-X466400Y194000D02*
-X486400Y194000D01*
-X466400Y194000D02*
-X439420Y220980D01*
-X386400Y187010D02*
-X386400Y174000D01*
-X386400Y187010D02*
-X387350Y187960D01*
-X387350Y213360D01*
-X408940Y198120D02*
-X411400Y195660D01*
-X408940Y198120D02*
-X408940Y213360D01*
-X411400Y195660D02*
-X411400Y174000D01*
+X234950Y528066D03*
+X234950Y589534D03*
+X247650Y528066D03*
+X260350Y528066D03*
+X247650Y589534D03*
+X260350Y589534D03*
+X273050Y528066D03*
+X273050Y589534D03*
 D24*
-X350520Y294640D03*
-X350520Y287020D03*
-D23*
-X350520Y294640D01*
-D24*
-X350520Y238760D03*
-D23*
-X350520Y246380D01*
-D24*
-X350520Y246380D03*
-X254000Y198120D03*
-X340360Y289560D03*
-X340360Y264160D03*
-X340360Y238760D03*
-X378460Y347980D03*
-X370840Y314960D03*
-X358140Y314960D03*
-X358140Y304800D03*
-X335280Y325120D03*
-X325120Y325120D03*
-X416560Y320040D03*
-X415290Y347980D03*
-X429260Y320040D03*
-X444500Y320040D03*
-X502920Y299720D03*
-X495300Y332740D03*
-X558800Y330200D03*
-X472440Y236220D03*
-X472440Y259080D03*
-X467360Y203200D03*
-X449580Y220980D03*
-X444500Y205740D03*
-X429260Y205740D03*
-X401320Y205740D03*
-X401320Y223520D03*
-X370840Y228600D03*
-X355600Y223520D03*
-X337820Y180340D03*
-X345440Y190500D03*
-X596900Y177800D03*
-X571500Y177800D03*
-X497840Y170180D03*
-X563880Y213360D03*
-X553720Y170180D03*
-X558800Y304800D03*
-D23*
-X594360Y304800D01*
-D24*
-X558800Y279400D03*
-X574040Y279400D03*
-X601980Y279400D03*
-X629920Y325120D03*
-D23*
-X431400Y174000D02*
-X431400Y165970D01*
-X429260Y163830D01*
-X407670Y163830D02*
-X406400Y165100D01*
-X406400Y174000D01*
-X407670Y163830D02*
-X429260Y163830D01*
+X247650Y516890D02*
+X243840Y513080D01*
+X243840Y503080D01*
+X244000Y502920D01*
+X731520Y558800D02*
+X736440Y558800D01*
+X736600Y558640D01*
 D25*
-X406400Y193040D02*
-X401320Y198120D01*
-X401320Y205740D01*
-X406400Y193040D02*
-X406400Y174000D01*
+X688550Y561130D02*
+X688550Y573000D01*
+X688550Y561130D02*
+X693420Y556260D01*
+X698500Y556260D01*
+X701040Y558800D01*
+X731520Y558800D01*
+X822800Y558640D02*
+X850900Y558640D01*
+X822800Y558640D02*
+X815340Y551180D01*
+X807720Y551180D01*
+X802850Y556050D02*
+X802850Y573000D01*
+X802850Y556050D02*
+X807720Y551180D01*
+D26*
+X736600Y558640D02*
+X736600Y568960D01*
+D27*
+X736600Y568960D03*
+X741680Y574040D03*
+D26*
+X736600Y568960D01*
+D27*
+X845820Y574040D03*
+D26*
+X850900Y568960D01*
+D27*
+X850900Y568960D03*
+D26*
+X850900Y558640D01*
 D24*
-X685800Y317500D03*
-X711200Y317500D03*
-X734060Y317500D03*
-X647700Y200660D03*
-X647700Y180340D03*
-X673100Y200660D03*
-X673100Y180340D03*
-X698500Y180340D03*
-X698500Y200660D03*
-X904240Y198120D03*
-X904240Y185420D03*
-X622300Y200660D03*
-X894080Y172720D03*
-X873760Y180340D03*
-X873760Y200660D03*
-X927100Y210820D03*
-X924560Y185420D03*
-X596900Y157480D03*
-X553720Y157480D03*
-X568960Y353060D03*
-X495300Y353060D03*
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+X791850Y434970D01*
+X791850Y443000D01*
+X703580Y388620D02*
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+X544421Y537210D01*
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+D27*
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+D24*
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+X721360Y398780D01*
+D27*
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+D24*
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+D27*
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+D27*
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+X710550Y468010D01*
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+X710550Y432450D01*
+X728980Y414020D01*
+D27*
+X831850Y412750D03*
+X829310Y429260D03*
+D24*
+X830580Y414020D02*
+X831850Y412750D01*
+X830580Y414020D02*
+X728980Y414020D01*
+X824850Y433720D02*
+X824850Y443000D01*
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+X680720Y650240D02*
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+D27*
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+D24*
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+X228600Y241300D01*
+X226060Y340360D02*
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+X609600Y342900D02*
+X612140Y340360D01*
+X612140Y271780D01*
+X608330Y267970D01*
+X608330Y242570D01*
+X609600Y241300D01*
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+X279400Y342900D01*
+X309880Y246380D02*
+X304800Y241300D01*
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+X309880Y307340D01*
+X304800Y312420D01*
+X304800Y342900D01*
+X88900Y520700D02*
+X88900Y546100D01*
+X88900Y571500D01*
+X88900Y546100D02*
+X127000Y546100D01*
+X152400Y546100D01*
+X127000Y546100D02*
+X127000Y574700D01*
+X152400Y574700D02*
+X152400Y546100D01*
+X203200Y571500D02*
+X203200Y602140D01*
+X221234Y589534D02*
+X234950Y589534D01*
+X221234Y589534D02*
+X203200Y571500D01*
+X203200Y546100D02*
+X203200Y515460D01*
+X221234Y528066D02*
+X234950Y528066D01*
+X221234Y528066D02*
+X203200Y546100D01*
+D27*
+X259080Y561340D03*
+D24*
+X260350Y562610D02*
+X260350Y589534D01*
+X260350Y562610D02*
+X259080Y561340D01*
+D27*
+X251460Y556260D03*
+D24*
+X264160Y543560D01*
+X269240Y543560D02*
+X274320Y538480D01*
+X274320Y529336D01*
+X273050Y528066D01*
+X269240Y543560D02*
+X264160Y543560D01*
 M02*
diff --git a/Gerbers/drill_1_16.xln b/Gerbers/drill_1_16.xln
index ae5ae8b..90969b3 100644
--- a/Gerbers/drill_1_16.xln
+++ b/Gerbers/drill_1_16.xln
@@ -1,422 +1,829 @@
 M48
 ;GenerationSoftware,Autodesk,EAGLE,9.6.2*%
-;CreationDate,2021-05-01T19:58:20Z*%
+;CreationDate,2021-07-25T20:18:48Z*%
 FMAT,2
 ICI,OFF
 METRIC,TZ,000.000
-T5C0.300
+T6C0.300
+T5C0.400
 T4C0.813
 T3C0.914
-T2C1.016
-T1C2.794
+T2C1.000
+T1C1.016
 %
 G90
 M71
 T1
-X6350Y2794
-X95250Y2794
-X95250Y2794
-X6350Y2794
+X8890Y54610
+X8890Y62230
+X39370Y66167
+X39370Y63627
+X36830Y66167
+X36830Y63627
+X34290Y66167
+X34290Y63627
+X31750Y66167
+X31750Y63627
+X29210Y66167
+X29210Y63627
+X8890Y52070
+X6350Y52070
+X6350Y62230
+X6350Y54610
+X8890Y57150
+X6350Y57150
+X8890Y59690
+X6350Y59690
 T2
-X52070Y22860
-X52070Y20320
-X54610Y22860
-X54610Y25400
-X52070Y25400
-X54610Y27940
-X52070Y27940
-X54610Y30480
-X52070Y30480
-X54610Y20320
+X52070Y6350
+X49530Y6350
+X46990Y6350
+X44450Y6350
+X41910Y6350
+X39370Y6350
+X36830Y6350
+X34290Y6350
+X31750Y6350
+X29210Y6350
+X26670Y6350
+X24130Y6350
+X21590Y6350
+X19050Y6350
+X16510Y6350
+X13970Y6350
+X11430Y6350
+X11430Y8890
+X87630Y3810
+X85090Y3810
+X8890Y6350
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+X80010Y3810
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+X72390Y3810
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 T3
-X39370Y10414
-X41910Y10414
-X44450Y10414
-X46990Y10414
-X49530Y10414
-X52070Y10414
-X54610Y10414
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-X19050Y5334
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-X34290Y7874
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-X11430Y7874
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-X87630Y7874
+X16510Y43180
+X19050Y43180
+X16510Y40640
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+X16510Y45720
+X19050Y45720
 T4
-X5080Y19050
-X10160Y19050
-X5080Y21590
-X10160Y21590
-X5080Y24130
+X15240Y62230
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 X10160Y24130
-X5080Y26670
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-X5080Y29210
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-X64770Y15240
-X77470Y15240
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-X72390Y15240
-X82550Y15240
-X85090Y15240
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-X95250Y22860
-X92710Y22860
-X90170Y22860
-X87630Y22860
-X85090Y22860
-X82550Y22860
-X80010Y22860
-X77470Y22860
-X74930Y22860
-X72390Y22860
-X67310Y22860
-X64770Y22860
-X62230Y22860
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-X2540Y26670
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-X62230Y35560
-X15240Y35560
-X15240Y27940
-X22860Y27940
-X22860Y35560
-X5080Y16510
-X10160Y16510
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+X86360Y34290
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+X58420Y34290
+X55880Y34290
+X53340Y34290
+X50800Y34290
+X48260Y34290
+X45720Y34290
+X43180Y34290
+X40640Y34290
+X7620Y34290
+X7620Y11430
+X40640Y11430
+X43180Y11430
+X45720Y11430
+X48260Y11430
+X50800Y11430
+X15240Y34290
+X12700Y34290
+X10160Y34290
+X38100Y11430
+X53340Y11430
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+X33020Y11430
+X30480Y11430
+X27940Y11430
+X25400Y11430
+X22860Y11430
+X17780Y11430
+X15240Y11430
+X12700Y11430
+X10160Y11430
+X55880Y11430
+X58420Y11430
+X60960Y11430
+X63500Y11430
+X66040Y11430
+X68580Y11430
+X71120Y11430
+X73660Y11430
+X76200Y11430
+X78740Y11430
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+X86360Y11430
+X38100Y34290
+X35560Y34290
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+X30480Y34290
+X27940Y34290
+X25400Y34290
+X22860Y34290
+X20320Y34290
+X17780Y34290
+X20320Y11430
 T5
-X35052Y29464
-X35052Y28702
-X35052Y23876
-X35052Y24638
-X25400Y19812
-X34036Y28956
-X34036Y26416
-X34036Y23876
-X37846Y34798
-X37084Y31496
-X35814Y31496
-X35814Y30480
-X33528Y32512
-X32512Y32512
-X41656Y32004
-X41529Y34798
-X42926Y32004
-X44450Y32004
-X50292Y29972
-X49530Y33274
-X55880Y33020
-X47244Y23622
-X47244Y25908
-X46736Y20320
-X44958Y22098
-X44450Y20574
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diff --git a/Gerbers/profile.gbr b/Gerbers/profile.gbr
index 48c086d..2d3be47 100644
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 M02*
diff --git a/Gerbers/silkscreen_bottom.gbr b/Gerbers/silkscreen_bottom.gbr
index 8604eee..cca5ab7 100644
--- a/Gerbers/silkscreen_bottom.gbr
+++ b/Gerbers/silkscreen_bottom.gbr
@@ -9,2698 +9,9479 @@ G75*
 5,1,8,0,0,1.08239X$1,22.5*%
 G01*
 %ADD10C,0.177800*%
-%ADD11C,0.254000*%
-%ADD12C,0.203200*%
+%ADD11C,0.152400*%
+%ADD12C,0.076200*%
+%ADD13C,0.127000*%
+%ADD14C,0.000000*%
 
 
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 D11*
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 D12*
-X137378Y29210D02*
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-X137386Y29376D01*
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 M02*
diff --git a/Gerbers/silkscreen_top.gbr b/Gerbers/silkscreen_top.gbr
index 982edc6..8a88c21 100644
--- a/Gerbers/silkscreen_top.gbr
+++ b/Gerbers/silkscreen_top.gbr
@@ -11,18477 +11,23969 @@ G01*
 %ADD10C,0.203200*%
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 D12*
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-D11*
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 D13*
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 M02*
diff --git a/Gerbers/soldermask_bottom.gbr b/Gerbers/soldermask_bottom.gbr
index 1ac2831..a460f97 100644
--- a/Gerbers/soldermask_bottom.gbr
+++ b/Gerbers/soldermask_bottom.gbr
@@ -9,314 +9,292 @@ G75*
 5,1,8,0,0,1.08239X$1,22.5*%
 G01*
 %ADD10C,1.422400*%
-%ADD11C,5.181600*%
-%ADD12P,1.649562X8X292.500000*%
-%ADD13C,2.895600*%
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+%ADD12C,1.625600*%
+%ADD13C,1.009600*%
+%ADD14R,1.701800X1.270000*%
+%ADD15C,1.609600*%
 
 
 D10*
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 D12*
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 D10*
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 M02*
diff --git a/Gerbers/soldermask_top.gbr b/Gerbers/soldermask_top.gbr
index 9ac6fd8..834c912 100644
--- a/Gerbers/soldermask_top.gbr
+++ b/Gerbers/soldermask_top.gbr
@@ -11,418 +11,1091 @@ G01*
 %ADD10R,1.601600X0.451600*%
 %ADD11R,0.451600X1.601600*%
 %ADD12C,1.422400*%
-%ADD13C,5.181600*%
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+%ADD20R,1.601600X1.401600*%
+%ADD21C,1.609600*%
+%ADD22R,0.762000X2.133600*%
 
 
 D10*
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 D11*
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 D10*
-X486400Y194000D03*
-X486400Y199000D03*
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-X486400Y209000D03*
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-X486400Y294000D03*
-X486400Y299000D03*
-X486400Y304000D03*
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 D11*
-X466400Y334000D03*
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-X366400Y334000D03*
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-X356400Y334000D03*
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 D12*
-X622300Y286004D02*
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-X647700Y272796D02*
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-X800100Y348996D02*
-X800100Y362204D01*
-X774700Y362204D02*
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-X749300Y348996D02*
-X749300Y362204D01*
-X723900Y362204D02*
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-X622300Y362204D02*
-X622300Y348996D01*
+X152400Y622300D03*
+X152400Y546100D03*
+X127000Y622300D03*
+X127000Y546100D03*
 D13*
-X952500Y27940D03*
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+X190500Y431800D03*
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+D12*
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+X292100Y431800D03*
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+X292100Y406400D03*
+X215900Y406400D03*
 D14*
-X901700Y53340D03*
-X876300Y53340D03*
-X850900Y53340D03*
-X825500Y53340D03*
-X800100Y53340D03*
-X774700Y53340D03*
-X749300Y53340D03*
-X723900Y53340D03*
-X698500Y53340D03*
-X673100Y53340D03*
-X647700Y53340D03*
-X622300Y53340D03*
-X596900Y53340D03*
-X571500Y53340D03*
-X546100Y53340D03*
-X520700Y53340D03*
-X495300Y53340D03*
-X469900Y53340D03*
-X444500Y53340D03*
-X419100Y53340D03*
-X393700Y53340D03*
-X368300Y53340D03*
-X342900Y53340D03*
-X317500Y53340D03*
-X292100Y53340D03*
-X266700Y53340D03*
-X241300Y53340D03*
-X215900Y53340D03*
-X190500Y53340D03*
-X165100Y53340D03*
-X139700Y53340D03*
-X114300Y53340D03*
-X901700Y104140D03*
-X876300Y104140D03*
-X850900Y104140D03*
-X825500Y104140D03*
-X800100Y104140D03*
-X774700Y104140D03*
-X749300Y104140D03*
-X723900Y104140D03*
-X698500Y104140D03*
-X673100Y104140D03*
-X647700Y104140D03*
-X622300Y104140D03*
-X596900Y104140D03*
-X571500Y104140D03*
-X546100Y104140D03*
-X520700Y104140D03*
-X495300Y104140D03*
-X469900Y104140D03*
-X444500Y104140D03*
-X419100Y104140D03*
-X393700Y104140D03*
-X368300Y104140D03*
-X342900Y104140D03*
-X317500Y104140D03*
-X292100Y104140D03*
-X266700Y104140D03*
-X241300Y104140D03*
-X215900Y104140D03*
-X190500Y104140D03*
-X165100Y104140D03*
-X139700Y104140D03*
-X114300Y104140D03*
-D13*
-X63500Y27940D03*
-D14*
-X901700Y78740D03*
-X876300Y78740D03*
-X850900Y78740D03*
-X825500Y78740D03*
-X800100Y78740D03*
-X774700Y78740D03*
-X749300Y78740D03*
-X723900Y78740D03*
-X698500Y78740D03*
-X673100Y78740D03*
-X647700Y78740D03*
-X622300Y78740D03*
-X596900Y78740D03*
-X571500Y78740D03*
-X546100Y78740D03*
-X520700Y78740D03*
-X495300Y78740D03*
-X469900Y78740D03*
-X444500Y78740D03*
-X419100Y78740D03*
-X393700Y78740D03*
-X368300Y78740D03*
-X342900Y78740D03*
-X317500Y78740D03*
-X292100Y78740D03*
-X266700Y78740D03*
-X241300Y78740D03*
-X215900Y78740D03*
-X190500Y78740D03*
-X165100Y78740D03*
-X139700Y78740D03*
-X114300Y78740D03*
+X736600Y558640D03*
+X736600Y538640D03*
+X850900Y558640D03*
+X850900Y538640D03*
 D15*
-X952500Y27940D03*
-X63500Y27940D03*
+X244000Y502920D03*
+X264000Y502920D03*
+D14*
+X327660Y518000D03*
+X327660Y498000D03*
+X566420Y518000D03*
+X566420Y498000D03*
+D12*
+X619760Y457200D03*
+X599440Y457200D03*
+X327660Y558800D03*
+X307340Y558800D03*
 D16*
-X152400Y355600D03*
-X152400Y279400D03*
-X228600Y279400D03*
-X228600Y355600D03*
-D17*
-X50800Y165100D03*
-X101600Y165100D03*
-X50800Y190500D03*
-X101600Y190500D03*
-X50800Y215900D03*
-X101600Y215900D03*
-X50800Y241300D03*
+X393700Y661670D03*
+X393700Y636270D03*
+X368300Y661670D03*
+X368300Y636270D03*
+X342900Y661670D03*
+X342900Y636270D03*
+X317500Y661670D03*
+X317500Y636270D03*
+X292100Y661670D03*
+X292100Y636270D03*
+X88900Y520700D03*
+X63500Y520700D03*
+X88900Y546100D03*
+X63500Y546100D03*
+X88900Y571500D03*
+X63500Y571500D03*
+X88900Y596900D03*
+X63500Y596900D03*
+X88900Y622300D03*
+X63500Y622300D03*
+D12*
+X863600Y241300D03*
+X838200Y241300D03*
+X812800Y241300D03*
+X787400Y241300D03*
+X762000Y241300D03*
+X736600Y241300D03*
+X711200Y241300D03*
+X685800Y241300D03*
+X660400Y241300D03*
+X635000Y241300D03*
+X609600Y241300D03*
+X584200Y241300D03*
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+X533400Y241300D03*
+X508000Y241300D03*
+X482600Y241300D03*
+X457200Y241300D03*
+X431800Y241300D03*
+X406400Y241300D03*
+X76200Y241300D03*
+X76200Y12700D03*
+X406400Y12700D03*
+X431800Y12700D03*
+X457200Y12700D03*
+X482600Y12700D03*
+X508000Y12700D03*
+X533400Y12700D03*
+X558800Y12700D03*
+X584200Y12700D03*
+X609600Y12700D03*
+X635000Y12700D03*
+X660400Y12700D03*
+X685800Y12700D03*
+X711200Y12700D03*
+X736600Y12700D03*
+X762000Y12700D03*
+X787400Y12700D03*
+X812800Y12700D03*
+X838200Y12700D03*
+X863600Y12700D03*
+X381000Y241300D03*
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+X330200Y241300D03*
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+X279400Y241300D03*
+X254000Y241300D03*
+X228600Y241300D03*
+X203200Y241300D03*
+X177800Y241300D03*
+X152400Y241300D03*
+X127000Y241300D03*
 X101600Y241300D03*
-X50800Y266700D03*
-X101600Y266700D03*
-X50800Y292100D03*
-X101600Y292100D03*
-D12*
-X622300Y159004D02*
-X622300Y145796D01*
-X647700Y145796D02*
-X647700Y159004D01*
-X774700Y159004D02*
-X774700Y145796D01*
-X800100Y145796D02*
-X800100Y159004D01*
-X673100Y159004D02*
-X673100Y145796D01*
-X698500Y145796D02*
-X698500Y159004D01*
-X749300Y159004D02*
-X749300Y145796D01*
-X723900Y145796D02*
-X723900Y159004D01*
-X825500Y159004D02*
-X825500Y145796D01*
-X850900Y145796D02*
-X850900Y159004D01*
-X876300Y159004D02*
-X876300Y145796D01*
-X901700Y145796D02*
-X901700Y159004D01*
-X927100Y159004D02*
-X927100Y145796D01*
-X952500Y145796D02*
-X952500Y159004D01*
-X952500Y221996D02*
-X952500Y235204D01*
-X927100Y235204D02*
-X927100Y221996D01*
-X901700Y221996D02*
-X901700Y235204D01*
-X876300Y235204D02*
-X876300Y221996D01*
-X850900Y221996D02*
-X850900Y235204D01*
-X825500Y235204D02*
-X825500Y221996D01*
-X800100Y221996D02*
-X800100Y235204D01*
-X774700Y235204D02*
-X774700Y221996D01*
-X749300Y221996D02*
-X749300Y235204D01*
-X723900Y235204D02*
-X723900Y221996D01*
-X698500Y221996D02*
-X698500Y235204D01*
-X673100Y235204D02*
-X673100Y221996D01*
-X647700Y221996D02*
-X647700Y235204D01*
-X622300Y235204D02*
-X622300Y221996D01*
-D18*
-X228600Y165100D03*
-X203200Y165100D03*
-X228600Y190500D03*
-X203200Y190500D03*
-X228600Y215900D03*
-X203200Y215900D03*
+X381000Y12700D03*
+X355600Y12700D03*
+X330200Y12700D03*
+X304800Y12700D03*
+X279400Y12700D03*
+X254000Y12700D03*
+X228600Y12700D03*
+X203200Y12700D03*
+X177800Y12700D03*
+X152400Y12700D03*
+X127000Y12700D03*
+X101600Y12700D03*
 D17*
-X127000Y165100D03*
-X177800Y165100D03*
-X127000Y190500D03*
-X177800Y190500D03*
-X127000Y215900D03*
-X177800Y215900D03*
-D12*
-X32004Y292100D02*
-X18796Y292100D01*
-X18796Y266700D02*
-X32004Y266700D01*
-X32004Y241300D02*
-X18796Y241300D01*
-X18796Y215900D02*
-X32004Y215900D01*
-X32004Y190500D02*
-X18796Y190500D01*
-X18796Y165100D02*
-X32004Y165100D01*
+X203200Y571500D03*
+X203200Y546100D03*
+D14*
+X203200Y515460D03*
+X203200Y495460D03*
+X203200Y602140D03*
+X203200Y622140D03*
+D18*
+X683050Y573000D03*
+X677550Y573000D03*
+X672050Y573000D03*
+X666550Y573000D03*
+X661050Y573000D03*
+X655550Y573000D03*
+X650050Y573000D03*
+X650050Y443000D03*
+X655550Y443000D03*
+X661050Y443000D03*
+X666550Y443000D03*
+X672050Y443000D03*
+X677550Y443000D03*
+X683050Y443000D03*
+X688550Y443000D03*
+X694050Y443000D03*
+X699550Y443000D03*
+X705050Y443000D03*
+X710550Y443000D03*
+X716050Y443000D03*
+X721550Y443000D03*
+X721550Y573000D03*
+X716050Y573000D03*
+X710550Y573000D03*
+X705050Y573000D03*
+X699550Y573000D03*
+X694050Y573000D03*
+X688550Y573000D03*
+X797350Y573000D03*
+X791850Y573000D03*
+X786350Y573000D03*
+X780850Y573000D03*
+X775350Y573000D03*
+X769850Y573000D03*
+X764350Y573000D03*
+X764350Y443000D03*
+X769850Y443000D03*
+X775350Y443000D03*
+X780850Y443000D03*
+X786350Y443000D03*
+X791850Y443000D03*
+X797350Y443000D03*
+X802850Y443000D03*
+X808350Y443000D03*
+X813850Y443000D03*
+X819350Y443000D03*
+X824850Y443000D03*
+X830350Y443000D03*
+X835850Y443000D03*
+X835850Y573000D03*
+X830350Y573000D03*
+X824850Y573000D03*
+X819350Y573000D03*
+X813850Y573000D03*
+X808350Y573000D03*
+X802850Y573000D03*
 D19*
-X584200Y228600D03*
-X584200Y177800D03*
-X584200Y203200D03*
-X584200Y355600D03*
-X584200Y304800D03*
-X584200Y330200D03*
-X279400Y381000D03*
-X279400Y330200D03*
-X279400Y355600D03*
+X244500Y457200D03*
+X263500Y457200D03*
+X244500Y431800D03*
+X263500Y431800D03*
+X244500Y406400D03*
+X263500Y406400D03*
 D20*
-X457200Y368300D03*
-X406400Y368300D03*
-X431800Y368300D03*
-X381000Y368300D03*
-X330200Y368300D03*
-X355600Y368300D03*
-X977900Y101600D03*
-D16*
-X998220Y101600D03*
-D20*
-X977900Y378460D03*
-D16*
-X998220Y378460D03*
+X152400Y574700D03*
+X152400Y593700D03*
+X127000Y574700D03*
+X127000Y593700D03*
+D12*
+X863600Y342900D03*
+X838200Y342900D03*
+X812800Y342900D03*
+X787400Y342900D03*
+X762000Y342900D03*
+X736600Y342900D03*
+X711200Y342900D03*
+X685800Y342900D03*
+X660400Y342900D03*
+X635000Y342900D03*
+X609600Y342900D03*
+X584200Y342900D03*
+X558800Y342900D03*
+X533400Y342900D03*
+X508000Y342900D03*
+X482600Y342900D03*
+X457200Y342900D03*
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+X406400Y342900D03*
+X76200Y342900D03*
+X76200Y114300D03*
+X406400Y114300D03*
+X431800Y114300D03*
+X457200Y114300D03*
+X482600Y114300D03*
+X508000Y114300D03*
+X533400Y114300D03*
+X558800Y114300D03*
+X584200Y114300D03*
+X609600Y114300D03*
+X635000Y114300D03*
+X660400Y114300D03*
+X685800Y114300D03*
+X711200Y114300D03*
+X736600Y114300D03*
+X762000Y114300D03*
+X787400Y114300D03*
+X812800Y114300D03*
+X838200Y114300D03*
+X863600Y114300D03*
+X381000Y342900D03*
+X355600Y342900D03*
+X330200Y342900D03*
+X304800Y342900D03*
+X279400Y342900D03*
+X254000Y342900D03*
+X228600Y342900D03*
+X203200Y342900D03*
+X177800Y342900D03*
+X152400Y342900D03*
+X127000Y342900D03*
+X101600Y342900D03*
+X381000Y114300D03*
+X355600Y114300D03*
+X330200Y114300D03*
+X304800Y114300D03*
+X279400Y114300D03*
+X254000Y114300D03*
+X228600Y114300D03*
+X203200Y114300D03*
+X177800Y114300D03*
+X152400Y114300D03*
+X127000Y114300D03*
+X101600Y114300D03*
 D21*
-X520700Y304800D03*
-X546100Y304800D03*
-X520700Y279400D03*
-X546100Y279400D03*
-X520700Y254000D03*
-X546100Y254000D03*
-X520700Y228600D03*
-X546100Y228600D03*
-X520700Y203200D03*
-X546100Y203200D03*
+X876300Y38100D03*
+X850900Y38100D03*
+X825500Y38100D03*
+X800100Y38100D03*
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+X698500Y38100D03*
+X673100Y38100D03*
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+X622300Y38100D03*
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+X571500Y38100D03*
+X546100Y38100D03*
+X520700Y38100D03*
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+X444500Y38100D03*
+X419100Y38100D03*
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+X342900Y38100D03*
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+X114300Y38100D03*
+X88900Y38100D03*
+X876300Y88900D03*
+X850900Y88900D03*
+X825500Y88900D03*
+X800100Y88900D03*
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+X749300Y88900D03*
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+X698500Y88900D03*
+X673100Y88900D03*
+X647700Y88900D03*
+X622300Y88900D03*
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+X571500Y88900D03*
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+X444500Y88900D03*
+X419100Y88900D03*
+X393700Y88900D03*
+X368300Y88900D03*
+X342900Y88900D03*
+X317500Y88900D03*
+X292100Y88900D03*
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+X241300Y88900D03*
+X215900Y88900D03*
+X190500Y88900D03*
+X165100Y88900D03*
+X139700Y88900D03*
+X114300Y88900D03*
+X88900Y88900D03*
+X876300Y63500D03*
+X850900Y63500D03*
+X825500Y63500D03*
+X800100Y63500D03*
+X774700Y63500D03*
+X749300Y63500D03*
+X723900Y63500D03*
+X698500Y63500D03*
+X673100Y63500D03*
+X647700Y63500D03*
+X622300Y63500D03*
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+X571500Y63500D03*
+X546100Y63500D03*
+X520700Y63500D03*
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+X444500Y63500D03*
+X419100Y63500D03*
+X393700Y63500D03*
+X368300Y63500D03*
+X342900Y63500D03*
+X317500Y63500D03*
+X292100Y63500D03*
+X266700Y63500D03*
+X241300Y63500D03*
+X215900Y63500D03*
+X190500Y63500D03*
+X165100Y63500D03*
+X139700Y63500D03*
+X114300Y63500D03*
+X88900Y63500D03*
+D22*
+X234950Y528066D03*
+X234950Y589534D03*
+X247650Y528066D03*
+X260350Y528066D03*
+X247650Y589534D03*
+X260350Y589534D03*
+X273050Y528066D03*
+X273050Y589534D03*
 M02*
diff --git a/Gerbers/solderpaste_bottom.gbr b/Gerbers/solderpaste_bottom.gbr
index c4e40b8..eeec3a7 100644
--- a/Gerbers/solderpaste_bottom.gbr
+++ b/Gerbers/solderpaste_bottom.gbr
@@ -8,6 +8,14 @@ G75*
 %AMOC8*
 5,1,8,0,0,1.08239X$1,22.5*%
 G01*
+%ADD10R,1.600200X1.168400*%
 
 
+D10*
+X271780Y543560D03*
+X271780Y558800D03*
+X271780Y574040D03*
+X236220Y574040D03*
+X236220Y558800D03*
+X236220Y543560D03*
 M02*
diff --git a/Gerbers/solderpaste_top.gbr b/Gerbers/solderpaste_top.gbr
index 31b679b..3529a4d 100644
--- a/Gerbers/solderpaste_top.gbr
+++ b/Gerbers/solderpaste_top.gbr
@@ -10,110 +10,811 @@ G75*
 G01*
 %ADD10R,1.500000X0.350000*%
 %ADD11R,0.350000X1.500000*%
+%ADD12R,1.600000X1.300000*%
+%ADD13R,1.300000X1.600000*%
+%ADD14R,0.300000X1.000000*%
+%ADD15R,1.300000X1.500000*%
+%ADD16R,1.500000X1.300000*%
+%ADD17R,0.660400X2.032000*%
 
 
 D10*
-X326400Y314000D03*
-X326400Y309000D03*
-X326400Y304000D03*
-X326400Y299000D03*
-X326400Y294000D03*
-X326400Y289000D03*
-X326400Y284000D03*
-X326400Y279000D03*
-X326400Y274000D03*
-X326400Y269000D03*
-X326400Y264000D03*
-X326400Y259000D03*
-X326400Y254000D03*
-X326400Y249000D03*
-X326400Y244000D03*
-X326400Y239000D03*
-X326400Y234000D03*
-X326400Y229000D03*
-X326400Y224000D03*
-X326400Y219000D03*
-X326400Y214000D03*
-X326400Y209000D03*
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 M02*

From c4b11b0a4ba32db65839eac0efe3c39b56d55ae5 Mon Sep 17 00:00:00 2001
From: techav <76832805+techav-homebrew@users.noreply.github.com>
Date: Mon, 26 Jul 2021 22:23:40 -0500
Subject: [PATCH 02/14] Change multiplier part

Changed 512MLF to 511MLF due to EOL
---
 Gerbers/copper_bottom.gbr     | 47720 +++++++++++-------------
 Gerbers/copper_top.gbr        | 63989 ++++++++++++++------------------
 Gerbers/drill_1_16.xln        |   402 +-
 Gerbers/silkscreen_top.gbr    |  6185 ++-
 Gerbers/soldermask_bottom.gbr |    18 +-
 Gerbers/soldermask_top.gbr    |    41 +-
 Gerbers/solderpaste_top.gbr   |    18 +-
 README.md                     |    30 +-
 SE-VGA_Schematic.pdf          |   Bin 0 -> 42926 bytes
 9 files changed, 50971 insertions(+), 67432 deletions(-)
 create mode 100644 SE-VGA_Schematic.pdf

diff --git a/Gerbers/copper_bottom.gbr b/Gerbers/copper_bottom.gbr
index a8ec71e..2c36957 100644
--- a/Gerbers/copper_bottom.gbr
+++ b/Gerbers/copper_bottom.gbr
@@ -22,377 +22,105 @@ G01*
 %ADD21C,0.127000*%
 
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+X386267Y191367D01*
+X387733Y189901D01*
+X387762Y189880D01*
+X387772Y189869D01*
+X387776Y189867D01*
+X387796Y189845D01*
+X387859Y189813D01*
+X387917Y189772D01*
+X387958Y189762D01*
+X387996Y189742D01*
+X388085Y189729D01*
+X388134Y189716D01*
+X388155Y189719D01*
+X388181Y189715D01*
 X390399Y189715D01*
 X392915Y187199D01*
-X392915Y185244D01*
-X392927Y185146D01*
-X392930Y185047D01*
-X392947Y184989D01*
-X392955Y184929D01*
-X392991Y184837D01*
-X393019Y184741D01*
-X393049Y184689D01*
-X393072Y184633D01*
-X393130Y184553D01*
-X393180Y184468D01*
-X393246Y184392D01*
-X393258Y184376D01*
-X393268Y184368D01*
-X393286Y184347D01*
-X404541Y173092D01*
-X404619Y173032D01*
-X404691Y172964D01*
-X404744Y172935D01*
-X404792Y172898D01*
-X404883Y172858D01*
-X404970Y172810D01*
-X405028Y172795D01*
-X405084Y172771D01*
-X405182Y172756D01*
-X405277Y172731D01*
-X405378Y172725D01*
-X405398Y172721D01*
-X405410Y172723D01*
-X405438Y172721D01*
-X412442Y172721D01*
-X412579Y172738D01*
+X392915Y184981D01*
+X392922Y184939D01*
+X392920Y184897D01*
+X392942Y184830D01*
+X392954Y184760D01*
+X392976Y184724D01*
+X392989Y184683D01*
+X393043Y184611D01*
+X393069Y184567D01*
+X393085Y184554D01*
+X393101Y184533D01*
+X404727Y172907D01*
+X404761Y172882D01*
+X404790Y172851D01*
+X404853Y172819D01*
+X404911Y172778D01*
+X404952Y172768D01*
+X404990Y172748D01*
+X405079Y172735D01*
+X405128Y172722D01*
+X405149Y172725D01*
+X405175Y172721D01*
+X413975Y172721D01*
+X414063Y172736D01*
 G37*
 %LPC*%
 G36*
-X202044Y540289D02*
-X202044Y540289D01*
-X199909Y541174D01*
-X198274Y542809D01*
-X197389Y544944D01*
-X197389Y547256D01*
-X198274Y549391D01*
-X199909Y551026D01*
-X202044Y551911D01*
-X204356Y551911D01*
-X206491Y551026D01*
-X208126Y549391D01*
-X209011Y547256D01*
-X209011Y544944D01*
-X208126Y542809D01*
-X206491Y541174D01*
-X204356Y540289D01*
-X202044Y540289D01*
+X196964Y540289D02*
+X196964Y540289D01*
+X194828Y541174D01*
+X193194Y542808D01*
+X192309Y544944D01*
+X192309Y547256D01*
+X193194Y549392D01*
+X194828Y551026D01*
+X196964Y551911D01*
+X199276Y551911D01*
+X201412Y551026D01*
+X203046Y549392D01*
+X203931Y547256D01*
+X203931Y544944D01*
+X203046Y542808D01*
+X201412Y541174D01*
+X199276Y540289D01*
+X196964Y540289D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X202044Y565689D02*
-X202044Y565689D01*
-X199909Y566574D01*
-X198274Y568209D01*
-X197389Y570344D01*
-X197389Y572656D01*
-X198274Y574791D01*
-X199909Y576426D01*
-X202044Y577311D01*
-X204356Y577311D01*
-X206491Y576426D01*
-X208126Y574791D01*
-X209011Y572656D01*
-X209011Y570344D01*
-X208126Y568209D01*
-X206491Y566574D01*
-X204356Y565689D01*
-X202044Y565689D01*
+X196964Y565689D02*
+X196964Y565689D01*
+X194828Y566574D01*
+X193194Y568208D01*
+X192309Y570344D01*
+X192309Y572656D01*
+X193194Y574792D01*
+X194828Y576426D01*
+X196964Y577311D01*
+X199276Y577311D01*
+X201412Y576426D01*
+X203046Y574792D01*
+X203931Y572656D01*
+X203931Y570344D01*
+X203046Y568208D01*
+X201412Y566574D01*
+X199276Y565689D01*
+X196964Y565689D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X227885Y535177D02*
-X227885Y535177D01*
-X227238Y535350D01*
-X226659Y535685D01*
-X226186Y536158D01*
-X225851Y536737D01*
-X225678Y537384D01*
-X225678Y541021D01*
-X233564Y541021D01*
-X233681Y541036D01*
-X233681Y535177D01*
-X227885Y535177D01*
-G37*
-%LPD*%
-%LPC*%
-G36*
-X238759Y535177D02*
-X238759Y535177D01*
-X238759Y541027D01*
-X238776Y541027D01*
-X238876Y541021D01*
-X246762Y541021D01*
-X246762Y537384D01*
-X246589Y536737D01*
-X246254Y536158D01*
-X245781Y535685D01*
-X245202Y535350D01*
-X244555Y535177D01*
-X238759Y535177D01*
-G37*
-%LPD*%
-%LPC*%
-G36*
-X274319Y535177D02*
-X274319Y535177D01*
-X274319Y541021D01*
-X282322Y541021D01*
-X282322Y537384D01*
+X273049Y535177D02*
+X273049Y535177D01*
+X273049Y542291D01*
+X282322Y542291D01*
+X282322Y537383D01*
 X282149Y536737D01*
 X281814Y536158D01*
 X281341Y535685D01*
 X280762Y535350D01*
-X280115Y535177D01*
-X274319Y535177D01*
+X280116Y535177D01*
+X273049Y535177D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X263445Y535177D02*
-X263445Y535177D01*
+X263444Y535177D02*
+X263444Y535177D01*
 X262798Y535350D01*
 X262219Y535685D01*
 X261746Y536158D01*
 X261411Y536737D01*
-X261238Y537384D01*
-X261238Y541021D01*
-X269241Y541021D01*
-X269241Y535177D01*
-X263445Y535177D01*
+X261238Y537383D01*
+X261238Y542291D01*
+X270511Y542291D01*
+X270511Y535177D01*
+X263444Y535177D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X66039Y523239D02*
-X66039Y523239D01*
-X66039Y530559D01*
-X67400Y530116D01*
-X68825Y529390D01*
-X70119Y528450D01*
-X71250Y527319D01*
-X72190Y526025D01*
-X72916Y524600D01*
-X73359Y523239D01*
-X66039Y523239D01*
+X39369Y547369D02*
+X39369Y547369D01*
+X39369Y556186D01*
+X40479Y556011D01*
+X42000Y555516D01*
+X43425Y554790D01*
+X44719Y553850D01*
+X45850Y552719D01*
+X46790Y551425D01*
+X47516Y550000D01*
+X48011Y548479D01*
+X48186Y547369D01*
+X39369Y547369D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X66039Y548639D02*
-X66039Y548639D01*
-X66039Y555959D01*
-X67400Y555516D01*
-X68825Y554790D01*
-X70119Y553850D01*
-X71250Y552719D01*
-X72190Y551425D01*
-X72916Y550000D01*
-X73359Y548639D01*
-X66039Y548639D01*
+X39369Y598169D02*
+X39369Y598169D01*
+X39369Y606986D01*
+X40479Y606811D01*
+X42000Y606316D01*
+X43425Y605590D01*
+X44719Y604650D01*
+X45850Y603519D01*
+X46790Y602225D01*
+X47516Y600800D01*
+X48011Y599279D01*
+X48186Y598169D01*
+X39369Y598169D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X294639Y638809D02*
-X294639Y638809D01*
-X294639Y646129D01*
-X296000Y645686D01*
-X297425Y644960D01*
-X298719Y644020D01*
-X299850Y642889D01*
-X300790Y641595D01*
-X301516Y640170D01*
-X301959Y638809D01*
-X294639Y638809D01*
+X39369Y521969D02*
+X39369Y521969D01*
+X39369Y530786D01*
+X40479Y530611D01*
+X42000Y530116D01*
+X43425Y529390D01*
+X44719Y528450D01*
+X45850Y527319D01*
+X46790Y526025D01*
+X47516Y524600D01*
+X48011Y523079D01*
+X48186Y521969D01*
+X39369Y521969D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X66039Y624839D02*
-X66039Y624839D01*
-X66039Y632159D01*
-X67400Y631716D01*
-X68825Y630990D01*
-X70119Y630050D01*
-X71250Y628919D01*
-X72190Y627625D01*
-X72916Y626200D01*
-X73359Y624839D01*
-X66039Y624839D01*
+X39369Y623569D02*
+X39369Y623569D01*
+X39369Y632386D01*
+X40479Y632211D01*
+X42000Y631716D01*
+X43425Y630990D01*
+X44719Y630050D01*
+X45850Y628919D01*
+X46790Y627625D01*
+X47516Y626200D01*
+X48011Y624679D01*
+X48186Y623569D01*
+X39369Y623569D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X66039Y599439D02*
-X66039Y599439D01*
-X66039Y606759D01*
-X67400Y606316D01*
-X68825Y605590D01*
-X70119Y604650D01*
-X71250Y603519D01*
-X72190Y602225D01*
-X72916Y600800D01*
-X73359Y599439D01*
-X66039Y599439D01*
+X39369Y572769D02*
+X39369Y572769D01*
+X39369Y581586D01*
+X40479Y581411D01*
+X42000Y580916D01*
+X43425Y580190D01*
+X44719Y579250D01*
+X45850Y578119D01*
+X46790Y576825D01*
+X47516Y575400D01*
+X48011Y573879D01*
+X48186Y572769D01*
+X39369Y572769D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X66039Y574039D02*
-X66039Y574039D01*
-X66039Y581359D01*
-X67400Y580916D01*
-X68825Y580190D01*
-X70119Y579250D01*
-X71250Y578119D01*
-X72190Y576825D01*
-X72916Y575400D01*
-X73359Y574039D01*
-X66039Y574039D01*
+X39369Y595631D02*
+X39369Y595631D01*
+X48186Y595631D01*
+X48011Y594521D01*
+X47516Y593000D01*
+X46790Y591575D01*
+X45850Y590281D01*
+X44719Y589150D01*
+X43425Y588210D01*
+X42000Y587484D01*
+X40479Y586989D01*
+X39369Y586814D01*
+X39369Y595631D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X53641Y548639D02*
-X53641Y548639D01*
-X54084Y550000D01*
-X54810Y551425D01*
-X55750Y552719D01*
-X56881Y553850D01*
-X58175Y554790D01*
-X59600Y555516D01*
-X60961Y555959D01*
-X60961Y548639D01*
-X53641Y548639D01*
-G37*
-%LPD*%
-%LPC*%
-G36*
-X66039Y568961D02*
-X66039Y568961D01*
-X73359Y568961D01*
-X72916Y567600D01*
-X72190Y566175D01*
-X71250Y564881D01*
-X70119Y563750D01*
-X68825Y562810D01*
-X67400Y562084D01*
-X66039Y561641D01*
-X66039Y568961D01*
-G37*
-%LPD*%
-%LPC*%
-G36*
-X53641Y624839D02*
-X53641Y624839D01*
-X54084Y626200D01*
-X54810Y627625D01*
-X55750Y628919D01*
-X56881Y630050D01*
-X58175Y630990D01*
-X59600Y631716D01*
-X60961Y632159D01*
-X60961Y624839D01*
-X53641Y624839D01*
-G37*
-%LPD*%
-%LPC*%
-G36*
-X53641Y574039D02*
-X53641Y574039D01*
-X54084Y575400D01*
-X54810Y576825D01*
-X55750Y578119D01*
-X56881Y579250D01*
-X58175Y580190D01*
-X59600Y580916D01*
-X60961Y581359D01*
-X60961Y574039D01*
-X53641Y574039D01*
-G37*
-%LPD*%
-%LPC*%
-G36*
-X66039Y594361D02*
-X66039Y594361D01*
-X73359Y594361D01*
-X72916Y593000D01*
-X72190Y591575D01*
-X71250Y590281D01*
-X70119Y589150D01*
-X68825Y588210D01*
-X67400Y587484D01*
-X66039Y587041D01*
-X66039Y594361D01*
-G37*
-%LPD*%
-%LPC*%
-G36*
-X53641Y599439D02*
-X53641Y599439D01*
-X54084Y600800D01*
-X54810Y602225D01*
-X55750Y603519D01*
-X56881Y604650D01*
-X58175Y605590D01*
-X59600Y606316D01*
-X60961Y606759D01*
-X60961Y599439D01*
-X53641Y599439D01*
-G37*
-%LPD*%
-%LPC*%
-G36*
-X66039Y619761D02*
-X66039Y619761D01*
-X73359Y619761D01*
-X72916Y618400D01*
-X72190Y616975D01*
-X71250Y615681D01*
-X70119Y614550D01*
-X68825Y613610D01*
-X67400Y612884D01*
-X66039Y612441D01*
-X66039Y619761D01*
-G37*
-%LPD*%
-%LPC*%
-G36*
-X66039Y518161D02*
-X66039Y518161D01*
-X73359Y518161D01*
-X72916Y516800D01*
-X72190Y515375D01*
-X71250Y514081D01*
-X70119Y512950D01*
-X68825Y512010D01*
-X67400Y511284D01*
-X66039Y510841D01*
-X66039Y518161D01*
-G37*
-%LPD*%
-%LPC*%
-G36*
-X53641Y523239D02*
-X53641Y523239D01*
-X54084Y524600D01*
-X54810Y526025D01*
-X55750Y527319D01*
-X56881Y528450D01*
-X58175Y529390D01*
-X59600Y530116D01*
-X60961Y530559D01*
-X60961Y523239D01*
-X53641Y523239D01*
-G37*
-%LPD*%
-%LPC*%
-G36*
-X66039Y543561D02*
-X66039Y543561D01*
-X73359Y543561D01*
-X72916Y542200D01*
-X72190Y540775D01*
-X71250Y539481D01*
-X70119Y538350D01*
-X68825Y537410D01*
-X67400Y536684D01*
-X66039Y536241D01*
-X66039Y543561D01*
-G37*
-%LPD*%
-%LPC*%
-G36*
-X282241Y638809D02*
-X282241Y638809D01*
-X282684Y640170D01*
-X283410Y641595D01*
-X284350Y642889D01*
-X285481Y644020D01*
-X286775Y644960D01*
-X288200Y645686D01*
-X289561Y646129D01*
-X289561Y638809D01*
-X282241Y638809D01*
-G37*
-%LPD*%
-%LPC*%
-G36*
-X294639Y633731D02*
-X294639Y633731D01*
-X301959Y633731D01*
-X301516Y632370D01*
-X300790Y630945D01*
-X299850Y629651D01*
-X298719Y628520D01*
-X297425Y627580D01*
-X296000Y626854D01*
-X294639Y626411D01*
-X294639Y633731D01*
-G37*
-%LPD*%
-%LPC*%
-G36*
-X396239Y633731D02*
-X396239Y633731D01*
-X403559Y633731D01*
+X394969Y635001D02*
+X394969Y635001D01*
+X403786Y635001D01*
+X403611Y633891D01*
 X403116Y632370D01*
 X402390Y630945D01*
 X401450Y629651D01*
 X400319Y628520D01*
 X399025Y627580D01*
 X397600Y626854D01*
-X396239Y626411D01*
-X396239Y633731D01*
+X396079Y626359D01*
+X394969Y626184D01*
+X394969Y635001D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X59600Y587484D02*
-X59600Y587484D01*
-X58175Y588210D01*
-X56881Y589150D01*
-X55750Y590281D01*
-X54810Y591575D01*
-X54084Y593000D01*
-X53641Y594361D01*
-X60961Y594361D01*
-X60961Y587041D01*
-X59600Y587484D01*
+X39369Y621031D02*
+X39369Y621031D01*
+X48186Y621031D01*
+X48011Y619921D01*
+X47516Y618400D01*
+X46790Y616975D01*
+X45850Y615681D01*
+X44719Y614550D01*
+X43425Y613610D01*
+X42000Y612884D01*
+X40479Y612389D01*
+X39369Y612214D01*
+X39369Y621031D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X59600Y511284D02*
-X59600Y511284D01*
-X58175Y512010D01*
-X56881Y512950D01*
-X55750Y514081D01*
-X54810Y515375D01*
-X54084Y516800D01*
-X53641Y518161D01*
-X60961Y518161D01*
-X60961Y510841D01*
-X59600Y511284D01*
+X39369Y570231D02*
+X39369Y570231D01*
+X48186Y570231D01*
+X48011Y569121D01*
+X47516Y567600D01*
+X46790Y566175D01*
+X45850Y564881D01*
+X44719Y563750D01*
+X43425Y562810D01*
+X42000Y562084D01*
+X40479Y561589D01*
+X39369Y561414D01*
+X39369Y570231D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X59600Y536684D02*
-X59600Y536684D01*
-X58175Y537410D01*
-X56881Y538350D01*
-X55750Y539481D01*
-X54810Y540775D01*
-X54084Y542200D01*
-X53641Y543561D01*
-X60961Y543561D01*
-X60961Y536241D01*
-X59600Y536684D01*
+X28014Y521969D02*
+X28014Y521969D01*
+X28189Y523079D01*
+X28684Y524600D01*
+X29410Y526025D01*
+X30350Y527319D01*
+X31481Y528450D01*
+X32775Y529390D01*
+X34200Y530116D01*
+X35721Y530611D01*
+X36831Y530786D01*
+X36831Y521969D01*
+X28014Y521969D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X59600Y612884D02*
-X59600Y612884D01*
-X58175Y613610D01*
-X56881Y614550D01*
-X55750Y615681D01*
-X54810Y616975D01*
-X54084Y618400D01*
-X53641Y619761D01*
-X60961Y619761D01*
-X60961Y612441D01*
-X59600Y612884D01*
+X39369Y544831D02*
+X39369Y544831D01*
+X48186Y544831D01*
+X48011Y543721D01*
+X47516Y542200D01*
+X46790Y540775D01*
+X45850Y539481D01*
+X44719Y538350D01*
+X43425Y537410D01*
+X42000Y536684D01*
+X40479Y536189D01*
+X39369Y536014D01*
+X39369Y544831D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X288200Y626854D02*
+X28014Y623569D02*
+X28014Y623569D01*
+X28189Y624679D01*
+X28684Y626200D01*
+X29410Y627625D01*
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+X32775Y630990D01*
+X34200Y631716D01*
+X35721Y632211D01*
+X36831Y632386D01*
+X36831Y623569D01*
+X28014Y623569D01*
+G37*
+%LPD*%
+%LPC*%
+G36*
+X28014Y572769D02*
+X28014Y572769D01*
+X28189Y573879D01*
+X28684Y575400D01*
+X29410Y576825D01*
+X30350Y578119D01*
+X31481Y579250D01*
+X32775Y580190D01*
+X34200Y580916D01*
+X35721Y581411D01*
+X36831Y581586D01*
+X36831Y572769D01*
+X28014Y572769D01*
+G37*
+%LPD*%
+%LPC*%
+G36*
+X39369Y519431D02*
+X39369Y519431D01*
+X48186Y519431D01*
+X48011Y518321D01*
+X47516Y516800D01*
+X46790Y515375D01*
+X45850Y514081D01*
+X44719Y512950D01*
+X43425Y512010D01*
+X42000Y511284D01*
+X40479Y510789D01*
+X39369Y510614D01*
+X39369Y519431D01*
+G37*
+%LPD*%
+%LPC*%
+G36*
+X28014Y547369D02*
+X28014Y547369D01*
+X28189Y548479D01*
+X28684Y550000D01*
+X29410Y551425D01*
+X30350Y552719D01*
+X31481Y553850D01*
+X32775Y554790D01*
+X34200Y555516D01*
+X35721Y556011D01*
+X36831Y556186D01*
+X36831Y547369D01*
+X28014Y547369D01*
+G37*
+%LPD*%
+%LPC*%
+G36*
+X28014Y598169D02*
+X28014Y598169D01*
+X28189Y599279D01*
+X28684Y600800D01*
+X29410Y602225D01*
+X30350Y603519D01*
+X31481Y604650D01*
+X32775Y605590D01*
+X34200Y606316D01*
+X35721Y606811D01*
+X36831Y606986D01*
+X36831Y598169D01*
+X28014Y598169D01*
+G37*
+%LPD*%
+%LPC*%
+G36*
+X282014Y637539D02*
+X282014Y637539D01*
+X282189Y638649D01*
+X282684Y640170D01*
+X283410Y641595D01*
+X284350Y642889D01*
+X285481Y644020D01*
+X286775Y644960D01*
+X288200Y645686D01*
+X289721Y646181D01*
+X290831Y646356D01*
+X290831Y637539D01*
+X282014Y637539D01*
+G37*
+%LPD*%
+%LPC*%
+G36*
+X35721Y586989D02*
+X35721Y586989D01*
+X34200Y587484D01*
+X32775Y588210D01*
+X31481Y589150D01*
+X30350Y590281D01*
+X29410Y591575D01*
+X28684Y593000D01*
+X28189Y594521D01*
+X28014Y595631D01*
+X36831Y595631D01*
+X36831Y586814D01*
+X35721Y586989D01*
+G37*
+%LPD*%
+%LPC*%
+G36*
+X35721Y510789D02*
+X35721Y510789D01*
+X34200Y511284D01*
+X32775Y512010D01*
+X31481Y512950D01*
+X30350Y514081D01*
+X29410Y515375D01*
+X28684Y516800D01*
+X28189Y518321D01*
+X28014Y519431D01*
+X36831Y519431D01*
+X36831Y510614D01*
+X35721Y510789D01*
+G37*
+%LPD*%
+%LPC*%
+G36*
+X35721Y536189D02*
+X35721Y536189D01*
+X34200Y536684D01*
+X32775Y537410D01*
+X31481Y538350D01*
+X30350Y539481D01*
+X29410Y540775D01*
+X28684Y542200D01*
+X28189Y543721D01*
+X28014Y544831D01*
+X36831Y544831D01*
+X36831Y536014D01*
+X35721Y536189D01*
+G37*
+%LPD*%
+%LPC*%
+G36*
+X391321Y626359D02*
+X391321Y626359D01*
+X389800Y626854D01*
+X388375Y627580D01*
+X387081Y628520D01*
+X385950Y629651D01*
+X385010Y630945D01*
+X384284Y632370D01*
+X383789Y633891D01*
+X383614Y635001D01*
+X392431Y635001D01*
+X392431Y626184D01*
+X391321Y626359D01*
+G37*
+%LPD*%
+%LPC*%
+G36*
+X289721Y626359D02*
+X289721Y626359D01*
 X288200Y626854D01*
 X286775Y627580D01*
 X285481Y628520D01*
 X284350Y629651D01*
 X283410Y630945D01*
 X282684Y632370D01*
-X282241Y633731D01*
-X289561Y633731D01*
-X289561Y626411D01*
-X288200Y626854D01*
+X282189Y633891D01*
+X282014Y635001D01*
+X290831Y635001D01*
+X290831Y626184D01*
+X289721Y626359D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X59600Y562084D02*
-X59600Y562084D01*
-X58175Y562810D01*
-X56881Y563750D01*
-X55750Y564881D01*
-X54810Y566175D01*
-X54084Y567600D01*
-X53641Y568961D01*
-X60961Y568961D01*
-X60961Y561641D01*
-X59600Y562084D01*
+X35721Y561589D02*
+X35721Y561589D01*
+X34200Y562084D01*
+X32775Y562810D01*
+X31481Y563750D01*
+X30350Y564881D01*
+X29410Y566175D01*
+X28684Y567600D01*
+X28189Y569121D01*
+X28014Y570231D01*
+X36831Y570231D01*
+X36831Y561414D01*
+X35721Y561589D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X878799Y65999D02*
-X878799Y65999D01*
-X878799Y73287D01*
-X880170Y72842D01*
-X881583Y72122D01*
-X882867Y71189D01*
-X883989Y70067D01*
-X884922Y68783D01*
-X885642Y67370D01*
-X886087Y65999D01*
-X878799Y65999D01*
+X35721Y612389D02*
+X35721Y612389D01*
+X34200Y612884D01*
+X32775Y613610D01*
+X31481Y614550D01*
+X30350Y615681D01*
+X29410Y616975D01*
+X28684Y618400D01*
+X28189Y619921D01*
+X28014Y621031D01*
+X36831Y621031D01*
+X36831Y612214D01*
+X35721Y612389D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X853399Y65999D02*
-X853399Y65999D01*
-X853399Y73287D01*
-X854770Y72842D01*
-X856183Y72122D01*
-X857467Y71189D01*
-X858589Y70067D01*
-X859522Y68783D01*
-X860242Y67370D01*
-X860687Y65999D01*
-X853399Y65999D01*
-G37*
-%LPD*%
-%LPC*%
-G36*
-X827999Y65999D02*
-X827999Y65999D01*
-X827999Y73287D01*
+X826769Y64769D02*
+X826769Y64769D01*
+X826769Y73505D01*
+X827860Y73333D01*
 X829370Y72842D01*
 X830783Y72122D01*
 X832067Y71189D01*
 X833189Y70067D01*
 X834122Y68783D01*
 X834842Y67370D01*
-X835287Y65999D01*
-X827999Y65999D01*
+X835333Y65860D01*
+X835505Y64769D01*
+X826769Y64769D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X802599Y65999D02*
-X802599Y65999D01*
-X802599Y73287D01*
+X852169Y64769D02*
+X852169Y64769D01*
+X852169Y73505D01*
+X853260Y73333D01*
+X854770Y72842D01*
+X856183Y72122D01*
+X857467Y71189D01*
+X858589Y70067D01*
+X859522Y68783D01*
+X860242Y67370D01*
+X860733Y65860D01*
+X860905Y64769D01*
+X852169Y64769D01*
+G37*
+%LPD*%
+%LPC*%
+G36*
+X877569Y64769D02*
+X877569Y64769D01*
+X877569Y73505D01*
+X878660Y73333D01*
+X880170Y72842D01*
+X881583Y72122D01*
+X882867Y71189D01*
+X883989Y70067D01*
+X884922Y68783D01*
+X885642Y67370D01*
+X886133Y65860D01*
+X886305Y64769D01*
+X877569Y64769D01*
+G37*
+%LPD*%
+%LPC*%
+G36*
+X801369Y64769D02*
+X801369Y64769D01*
+X801369Y73505D01*
+X802460Y73333D01*
 X803970Y72842D01*
 X805383Y72122D01*
 X806667Y71189D01*
 X807789Y70067D01*
 X808722Y68783D01*
 X809442Y67370D01*
-X809887Y65999D01*
-X802599Y65999D01*
+X809933Y65860D01*
+X810105Y64769D01*
+X801369Y64769D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X802599Y61001D02*
-X802599Y61001D01*
-X809887Y61001D01*
-X809442Y59630D01*
-X808722Y58217D01*
-X807789Y56933D01*
-X806667Y55811D01*
-X805383Y54878D01*
-X803970Y54158D01*
-X802599Y53713D01*
-X802599Y61001D01*
-G37*
-%LPD*%
-%LPC*%
-G36*
-X878799Y61001D02*
-X878799Y61001D01*
-X886087Y61001D01*
-X885642Y59630D01*
-X884922Y58217D01*
-X883989Y56933D01*
-X882867Y55811D01*
-X881583Y54878D01*
-X880170Y54158D01*
-X878799Y53713D01*
-X878799Y61001D01*
-G37*
-%LPD*%
-%LPC*%
-G36*
-X853399Y61001D02*
-X853399Y61001D01*
-X860687Y61001D01*
+X852169Y62231D02*
+X852169Y62231D01*
+X860905Y62231D01*
+X860733Y61140D01*
 X860242Y59630D01*
 X859522Y58217D01*
 X858589Y56933D01*
 X857467Y55811D01*
 X856183Y54878D01*
 X854770Y54158D01*
-X853399Y53713D01*
-X853399Y61001D01*
+X853260Y53667D01*
+X852169Y53495D01*
+X852169Y62231D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X827999Y61001D02*
-X827999Y61001D01*
-X835287Y61001D01*
-X834842Y59630D01*
-X834122Y58217D01*
-X833189Y56933D01*
-X832067Y55811D01*
-X830783Y54878D01*
-X829370Y54158D01*
-X827999Y53713D01*
-X827999Y61001D01*
+X801369Y62231D02*
+X801369Y62231D01*
+X810105Y62231D01*
+X809933Y61140D01*
+X809442Y59630D01*
+X808722Y58217D01*
+X807789Y56933D01*
+X806667Y55811D01*
+X805383Y54878D01*
+X803970Y54158D01*
+X802460Y53667D01*
+X801369Y53495D01*
+X801369Y62231D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X815713Y65999D02*
-X815713Y65999D01*
+X815495Y64769D02*
+X815495Y64769D01*
+X815667Y65860D01*
 X816158Y67370D01*
 X816878Y68783D01*
 X817811Y70067D01*
 X818933Y71189D01*
 X820217Y72122D01*
 X821630Y72842D01*
-X823001Y73287D01*
-X823001Y65999D01*
-X815713Y65999D01*
+X823140Y73333D01*
+X824231Y73505D01*
+X824231Y64769D01*
+X815495Y64769D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X841113Y65999D02*
-X841113Y65999D01*
+X840895Y64769D02*
+X840895Y64769D01*
+X841067Y65860D01*
 X841558Y67370D01*
 X842278Y68783D01*
 X843211Y70067D01*
 X844333Y71189D01*
 X845617Y72122D01*
 X847030Y72842D01*
-X848401Y73287D01*
-X848401Y65999D01*
-X841113Y65999D01*
+X848540Y73333D01*
+X849631Y73505D01*
+X849631Y64769D01*
+X840895Y64769D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X866513Y65999D02*
-X866513Y65999D01*
+X877569Y62231D02*
+X877569Y62231D01*
+X886305Y62231D01*
+X886133Y61140D01*
+X885642Y59630D01*
+X884922Y58217D01*
+X883989Y56933D01*
+X882867Y55811D01*
+X881583Y54878D01*
+X880170Y54158D01*
+X878660Y53667D01*
+X877569Y53495D01*
+X877569Y62231D01*
+G37*
+%LPD*%
+%LPC*%
+G36*
+X826769Y62231D02*
+X826769Y62231D01*
+X835505Y62231D01*
+X835333Y61140D01*
+X834842Y59630D01*
+X834122Y58217D01*
+X833189Y56933D01*
+X832067Y55811D01*
+X830783Y54878D01*
+X829370Y54158D01*
+X827860Y53667D01*
+X826769Y53495D01*
+X826769Y62231D01*
+G37*
+%LPD*%
+%LPC*%
+G36*
+X866295Y64769D02*
+X866295Y64769D01*
+X866467Y65860D01*
 X866958Y67370D01*
 X867678Y68783D01*
 X868611Y70067D01*
 X869733Y71189D01*
 X871017Y72122D01*
 X872430Y72842D01*
-X873801Y73287D01*
-X873801Y65999D01*
-X866513Y65999D01*
+X873940Y73333D01*
+X875031Y73505D01*
+X875031Y64769D01*
+X866295Y64769D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X821630Y54158D02*
-X821630Y54158D01*
-X820217Y54878D01*
-X818933Y55811D01*
-X817811Y56933D01*
-X816878Y58217D01*
-X816158Y59630D01*
-X815713Y61001D01*
-X823001Y61001D01*
-X823001Y53713D01*
-X821630Y54158D01*
-G37*
-%LPD*%
-%LPC*%
-G36*
-X872430Y54158D02*
-X872430Y54158D01*
-X871017Y54878D01*
-X869733Y55811D01*
-X868611Y56933D01*
-X867678Y58217D01*
-X866958Y59630D01*
-X866513Y61001D01*
-X873801Y61001D01*
-X873801Y53713D01*
-X872430Y54158D01*
-G37*
-%LPD*%
-%LPC*%
-G36*
-X847030Y54158D02*
+X848540Y53667D02*
+X848540Y53667D01*
 X847030Y54158D01*
 X845617Y54878D01*
 X844333Y55811D01*
 X843211Y56933D01*
 X842278Y58217D01*
 X841558Y59630D01*
-X841113Y61001D01*
-X848401Y61001D01*
-X848401Y53713D01*
-X847030Y54158D01*
+X841067Y61140D01*
+X840895Y62231D01*
+X849631Y62231D01*
+X849631Y53495D01*
+X848540Y53667D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X294131Y408431D02*
-X294131Y408431D01*
-X294131Y415337D01*
-X294241Y415320D01*
-X295610Y414875D01*
-X296893Y414221D01*
-X298057Y413375D01*
-X299075Y412357D01*
-X299921Y411193D01*
-X300575Y409910D01*
-X301020Y408541D01*
-X301037Y408431D01*
-X294131Y408431D01*
+X873940Y53667D02*
+X873940Y53667D01*
+X872430Y54158D01*
+X871017Y54878D01*
+X869733Y55811D01*
+X868611Y56933D01*
+X867678Y58217D01*
+X866958Y59630D01*
+X866467Y61140D01*
+X866295Y62231D01*
+X875031Y62231D01*
+X875031Y53495D01*
+X873940Y53667D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X621791Y459231D02*
-X621791Y459231D01*
-X621791Y466137D01*
-X621901Y466120D01*
-X623270Y465675D01*
-X624553Y465021D01*
-X625717Y464175D01*
-X626735Y463157D01*
-X627581Y461993D01*
-X628235Y460710D01*
-X628680Y459341D01*
-X628697Y459231D01*
-X621791Y459231D01*
+X823140Y53667D02*
+X823140Y53667D01*
+X821630Y54158D01*
+X820217Y54878D01*
+X818933Y55811D01*
+X817811Y56933D01*
+X816878Y58217D01*
+X816158Y59630D01*
+X815667Y61140D01*
+X815495Y62231D01*
+X824231Y62231D01*
+X824231Y53495D01*
+X823140Y53667D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X294131Y459231D02*
-X294131Y459231D01*
-X294131Y466137D01*
-X294241Y466120D01*
-X295610Y465675D01*
-X296893Y465021D01*
-X298057Y464175D01*
-X299075Y463157D01*
-X299921Y461993D01*
-X300575Y460710D01*
-X301020Y459341D01*
-X301037Y459231D01*
-X294131Y459231D01*
+X293369Y433069D02*
+X293369Y433069D01*
+X293369Y440871D01*
+X294767Y440593D01*
+X296432Y439904D01*
+X297929Y438903D01*
+X299203Y437629D01*
+X300204Y436132D01*
+X300893Y434467D01*
+X301171Y433069D01*
+X293369Y433069D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X586231Y14731D02*
-X586231Y14731D01*
-X586231Y21637D01*
-X586341Y21620D01*
-X587710Y21175D01*
-X588993Y20521D01*
-X590157Y19675D01*
-X591175Y18657D01*
-X592021Y17493D01*
-X592675Y16210D01*
-X593120Y14841D01*
-X593137Y14731D01*
-X586231Y14731D01*
+X483869Y242569D02*
+X483869Y242569D01*
+X483869Y250371D01*
+X485267Y250093D01*
+X486932Y249404D01*
+X488429Y248403D01*
+X489703Y247129D01*
+X490704Y245632D01*
+X491393Y243967D01*
+X491671Y242569D01*
+X483869Y242569D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X129031Y624331D02*
-X129031Y624331D01*
-X129031Y631237D01*
-X129141Y631220D01*
-X130510Y630775D01*
-X131793Y630121D01*
-X132957Y629275D01*
-X133975Y628257D01*
-X134821Y627093D01*
-X135475Y625810D01*
-X135920Y624441D01*
-X135937Y624331D01*
-X129031Y624331D01*
+X621029Y458469D02*
+X621029Y458469D01*
+X621029Y466271D01*
+X622427Y465993D01*
+X624092Y465304D01*
+X625589Y464303D01*
+X626863Y463029D01*
+X627864Y461532D01*
+X628553Y459867D01*
+X628831Y458469D01*
+X621029Y458469D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X484631Y243331D02*
-X484631Y243331D01*
-X484631Y250237D01*
-X484741Y250220D01*
-X486110Y249775D01*
-X487393Y249121D01*
-X488557Y248275D01*
-X489575Y247257D01*
-X490421Y246093D01*
-X491075Y244810D01*
-X491520Y243441D01*
-X491537Y243331D01*
-X484631Y243331D01*
+X293369Y458469D02*
+X293369Y458469D01*
+X293369Y466271D01*
+X294767Y465993D01*
+X296432Y465304D01*
+X297929Y464303D01*
+X299203Y463029D01*
+X300204Y461532D01*
+X300893Y459867D01*
+X301171Y458469D01*
+X293369Y458469D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X484631Y344931D02*
-X484631Y344931D01*
-X484631Y351837D01*
-X484741Y351820D01*
-X486110Y351375D01*
-X487393Y350721D01*
-X488557Y349875D01*
-X489575Y348857D01*
-X490421Y347693D01*
-X491075Y346410D01*
-X491520Y345041D01*
-X491537Y344931D01*
-X484631Y344931D01*
+X293369Y407669D02*
+X293369Y407669D01*
+X293369Y415471D01*
+X294767Y415193D01*
+X296432Y414504D01*
+X297929Y413503D01*
+X299203Y412229D01*
+X300204Y410732D01*
+X300893Y409067D01*
+X301171Y407669D01*
+X293369Y407669D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X329691Y560831D02*
-X329691Y560831D01*
-X329691Y567737D01*
-X329801Y567720D01*
-X331170Y567275D01*
-X332453Y566621D01*
-X333617Y565775D01*
-X334635Y564757D01*
-X335481Y563593D01*
-X336135Y562310D01*
-X336580Y560941D01*
-X336597Y560831D01*
-X329691Y560831D01*
+X585469Y13969D02*
+X585469Y13969D01*
+X585469Y21771D01*
+X586867Y21493D01*
+X588532Y20804D01*
+X590029Y19803D01*
+X591303Y18529D01*
+X592304Y17032D01*
+X592993Y15367D01*
+X593271Y13969D01*
+X585469Y13969D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X294131Y433831D02*
-X294131Y433831D01*
-X294131Y440737D01*
-X294241Y440720D01*
-X295610Y440275D01*
-X296893Y439621D01*
-X298057Y438775D01*
-X299075Y437757D01*
-X299921Y436593D01*
-X300575Y435310D01*
-X301020Y433941D01*
-X301037Y433831D01*
-X294131Y433831D01*
+X328929Y560069D02*
+X328929Y560069D01*
+X328929Y567871D01*
+X330327Y567593D01*
+X331992Y566904D01*
+X333489Y565903D01*
+X334763Y564629D01*
+X335764Y563132D01*
+X336453Y561467D01*
+X336731Y560069D01*
+X328929Y560069D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X294131Y455169D02*
-X294131Y455169D01*
-X301037Y455169D01*
-X301020Y455059D01*
-X300575Y453690D01*
-X299921Y452407D01*
-X299075Y451243D01*
-X298057Y450225D01*
-X296893Y449379D01*
-X295610Y448725D01*
-X294241Y448280D01*
-X294131Y448263D01*
-X294131Y455169D01*
+X102869Y623569D02*
+X102869Y623569D01*
+X102869Y631371D01*
+X104267Y631093D01*
+X105932Y630404D01*
+X107429Y629403D01*
+X108703Y628129D01*
+X109704Y626632D01*
+X110393Y624967D01*
+X110671Y623569D01*
+X102869Y623569D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X294131Y429769D02*
-X294131Y429769D01*
-X301037Y429769D01*
-X301020Y429659D01*
-X300575Y428290D01*
-X299921Y427007D01*
-X299075Y425843D01*
-X298057Y424825D01*
-X296893Y423979D01*
-X295610Y423325D01*
-X294241Y422880D01*
-X294131Y422863D01*
-X294131Y429769D01*
+X483869Y344169D02*
+X483869Y344169D01*
+X483869Y351971D01*
+X485267Y351693D01*
+X486932Y351004D01*
+X488429Y350003D01*
+X489703Y348729D01*
+X490704Y347232D01*
+X491393Y345567D01*
+X491671Y344169D01*
+X483869Y344169D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X610823Y459231D02*
-X610823Y459231D01*
-X610840Y459341D01*
-X611285Y460710D01*
-X611939Y461993D01*
-X612785Y463157D01*
-X613803Y464175D01*
-X614967Y465021D01*
-X616250Y465675D01*
-X617619Y466120D01*
-X617729Y466137D01*
-X617729Y459231D01*
-X610823Y459231D01*
+X283029Y458469D02*
+X283029Y458469D01*
+X283307Y459867D01*
+X283996Y461532D01*
+X284997Y463029D01*
+X286271Y464303D01*
+X287768Y465304D01*
+X289433Y465993D01*
+X290831Y466271D01*
+X290831Y458469D01*
+X283029Y458469D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X283163Y459231D02*
-X283163Y459231D01*
-X283180Y459341D01*
-X283625Y460710D01*
-X284279Y461993D01*
-X285125Y463157D01*
-X286143Y464175D01*
-X287307Y465021D01*
-X288590Y465675D01*
-X289959Y466120D01*
-X290069Y466137D01*
-X290069Y459231D01*
-X283163Y459231D01*
+X610689Y458469D02*
+X610689Y458469D01*
+X610967Y459867D01*
+X611656Y461532D01*
+X612657Y463029D01*
+X613931Y464303D01*
+X615428Y465304D01*
+X617093Y465993D01*
+X618491Y466271D01*
+X618491Y458469D01*
+X610689Y458469D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X283163Y433831D02*
-X283163Y433831D01*
-X283180Y433941D01*
-X283625Y435310D01*
-X284279Y436593D01*
-X285125Y437757D01*
-X286143Y438775D01*
-X287307Y439621D01*
-X288590Y440275D01*
-X289959Y440720D01*
-X290069Y440737D01*
-X290069Y433831D01*
-X283163Y433831D01*
+X283029Y433069D02*
+X283029Y433069D01*
+X283307Y434467D01*
+X283996Y436132D01*
+X284997Y437629D01*
+X286271Y438903D01*
+X287768Y439904D01*
+X289433Y440593D01*
+X290831Y440871D01*
+X290831Y433069D01*
+X283029Y433069D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X484631Y239269D02*
-X484631Y239269D01*
-X491537Y239269D01*
-X491520Y239159D01*
-X491075Y237790D01*
-X490421Y236507D01*
-X489575Y235343D01*
-X488557Y234325D01*
-X487393Y233479D01*
-X486110Y232825D01*
-X484741Y232380D01*
-X484631Y232363D01*
-X484631Y239269D01*
+X328929Y557531D02*
+X328929Y557531D01*
+X336731Y557531D01*
+X336453Y556133D01*
+X335764Y554468D01*
+X334763Y552971D01*
+X333489Y551697D01*
+X331992Y550696D01*
+X330327Y550007D01*
+X328929Y549729D01*
+X328929Y557531D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X129031Y620269D02*
-X129031Y620269D01*
-X135937Y620269D01*
-X135920Y620159D01*
-X135475Y618790D01*
-X134821Y617507D01*
-X133975Y616343D01*
-X132957Y615325D01*
-X131793Y614479D01*
-X130510Y613825D01*
-X129141Y613380D01*
-X129031Y613363D01*
-X129031Y620269D01*
+X318589Y560069D02*
+X318589Y560069D01*
+X318867Y561467D01*
+X319556Y563132D01*
+X320557Y564629D01*
+X321831Y565903D01*
+X323328Y566904D01*
+X324993Y567593D01*
+X326391Y567871D01*
+X326391Y560069D01*
+X318589Y560069D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X118063Y624331D02*
-X118063Y624331D01*
-X118080Y624441D01*
-X118525Y625810D01*
-X119179Y627093D01*
-X120025Y628257D01*
-X121043Y629275D01*
-X122207Y630121D01*
-X123490Y630775D01*
-X124859Y631220D01*
-X124969Y631237D01*
-X124969Y624331D01*
-X118063Y624331D01*
+X102869Y621031D02*
+X102869Y621031D01*
+X110671Y621031D01*
+X110393Y619633D01*
+X109704Y617968D01*
+X108703Y616471D01*
+X107429Y615197D01*
+X105932Y614196D01*
+X104267Y613507D01*
+X102869Y613229D01*
+X102869Y621031D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X318723Y560831D02*
-X318723Y560831D01*
-X318740Y560941D01*
-X319185Y562310D01*
-X319839Y563593D01*
-X320685Y564757D01*
-X321703Y565775D01*
-X322867Y566621D01*
-X324150Y567275D01*
-X325519Y567720D01*
-X325629Y567737D01*
-X325629Y560831D01*
-X318723Y560831D01*
+X92529Y623569D02*
+X92529Y623569D01*
+X92807Y624967D01*
+X93496Y626632D01*
+X94497Y628129D01*
+X95771Y629403D01*
+X97268Y630404D01*
+X98933Y631093D01*
+X100331Y631371D01*
+X100331Y623569D01*
+X92529Y623569D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X329691Y556769D02*
-X329691Y556769D01*
-X336597Y556769D01*
-X336580Y556659D01*
-X336135Y555290D01*
-X335481Y554007D01*
-X334635Y552843D01*
-X333617Y551825D01*
-X332453Y550979D01*
-X331170Y550325D01*
-X329801Y549880D01*
-X329691Y549863D01*
-X329691Y556769D01*
+X575129Y13969D02*
+X575129Y13969D01*
+X575407Y15367D01*
+X576096Y17032D01*
+X577097Y18529D01*
+X578371Y19803D01*
+X579868Y20804D01*
+X581533Y21493D01*
+X582931Y21771D01*
+X582931Y13969D01*
+X575129Y13969D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X294131Y404369D02*
-X294131Y404369D01*
-X301037Y404369D01*
-X301020Y404259D01*
-X300575Y402890D01*
-X299921Y401607D01*
-X299075Y400443D01*
-X298057Y399425D01*
-X296893Y398579D01*
-X295610Y397925D01*
-X294241Y397480D01*
-X294131Y397463D01*
-X294131Y404369D01*
+X283029Y407669D02*
+X283029Y407669D01*
+X283307Y409067D01*
+X283996Y410732D01*
+X284997Y412229D01*
+X286271Y413503D01*
+X287768Y414504D01*
+X289433Y415193D01*
+X290831Y415471D01*
+X290831Y407669D01*
+X283029Y407669D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X575263Y14731D02*
-X575263Y14731D01*
-X575280Y14841D01*
-X575725Y16210D01*
-X576379Y17493D01*
-X577225Y18657D01*
-X578243Y19675D01*
-X579407Y20521D01*
-X580690Y21175D01*
-X582059Y21620D01*
-X582169Y21637D01*
-X582169Y14731D01*
-X575263Y14731D01*
+X483869Y240031D02*
+X483869Y240031D01*
+X491671Y240031D01*
+X491393Y238633D01*
+X490704Y236968D01*
+X489703Y235471D01*
+X488429Y234197D01*
+X486932Y233196D01*
+X485267Y232507D01*
+X483869Y232229D01*
+X483869Y240031D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X473663Y344931D02*
-X473663Y344931D01*
-X473680Y345041D01*
-X474125Y346410D01*
-X474779Y347693D01*
-X475625Y348857D01*
-X476643Y349875D01*
-X477807Y350721D01*
-X479090Y351375D01*
-X480459Y351820D01*
-X480569Y351837D01*
-X480569Y344931D01*
-X473663Y344931D01*
+X473529Y242569D02*
+X473529Y242569D01*
+X473807Y243967D01*
+X474496Y245632D01*
+X475497Y247129D01*
+X476771Y248403D01*
+X478268Y249404D01*
+X479933Y250093D01*
+X481331Y250371D01*
+X481331Y242569D01*
+X473529Y242569D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X283163Y408431D02*
-X283163Y408431D01*
-X283180Y408541D01*
-X283625Y409910D01*
-X284279Y411193D01*
-X285125Y412357D01*
-X286143Y413375D01*
-X287307Y414221D01*
-X288590Y414875D01*
-X289959Y415320D01*
-X290069Y415337D01*
-X290069Y408431D01*
-X283163Y408431D01*
+X473529Y344169D02*
+X473529Y344169D01*
+X473807Y345567D01*
+X474496Y347232D01*
+X475497Y348729D01*
+X476771Y350003D01*
+X478268Y351004D01*
+X479933Y351693D01*
+X481331Y351971D01*
+X481331Y344169D01*
+X473529Y344169D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X473663Y243331D02*
-X473663Y243331D01*
-X473680Y243441D01*
-X474125Y244810D01*
-X474779Y246093D01*
-X475625Y247257D01*
-X476643Y248275D01*
-X477807Y249121D01*
-X479090Y249775D01*
-X480459Y250220D01*
-X480569Y250237D01*
-X480569Y243331D01*
-X473663Y243331D01*
+X293369Y455931D02*
+X293369Y455931D01*
+X301171Y455931D01*
+X300893Y454533D01*
+X300204Y452868D01*
+X299203Y451371D01*
+X297929Y450097D01*
+X296432Y449096D01*
+X294767Y448407D01*
+X293369Y448129D01*
+X293369Y455931D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X289959Y448280D02*
-X289959Y448280D01*
-X288590Y448725D01*
-X287307Y449379D01*
-X286143Y450225D01*
-X285125Y451243D01*
-X284279Y452407D01*
-X283625Y453690D01*
-X283180Y455059D01*
-X283163Y455169D01*
-X290069Y455169D01*
-X290069Y448263D01*
-X289959Y448280D01*
+X293369Y405131D02*
+X293369Y405131D01*
+X301171Y405131D01*
+X300893Y403733D01*
+X300204Y402068D01*
+X299203Y400571D01*
+X297929Y399297D01*
+X296432Y398296D01*
+X294767Y397607D01*
+X293369Y397329D01*
+X293369Y405131D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X480459Y232380D02*
-X480459Y232380D01*
-X479090Y232825D01*
-X477807Y233479D01*
-X476643Y234325D01*
-X475625Y235343D01*
-X474779Y236507D01*
-X474125Y237790D01*
-X473680Y239159D01*
-X473663Y239269D01*
-X480569Y239269D01*
-X480569Y232363D01*
-X480459Y232380D01*
+X293369Y430531D02*
+X293369Y430531D01*
+X301171Y430531D01*
+X300893Y429133D01*
+X300204Y427468D01*
+X299203Y425971D01*
+X297929Y424697D01*
+X296432Y423696D01*
+X294767Y423007D01*
+X293369Y422729D01*
+X293369Y430531D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X124859Y613380D02*
-X124859Y613380D01*
-X123490Y613825D01*
-X122207Y614479D01*
-X121043Y615325D01*
-X120025Y616343D01*
-X119179Y617507D01*
-X118525Y618790D01*
-X118080Y620159D01*
-X118063Y620269D01*
-X124969Y620269D01*
-X124969Y613363D01*
-X124859Y613380D01*
+X585469Y11431D02*
+X585469Y11431D01*
+X593271Y11431D01*
+X592993Y10033D01*
+X592304Y8368D01*
+X591303Y6871D01*
+X590029Y5597D01*
+X588532Y4596D01*
+X586867Y3907D01*
+X585469Y3629D01*
+X585469Y11431D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X289959Y397480D02*
-X289959Y397480D01*
-X288590Y397925D01*
-X287307Y398579D01*
-X286143Y399425D01*
-X285125Y400443D01*
-X284279Y401607D01*
-X283625Y402890D01*
-X283180Y404259D01*
-X283163Y404369D01*
-X290069Y404369D01*
-X290069Y397463D01*
-X289959Y397480D01*
+X324993Y550007D02*
+X324993Y550007D01*
+X323328Y550696D01*
+X321831Y551697D01*
+X320557Y552971D01*
+X319556Y554468D01*
+X318867Y556133D01*
+X318589Y557531D01*
+X326391Y557531D01*
+X326391Y549729D01*
+X324993Y550007D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X289959Y422880D02*
-X289959Y422880D01*
-X288590Y423325D01*
-X287307Y423979D01*
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 %LPD*%
 %LPC*%
 G36*
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 %LPD*%
 %LPC*%
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 G37*
 %LPD*%
 %LPC*%
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 %LPC*%
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 %LPD*%
 %LPC*%
 G36*
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 %LPC*%
 G36*
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 G37*
 %LPD*%
 D10*
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 D11*
 X165100Y457200D03*
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@@ -28573,16 +22131,16 @@ X317500Y661670D03*
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 X863600Y241300D03*
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 D19*
 X661670Y637540D01*
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 D17*
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 D19*
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@@ -30379,103 +23981,93 @@ X843280Y612140D03*
 D19*
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 X236220Y558800D01*
 M02*
diff --git a/Gerbers/copper_top.gbr b/Gerbers/copper_top.gbr
index 85310cd..cf3286c 100644
--- a/Gerbers/copper_top.gbr
+++ b/Gerbers/copper_top.gbr
@@ -22,94 +22,77 @@ G01*
 %ADD21R,1.500000X1.300000*%
 %ADD22C,1.508000*%
 %ADD23R,0.660400X2.032000*%
-%ADD24C,0.254000*%
-%ADD25C,0.304800*%
-%ADD26C,0.812800*%
-%ADD27C,0.604800*%
-%ADD28C,0.127000*%
+%ADD24R,1.930400X5.334000*%
+%ADD25C,1.000000*%
+%ADD26C,0.254000*%
+%ADD27C,0.304800*%
+%ADD28C,0.812800*%
+%ADD29C,0.604800*%
+%ADD30C,0.127000*%
 
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+X263255Y545936D01*
+X263207Y545981D01*
+X263163Y545999D01*
+X263125Y546026D01*
+X263061Y546043D01*
+X263000Y546068D01*
+X262953Y546070D01*
+X262907Y546082D01*
+X262842Y546075D01*
+X262776Y546078D01*
+X262731Y546064D01*
+X262684Y546059D01*
+X262625Y546030D01*
+X262562Y546010D01*
+X262518Y545977D01*
+X262483Y545959D01*
+X262456Y545931D01*
+X262412Y545898D01*
+X260859Y544345D01*
+X257301Y544345D01*
+X254785Y546861D01*
+X254785Y550419D01*
+X257301Y552935D01*
+X260859Y552935D01*
+X262427Y551367D01*
+X262462Y551342D01*
+X262491Y551311D01*
+X262554Y551279D01*
+X262611Y551238D01*
+X262652Y551228D01*
+X262690Y551208D01*
+X262780Y551195D01*
+X262829Y551182D01*
+X262849Y551185D01*
+X262876Y551181D01*
+X265212Y551181D01*
+X276992Y539401D01*
+X277015Y539363D01*
+X277031Y539350D01*
+X277047Y539329D01*
+X277623Y538752D01*
+X277623Y517380D01*
+X276878Y516635D01*
+X269222Y516635D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X315731Y652779D02*
-X315731Y652779D01*
-X312464Y654133D01*
-X309963Y656634D01*
-X308609Y659901D01*
-X308609Y663439D01*
-X309963Y666706D01*
-X312464Y669207D01*
-X315731Y670561D01*
-X319269Y670561D01*
-X322536Y669207D01*
-X325037Y666706D01*
-X326391Y663439D01*
-X326391Y659901D01*
-X325037Y656634D01*
-X322536Y654133D01*
-X319269Y652779D01*
-X315731Y652779D01*
+X257301Y562125D02*
+X257301Y562125D01*
+X254785Y564641D01*
+X254785Y568199D01*
+X257321Y570735D01*
+X257349Y570746D01*
+X257396Y570754D01*
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+X257513Y570813D01*
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+X257589Y570869D01*
+X257631Y570920D01*
+X257679Y570964D01*
+X257701Y571006D01*
+X257730Y571043D01*
+X257751Y571105D01*
+X257782Y571164D01*
+X257790Y571218D01*
+X257802Y571255D01*
+X257801Y571295D01*
+X257809Y571349D01*
+X257809Y577469D01*
+X257798Y577534D01*
+X257796Y577600D01*
+X257778Y577643D01*
+X257770Y577690D01*
+X257736Y577747D01*
+X257711Y577807D01*
+X257680Y577842D01*
+X257655Y577883D01*
+X257604Y577925D01*
+X257560Y577973D01*
+X257518Y577995D01*
+X257481Y578024D01*
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+X257269Y578096D01*
+X257229Y578095D01*
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+X256522Y578103D01*
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+X263351Y578072D01*
+X263304Y578064D01*
+X263247Y578030D01*
+X263187Y578005D01*
+X263152Y577974D01*
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+X263069Y577898D01*
+X263021Y577854D01*
+X262999Y577812D01*
+X262970Y577775D01*
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+X262918Y577654D01*
+X262910Y577600D01*
+X262898Y577563D01*
+X262899Y577523D01*
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+X262891Y568946D01*
+X262898Y568904D01*
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+X263375Y568199D01*
+X263375Y564641D01*
+X260859Y562125D01*
+X257301Y562125D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X366531Y652779D02*
-X366531Y652779D01*
-X363264Y654133D01*
-X360763Y656634D01*
-X359409Y659901D01*
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-X370069Y652779D01*
-X366531Y652779D01*
-G37*
-%LPD*%
-%LPC*%
-G36*
-X391931Y652779D02*
-X391931Y652779D01*
+X391932Y652779D02*
+X391932Y652779D01*
 X388664Y654133D01*
 X386163Y656634D01*
-X384809Y659901D01*
-X384809Y663439D01*
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 X386163Y666706D01*
 X388664Y669207D01*
-X391931Y670561D01*
-X395469Y670561D01*
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 X398736Y669207D01*
 X401237Y666706D01*
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 X401237Y656634D01*
 X398736Y654133D01*
-X395469Y652779D01*
-X391931Y652779D01*
+X395468Y652779D01*
+X391932Y652779D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X315731Y627379D02*
-X315731Y627379D01*
-X312464Y628733D01*
-X309963Y631234D01*
-X308609Y634501D01*
-X308609Y638039D01*
-X309963Y641306D01*
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-X319269Y645161D01*
-X322536Y643807D01*
-X325037Y641306D01*
-X326391Y638039D01*
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-X322536Y628733D01*
-X319269Y627379D01*
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+X350437Y656634D01*
+X347936Y654133D01*
+X344668Y652779D01*
+X341132Y652779D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X366531Y627379D02*
-X366531Y627379D01*
+X315732Y652779D02*
+X315732Y652779D01*
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+G37*
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 X363264Y628733D01*
 X360763Y631234D01*
-X359409Y634501D01*
-X359409Y638039D01*
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 X360763Y641306D01*
 X363264Y643807D01*
-X366531Y645161D01*
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 X373336Y643807D01*
 X375837Y641306D01*
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 X373336Y628733D01*
-X370069Y627379D01*
-X366531Y627379D01*
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 G37*
 %LPD*%
 %LPC*%
 G36*
-X341131Y627379D02*
-X341131Y627379D01*
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 X337864Y628733D01*
 X335363Y631234D01*
-X334009Y634501D01*
-X334009Y638039D01*
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 X335363Y641306D01*
 X337864Y643807D01*
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 X347936Y643807D01*
 X350437Y641306D01*
-X351791Y638039D01*
-X351791Y634501D01*
+X351791Y638038D01*
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 X350437Y631234D01*
 X347936Y628733D01*
-X344669Y627379D01*
-X341131Y627379D01*
+X344668Y627379D01*
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 G37*
 %LPD*%
 %LPC*%
 G36*
-X468147Y29289D02*
-X468147Y29289D01*
-X464909Y30631D01*
-X462431Y33109D01*
-X461089Y36347D01*
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 G37*
 %LPD*%
 %LPC*%
 G36*
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-X112547Y29289D01*
-X109309Y30631D01*
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-G37*
-%LPD*%
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-G36*
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-G37*
-%LPD*%
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+X451969Y58509D01*
+X449491Y56031D01*
+X446253Y54689D01*
+X442747Y54689D01*
 G37*
 %LPD*%
 %LPC*%
@@ -35771,24 +24789,46 @@ G37*
 %LPD*%
 %LPC*%
 G36*
-X87147Y80089D02*
-X87147Y80089D01*
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+%LPD*%
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 G37*
 %LPD*%
 %LPC*%
@@ -35815,112 +24855,266 @@ G37*
 %LPD*%
 %LPC*%
 G36*
-X137947Y54689D02*
-X137947Y54689D01*
-X134709Y56031D01*
-X132231Y58509D01*
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 G37*
 %LPD*%
 %LPC*%
 G36*
-X188747Y54689D02*
-X188747Y54689D01*
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-X183031Y58509D01*
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+X629769Y33109D01*
+X627291Y30631D01*
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+X620547Y29289D01*
 G37*
 %LPD*%
 %LPC*%
 G36*
-X112547Y54689D02*
-X112547Y54689D01*
-X109309Y56031D01*
-X106831Y58509D01*
-X105489Y61747D01*
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@@ -37312,6 +28269,81 @@ G37*
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diff --git a/Gerbers/drill_1_16.xln b/Gerbers/drill_1_16.xln
index 90969b3..8e54957 100644
--- a/Gerbers/drill_1_16.xln
+++ b/Gerbers/drill_1_16.xln
@@ -1,6 +1,6 @@
 M48
 ;GenerationSoftware,Autodesk,EAGLE,9.6.2*%
-;CreationDate,2021-07-25T20:18:48Z*%
+;CreationDate,2021-07-27T02:59:54Z*%
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@@ -131,18 +120,77 @@ X62230Y6350
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 T3
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 X16510Y43180
 X19050Y43180
 X16510Y40640
 X19050Y40640
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 T4
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@@ -174,7 +222,6 @@ X43180Y24130
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 X43180Y1270
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@@ -200,6 +247,7 @@ X30480Y24130
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 X20320Y24130
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@@ -232,58 +280,10 @@ X58420Y34290
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 T5
-X20320Y57150
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 T6
 X56388Y38862
 X56388Y38100
@@ -348,9 +348,8 @@ X55118Y38100
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@@ -372,23 +371,22 @@ X60198Y26416
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@@ -401,48 +399,66 @@ X65405Y62103
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@@ -463,46 +479,46 @@ X57023Y33274
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@@ -524,55 +540,55 @@ X70612Y60198
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@@ -592,13 +608,13 @@ X35560Y39370
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@@ -749,19 +765,19 @@ X81026Y15240
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@@ -779,26 +795,26 @@ X80772Y45720
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diff --git a/Gerbers/silkscreen_top.gbr b/Gerbers/silkscreen_top.gbr
index 8a88c21..8dcbc8f 100644
--- a/Gerbers/silkscreen_top.gbr
+++ b/Gerbers/silkscreen_top.gbr
@@ -587,14 +587,14 @@ X407289Y682061D01*
 D12*
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 X371406Y490193D02*
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 D13*
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 D15*
 X10668Y482092D02*
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@@ -12864,823 +12864,6 @@ X411993Y546253D01*
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 M02*
diff --git a/Gerbers/soldermask_bottom.gbr b/Gerbers/soldermask_bottom.gbr
index a460f97..b36d88d 100644
--- a/Gerbers/soldermask_bottom.gbr
+++ b/Gerbers/soldermask_bottom.gbr
@@ -17,10 +17,10 @@ G01*
 
 
 D10*
-X152400Y622300D03*
-X152400Y546100D03*
 X127000Y622300D03*
 X127000Y546100D03*
+X101600Y622300D03*
+X101600Y546100D03*
 D11*
 X165100Y457200D03*
 X190500Y457200D03*
@@ -50,16 +50,16 @@ X317500Y661670D03*
 X317500Y636270D03*
 X292100Y661670D03*
 X292100Y636270D03*
-X88900Y520700D03*
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 X63500Y622300D03*
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 D10*
 X863600Y241300D03*
 X838200Y241300D03*
@@ -126,8 +126,8 @@ X152400Y12700D03*
 X127000Y12700D03*
 X101600Y12700D03*
 D13*
-X203200Y571500D03*
-X203200Y546100D03*
+X198120Y571500D03*
+X198120Y546100D03*
 D14*
 X271780Y543560D03*
 X271780Y558800D03*
diff --git a/Gerbers/soldermask_top.gbr b/Gerbers/soldermask_top.gbr
index 834c912..f1bb68b 100644
--- a/Gerbers/soldermask_top.gbr
+++ b/Gerbers/soldermask_top.gbr
@@ -21,6 +21,8 @@ G01*
 %ADD20R,1.601600X1.401600*%
 %ADD21C,1.609600*%
 %ADD22R,0.762000X2.133600*%
+%ADD23R,2.032000X5.435600*%
+%ADD24C,1.101600*%
 
 
 D10*
@@ -728,10 +730,10 @@ X341440Y529401D01*
 X352764Y518077D01*
 G37*
 D12*
-X152400Y622300D03*
-X152400Y546100D03*
 X127000Y622300D03*
 X127000Y546100D03*
+X101600Y622300D03*
+X101600Y546100D03*
 D13*
 X165100Y457200D03*
 X190500Y457200D03*
@@ -755,8 +757,8 @@ D15*
 X244000Y502920D03*
 X264000Y502920D03*
 D14*
-X327660Y518000D03*
 X327660Y498000D03*
+X327660Y518000D03*
 X566420Y518000D03*
 X566420Y498000D03*
 D12*
@@ -775,16 +777,16 @@ X317500Y661670D03*
 X317500Y636270D03*
 X292100Y661670D03*
 X292100Y636270D03*
-X88900Y520700D03*
 X63500Y520700D03*
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+X38100Y520700D03*
 X63500Y546100D03*
-X88900Y571500D03*
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 X63500Y571500D03*
-X88900Y596900D03*
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 X63500Y596900D03*
-X88900Y622300D03*
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 X63500Y622300D03*
+X38100Y622300D03*
 D12*
 X863600Y241300D03*
 X838200Y241300D03*
@@ -851,13 +853,13 @@ X152400Y12700D03*
 X127000Y12700D03*
 X101600Y12700D03*
 D17*
-X203200Y571500D03*
-X203200Y546100D03*
+X198120Y571500D03*
+X198120Y546100D03*
 D14*
-X203200Y515460D03*
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-X203200Y622140D03*
+X160020Y543400D03*
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+X160020Y594200D03*
 D18*
 X683050Y573000D03*
 X677550Y573000D03*
@@ -923,10 +925,10 @@ X263500Y431800D03*
 X244500Y406400D03*
 X263500Y406400D03*
 D20*
-X152400Y574700D03*
-X152400Y593700D03*
 X127000Y574700D03*
 X127000Y593700D03*
+X101600Y574700D03*
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 D12*
 X863600Y342900D03*
 X838200Y342900D03*
@@ -1098,4 +1100,11 @@ X247650Y589534D03*
 X260350Y589534D03*
 X273050Y528066D03*
 X273050Y589534D03*
+D23*
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+D24*
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+X927100Y12700D03*
+X38100Y12700D03*
 M02*
diff --git a/Gerbers/solderpaste_top.gbr b/Gerbers/solderpaste_top.gbr
index 3529a4d..9936f05 100644
--- a/Gerbers/solderpaste_top.gbr
+++ b/Gerbers/solderpaste_top.gbr
@@ -16,6 +16,7 @@ G01*
 %ADD15R,1.300000X1.500000*%
 %ADD16R,1.500000X1.300000*%
 %ADD17R,0.660400X2.032000*%
+%ADD18R,1.930400X5.334000*%
 
 
 D10*
@@ -731,14 +732,14 @@ D13*
 X244000Y502920D03*
 X264000Y502920D03*
 D12*
-X327660Y518000D03*
 X327660Y498000D03*
+X327660Y518000D03*
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 X566420Y498000D03*
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-X203200Y622140D03*
+X160020Y543400D03*
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 D14*
 X683050Y573000D03*
 X677550Y573000D03*
@@ -804,10 +805,10 @@ X263500Y431800D03*
 X244500Y406400D03*
 X263500Y406400D03*
 D16*
-X152400Y574700D03*
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 X127000Y574700D03*
 X127000Y593700D03*
+X101600Y574700D03*
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 D17*
 X234950Y528066D03*
 X234950Y589534D03*
@@ -817,4 +818,7 @@ X247650Y589534D03*
 X260350Y589534D03*
 X273050Y528066D03*
 X273050Y589534D03*
+D18*
+X198120Y607060D03*
+X198120Y510540D03*
 M02*
diff --git a/README.md b/README.md
index f246032..2939cd0 100644
--- a/README.md
+++ b/README.md
@@ -1,24 +1,28 @@
 # SE-VGA
-Simple CPLD project to mirror the Mac SE video over VGA. No scaling is performed -- the Mac 512x342 video is displayed letterboxed (black borders) in a 640x480 frame. Plugs into SE PDS slot and snoops writes to the frame buffer memory locations. Writes are cached and copied to VRAM.
+Simple CPLD project to mirror the Mac SE video over VGA. The image is pixel-doubled to 1024x684 and displayed letterboxed (black borders) in a 1024x768 video frame. Device snoops writes to the frame buffer memory locations and caches the data to its own VRAM for display. Plugs into the PDS slot in a Mac SE, or plugs in place of the CPU on Mac SE, Plus, or 512k models (128k Mac could be made to work with some adjustment to the CPLD configuration, but is not a configuration supported by the memory selection jumpers).
 
-Circuit uses a single AFT1508AS-100AU CPLD, a pair of 256kbit (32kx8) 15ns SRAM, and a 25.175MHz can oscillator, along with some passives.
+Circuit uses a single AFT1508AS-7AX100 CPLD, a pair of 256kbit (32kx8) 15ns or faster SRAM, a 13MHz crystal with 5x clock multiplier for 65MHz pixel clock, along with some passives.
 
 ## Bill of Materials
 
 | Qty | Manufacturer    | Part No.           | Name               | Description                                   |
 |:---:|:----------------|:-------------------|:-------------------|:----------------------------------------------|
-|  2  | Renesas         | 71256SA12TPG       | VRAM-ALT, VRAM-MAIN| 32kx8 15ns SRAM                               | 
-|  1  | Microchip       | ATF1508AS-7AX100   | LOGIC              | ATF1508AS or EPM7128 CPLD                     |
-|  1  | CTS             | MXO45HS-3C-25M1750 | CLK                | 25.175MHz oscillator                          |
+|  2  | ISSI            | IS61C256AL-12TLI   | VRAM-ALT, VRAM-MAIN| 32kx8 12ns SRAM, TSOP-28                      | 
+|  1  | Microchip       | ATF1508AS-7AX100   | LOGIC              | ATF1508AS or EPM7128 CPLD, TQFP-100           |
+|  1  | Renesas / IDT   | 511MLF             | CLK                | Programmable Clock Multiplier, SO-8           |
+|  1  | ECS             | ECS-130-20-46X     | XTAL               | 13MHz Crystal, HC-46X or HC-49UP              |
 |  1  | TE Connectivity | 650473-5           | PDS                | DIN 41612 Right-angle 3x32 pin male connector |
-|  5  |                 |                    | C1, C2, C3, C4, C5 | 0.1uF Decoupling Capacitor                    |
+|  5  |                 |                    | C1, C2, C3, C4, C5 | 0.1uF Decoupling Capacitor, 0805              |
 |  2  |                 |                    | C6, C7             | 10uF Electrolytic Capacitor                   |
-|  2  |                 |                    | R7, R8, R9         | 4k7 pullup resistor (value not critical)      |
-|  3  |                 |                    | R1, R2, R3         | 470 ohm resistor                              |
-|  3  |                 |                    | R4, R5, R6         | 75 ohm resistor                               |
+|  2  |                 |                    | C8, C9             | 20pF Capacitor, 0805                          |
+|  2  |                 |                    | R3, R4, R5         | 10k pullup resistor, 0805 or axial            |
+|  3  |                 |                    | R2                 | 460 ohm resistor, 0805 or axial               |
+|  3  |                 |                    | R1                 | 75 ohm resistor, 0805 or axial                |
 |  1  |                 |                    | PGM                | 2x5 pin header for CPLD JTAG programming      |
-|  1  |                 |                    | VGA                | 6x1 pin header for VGA adapter                |
+|  1  |                 |                    | VGA                | 2x5 pin header for VGA adapter                |
 |  1  |                 |                    | RAMSIZE            | 3x2 jumper                                    |
+|  1  |                 |                    | BRD                | 64-pin DIP header, male                       |
+|  1  |                 |                    | CPU                | 64-pin DIP socket, female                     |
 
 ## Frame Buffer Addressing
 
@@ -124,11 +128,11 @@ Logic uses nearly all available resources in the CPLD (104 of 128 macrocells).
 |TMS|Input|PIN_15
 
 ## Known Issues
-First run schematic and gerbers used three pairs of resistor dividers for R, G, B output channels. A better approach would be to use a single divider and tie all three output channels together. Also 470 ohm is a bit too high, so the image is quite dark.
+~~First run schematic and gerbers used three pairs of resistor dividers for R, G, B output channels. A better approach would be to use a single divider and tie all three output channels together. Also 470 ohm is a bit too high, so the image is quite dark.~~ Removed extraneous resistor dividers. Changed 470ohm resistor to 460.
 
-The resistor footprints are too small for 1/4W parts. Might work with 1/8W parts.
+~~The resistor footprints are too small for 1/4W parts. Might work with 1/8W parts.~~ Added footprints for 0805 resistors. 
 
 Timing for the SE window is a bit off. It appears to be starting the window a couple pixels early on the left, and it might be cutting off the last pixel or two on the right.
 
 ## Wish List
-I would like to bump up the pixel clock to 65MHz and run the output video at 1024x768@60. This would allow the SE frame to be pixel doubled to 1024x684, which would only leave black bars on the top and bottom, instead of on all four sides. This could also be a useful starting point for a future project to output video for an early iPad display for units missing a CRT. 
\ No newline at end of file
+~~I would like to bump up the pixel clock to 65MHz and run the output video at 1024x768@60. This would allow the SE frame to be pixel doubled to 1024x684, which would only leave black bars on the top and bottom, instead of on all four sides. This could also be a useful starting point for a future project to output video for an early iPad display for units missing a CRT. ~~
\ No newline at end of file
diff --git a/SE-VGA_Schematic.pdf b/SE-VGA_Schematic.pdf
new file mode 100644
index 0000000000000000000000000000000000000000..9c3e91d909a3817af2ab34535df0d951968e7682
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From 4f08c1f6fcc058eded54a7641bb922ecec0ef4c7 Mon Sep 17 00:00:00 2001
From: techav <76832805+techav-homebrew@users.noreply.github.com>
Date: Wed, 4 Aug 2021 23:40:16 -0500
Subject: [PATCH 03/14] Start logic rebuild for XGA

Ground-up rewrite of the video timing and output logic for XGA. Much simpler than the initial VGA logic. First draft, incomplete.
---
 se-vga.sv => old/se-vga.sv           |   0
 sevga.vwf => old/sevga.vwf           |   0
 vgacount.sv => old/vgacount.sv       |   0
 vgagen.sv => old/vgagen.sv           |   0
 vgaout.sv => old/vgaout.sv           |   0
 vgashiftout.sv => old/vgashiftout.sv |   0
 vgatest.sv => old/vgatest.sv         |   0
 se-xga.sv                            | 187 +++++++++++++++++++++++++++
 8 files changed, 187 insertions(+)
 rename se-vga.sv => old/se-vga.sv (100%)
 rename sevga.vwf => old/sevga.vwf (100%)
 rename vgacount.sv => old/vgacount.sv (100%)
 rename vgagen.sv => old/vgagen.sv (100%)
 rename vgaout.sv => old/vgaout.sv (100%)
 rename vgashiftout.sv => old/vgashiftout.sv (100%)
 rename vgatest.sv => old/vgatest.sv (100%)
 create mode 100644 se-xga.sv

diff --git a/se-vga.sv b/old/se-vga.sv
similarity index 100%
rename from se-vga.sv
rename to old/se-vga.sv
diff --git a/sevga.vwf b/old/sevga.vwf
similarity index 100%
rename from sevga.vwf
rename to old/sevga.vwf
diff --git a/vgacount.sv b/old/vgacount.sv
similarity index 100%
rename from vgacount.sv
rename to old/vgacount.sv
diff --git a/vgagen.sv b/old/vgagen.sv
similarity index 100%
rename from vgagen.sv
rename to old/vgagen.sv
diff --git a/vgaout.sv b/old/vgaout.sv
similarity index 100%
rename from vgaout.sv
rename to old/vgaout.sv
diff --git a/vgashiftout.sv b/old/vgashiftout.sv
similarity index 100%
rename from vgashiftout.sv
rename to old/vgashiftout.sv
diff --git a/vgatest.sv b/old/vgatest.sv
similarity index 100%
rename from vgatest.sv
rename to old/vgatest.sv
diff --git a/se-xga.sv b/se-xga.sv
new file mode 100644
index 0000000..44eb0d7
--- /dev/null
+++ b/se-xga.sv
@@ -0,0 +1,187 @@
+/******************************************************************************
+ * SE-VGA
+ * Top-level module 
+ * techav
+ * 2021-08-04
+ ******************************************************************************
+ * Pulls together all the smaller modules to form the SE-VGA adapter
+ *****************************************************************************/
+
+module sevga (
+    input wire              nReset,     // System reset signal
+    input wire              pixClk,     // 25.175MHz pixel clock
+    output wire             nhSync,     // HSync signal
+    output wire             nvSync,     // VSync signal
+    output wire             vidOut,     // 1-bit Monochrome video signal
+
+    output logic [14:0]     vramAddr,   // VRAM Address bus
+    inout logic [7:0]       vramData,   // VRAM Data bus
+    output wire             nvramOE,    // VRAM Read strobe
+    output wire             nvramWE,    // VRAM Write strobe
+    output wire             nvramCE0,   // VRAM Main chip select signal
+    output wire             nvramCE1,   // VRAM Alt chip select signal
+
+    input logic [23:1]      cpuAddr,    // CPU Address bus
+    input logic [15:0]      cpuData,    // CPU Data bus
+    input wire              ncpuAS,     // CPU Address Strobe signal
+    input wire              ncpuUDS,    // CPU Upper Data Strobe signal
+    input wire              ncpuLDS,    // CPU Lower Data Strobe signal
+    input wire              cpuRnW,     // CPU Read/Write select signal
+    input logic [2:0]       ramSize     // Select installed RAM size
+);
+
+/******************************************************************************
+ * Initial Video Signal Timing
+ * The following four functions establish the basic XGA signal timing and 
+ * assert the horizontal and vertical sync signals as appropriate.
+ * These functions are the minimum required for a signal presence detect test.
+ *****************************************************************************/
+logic [10:0] hCount;    // 0..1343
+logic [9:0] vCount;     // 0..805
+
+// horizontal counter
+always @(negedge pixClk or negedge nReset) begin
+    if(!nReset) hCount <= 0;
+    else begin
+        if(hCount < 1343) hCount <= hCount + 1;
+        else hCount <= 0;
+    end
+end
+
+// vertical counter
+always @(negedge pixClk or negedge nReset) begin
+    if(!nReset) vCount <= 0;
+    else begin
+        if(vCount < 805) vCount <= vCount + 1;
+        else vCount <= 0;
+    end
+end
+
+// horizontal and vertical sync signals
+always_comb begin
+    if(hCount >= 1049 && hCount < 1184) nhSync <= 0;
+    else nhSync <= 1;
+
+    if(vCount >= 729 && vCount < 735) nvSync <= 0;
+    else nvSync <= 1;
+end
+
+/******************************************************************************
+ * Useful signals
+ * Here we break out a few useful signals, derived from the timing above, that
+ * will help us elsewhere.
+ *****************************************************************************/
+wire hActive, vActive;      // active video signals. vidout black when negated
+wire vidActive;             // active when both hActive and vActive asserted
+wire hLoad;                 // load pixel data from vram when asserted
+
+assign vidActive = hActive & vidActive;
+
+always_comb begin
+    if(hCount >= 1 && hCount < 1025) hActive <= 1;
+    else hActive <= 0;
+
+    if(vCount >= 0 && vCount < 684) vActive <= 1;
+    else vActive <= 0;
+
+    if(hCount >= 0 && hCount < 1024 && vActive) hLoad <= 1;
+    else hLoad <= 0;
+end
+
+/******************************************************************************
+ * Video Output Sequencing
+ * Here is the primary video output shift register sequencing.
+ * With these functions in place, it should be possible to strap the VRAM data
+ * signals and see the strapped pattern output on screen.
+ *****************************************************************************/
+logic [8:0] vidData;        // the video data we are displaying
+wire  [2:0] vidSeq;         // sequence counter, derived from hCount
+wire tick, tock;            // even/odd pulses of pixel clock divided by 2
+
+assign vidSeq = hCount[3:1];
+assign tick = !hCount[0];
+assign tock = hCount[0];
+
+always @(negedge pixClk or negedge nReset) begin
+    if(!nReset) vidData <= 0;
+    else
+        if(tock && hLoad && vidSeq == 0) begin
+            // store the VRAM data in vidData[8:1]
+            //vidData[0] <= vidData[1]; // this should actually have already been done
+            vidData[8:1] <= vramData;
+        end else if(tick && hLoad) begin
+            // shift vidData
+            vidData[7:0] <= vidData[8:1];
+            vidData[8] <= 0;
+        end
+    end
+end
+
+always_comb begin
+    // here is where the shifted video data actually gets output
+    if(vidActive) vidOut <= ~vidData[0];
+    else vidOut <= 0;
+
+    // vram read signal can be asserted here
+    if(vidActive && vidSeq == 0) nvramOE <= 0;
+    else nvramOE <= 1;
+end
+
+
+/******************************************************************************
+ * CPU Bus Snooping
+ * Watch the CPU bus for writes to the video buffer regions of memory, cache
+ * the data internally until a write slot is available, then store in VRAM.
+ * This is the last step, and it's a big one. Once this is in place and
+ * operational, the adapter should be fully operational. 
+ *****************************************************************************/
+
+// to remember for later:
+// vramCE[x] should be asserted when vidSeq == 0
+// vramOE should be asserted when vidSeq == 0 && vidActive
+// vramWE should be asserted on tock pulses of write sequences
+
+/*
+// link module that snoops cpu writes
+cpusnoop cpusnp(    
+    .nReset(nReset),
+    .pixClock(pixClk),
+    .seq(hCount[2:0]),
+    .cpuAddr(cpuAddr),
+    .cpuData(cpuData),
+    .ncpuAS(ncpuAS),
+    .ncpuUDS(ncpuUDS),
+    .ncpuLDS(ncpuLDS),
+    .cpuRnW(cpuRnW),
+    .cpuClk(cpuClk),
+    .vramAddr(cpuVramAddr),
+    .vramDataOut(cpuVramData),
+    .nvramWE(nvramWEpre),
+    .nvramCE0(nvramCE0pre),
+    .nvramCE1(nvramCE1pre),
+    .vidBufSelOut(vidBufSel),
+    .ramSize(ramSize)
+);
+*/
+
+/*
+cpusnoop cpusnp(
+    .nReset(nReset),
+    .pixClock(pixClk),
+    .seq(vidSeq),
+    .cpuAddr(cpuAddr),
+    .cpuData(cpuData),
+    .ncpuAS(ncpuAS),
+    .ncpuUDS(ncpuUDS),
+    .ncpuLDS(ncpuLDS),
+    .cpuRnW(cpuRnW),
+    .cpuClk(cpuClk),
+    .vramAddr(),
+    .vramDataOut(),
+    .nvramWE(),
+    .nvramCE0(),
+    .nvramCE1(),
+    .vidBufSelOut(),
+    .ramSize(ramSize)
+);
+*/
\ No newline at end of file

From 90d5384b906b3b26849b944203b14b43cb3e2cd4 Mon Sep 17 00:00:00 2001
From: techav <76832805+techav-homebrew@users.noreply.github.com>
Date: Thu, 7 Oct 2021 18:54:47 -0500
Subject: [PATCH 04/14] Starting new cpu snoop

---
 se-xga.sv | 67 ++++++++++++++++++++++++++++++++++++++++++++-----------
 1 file changed, 54 insertions(+), 13 deletions(-)

diff --git a/se-xga.sv b/se-xga.sv
index 44eb0d7..d4474b9 100644
--- a/se-xga.sv
+++ b/se-xga.sv
@@ -42,17 +42,17 @@ logic [9:0] vCount;     // 0..805
 // horizontal counter
 always @(negedge pixClk or negedge nReset) begin
     if(!nReset) hCount <= 0;
-    else begin
-        if(hCount < 1343) hCount <= hCount + 1;
+    else if(!pixClk) begin
+        if(hCount < 1343) hCount <= hCount + 11'd1;
         else hCount <= 0;
     end
 end
 
 // vertical counter
-always @(negedge pixClk or negedge nReset) begin
+always @(negedge nhSync or negedge nReset) begin
     if(!nReset) vCount <= 0;
-    else begin
-        if(vCount < 805) vCount <= vCount + 1;
+    else if(!pixClk) begin
+        if(vCount < 805) vCount <= vCount + 10'd1;
         else vCount <= 0;
     end
 end
@@ -75,7 +75,7 @@ wire hActive, vActive;      // active video signals. vidout black when negated
 wire vidActive;             // active when both hActive and vActive asserted
 wire hLoad;                 // load pixel data from vram when asserted
 
-assign vidActive = hActive & vidActive;
+assign vidActive = hActive & vActive;
 
 always_comb begin
     if(hCount >= 1 && hCount < 1025) hActive <= 1;
@@ -97,6 +97,7 @@ end
 logic [8:0] vidData;        // the video data we are displaying
 wire  [2:0] vidSeq;         // sequence counter, derived from hCount
 wire tick, tock;            // even/odd pulses of pixel clock divided by 2
+wire [14:0] readAddr;              // VRAM read address
 
 assign vidSeq = hCount[3:1];
 assign tick = !hCount[0];
@@ -104,8 +105,8 @@ assign tock = hCount[0];
 
 always @(negedge pixClk or negedge nReset) begin
     if(!nReset) vidData <= 0;
-    else
-        if(tock && hLoad && vidSeq == 0) begin
+    else if(!pixClk) begin
+        if(tock && hLoad && vidSeq == 3'd0) begin
             // store the VRAM data in vidData[8:1]
             //vidData[0] <= vidData[1]; // this should actually have already been done
             vidData[8:1] <= vramData;
@@ -123,8 +124,15 @@ always_comb begin
     else vidOut <= 0;
 
     // vram read signal can be asserted here
-    if(vidActive && vidSeq == 0) nvramOE <= 0;
+    if(vidActive && vidSeq == 3'd0) nvramOE <= 0;
     else nvramOE <= 1;
+
+    // we'll be interleaving VRAM accesses, so the highest address bit will be
+    // used to select between Main & Aux video buffers.
+    // hCount[4] will be used to select between SRAM chips
+    readAddr[14] <= vidBufSel;
+    readAddr[13:5] <= vCount[9:1];
+    readAddr[4:0] <= hCount[9:5];
 end
 
 
@@ -140,6 +148,20 @@ end
 // vramCE[x] should be asserted when vidSeq == 0
 // vramOE should be asserted when vidSeq == 0 && vidActive
 // vramWE should be asserted on tock pulses of write sequences
+wire [14:0] writeAddr;
+reg vidBufSel;
+wire nvramCE0cpu, nvramCE1cpu;
+
+
+reg nvramWEpre;
+
+always @(negedge pixClk or negedge nReset) begin
+    if(nReset) begin
+        nvramWEpre <= 1;
+    end else if(!pixClk && vidSeq != 0 && (!ncpuLDS || !ncpuUDS) && tock) begin
+        
+    end
+end
 
 /*
 // link module that snoops cpu writes
@@ -176,12 +198,31 @@ cpusnoop cpusnp(
     .ncpuLDS(ncpuLDS),
     .cpuRnW(cpuRnW),
     .cpuClk(cpuClk),
-    .vramAddr(),
+    .vramAddr(writeAddr),
     .vramDataOut(),
     .nvramWE(),
-    .nvramCE0(),
-    .nvramCE1(),
+    .nvramCE0(nvramCE0cpu),
+    .nvramCE1(nvramCE1cpu),
     .vidBufSelOut(),
     .ramSize(ramSize)
 );
-*/
\ No newline at end of file
+*/
+
+always_comb begin
+    if(nvramOE == 0) vramAddr <= readAddr;
+    else if(nvramWE == 0) vramAddr <= writeAddr;
+    else vramAddr <= 0;
+
+    if(nvramOE == 0) begin
+        nvramCE0 <= hCount[4];
+        nvramCE1 <= ~hCount[4];
+    end else if(nvramWE == 0) begin
+        nvramCE0 <= nvramCE0cpu;
+        nvramCE1 <= nvramCE1cpu;
+    end else begin
+        nvramCE0 <= 1;
+        nvramCE1 <= 1;
+    end
+end
+
+endmodule
\ No newline at end of file

From 3669e3a66be2ff284c0737b108a245f03627ea54 Mon Sep 17 00:00:00 2001
From: techav-homebrew <76832805+techav-homebrew@users.noreply.github.com>
Date: Thu, 7 Oct 2021 21:17:36 -0500
Subject: [PATCH 05/14] CPU Snoop First Draft

---
 se-xga.sv | 175 ++++++++++++++++++++++++++++++++++--------------------
 1 file changed, 110 insertions(+), 65 deletions(-)

diff --git a/se-xga.sv b/se-xga.sv
index d4474b9..62121ee 100644
--- a/se-xga.sv
+++ b/se-xga.sv
@@ -97,7 +97,7 @@ end
 logic [8:0] vidData;        // the video data we are displaying
 wire  [2:0] vidSeq;         // sequence counter, derived from hCount
 wire tick, tock;            // even/odd pulses of pixel clock divided by 2
-wire [14:0] readAddr;              // VRAM read address
+wire [14:0] readAddr;       // VRAM read address
 
 assign vidSeq = hCount[3:1];
 assign tick = !hCount[0];
@@ -138,79 +138,122 @@ end
 
 /******************************************************************************
  * CPU Bus Snooping
- * Watch the CPU bus for writes to the video buffer regions of memory, cache
- * the data internally until a write slot is available, then store in VRAM.
- * This is the last step, and it's a big one. Once this is in place and
- * operational, the adapter should be fully operational. 
+ * Watch the CPU bus for writes to the video buffer regions of memory and write
+ * that data to VRAM. VRAM write cycles can occur during vidSeq 1 through 7.
+ * High-order bytes are passed to VRAM on tick states and low-order bytes are 
+ * passed to VRAM on tock states. After the VRAM writes are complete, state
+ * machine waits for the CPU cycle to end before returning to idle.
  *****************************************************************************/
 
-// to remember for later:
-// vramCE[x] should be asserted when vidSeq == 0
-// vramOE should be asserted when vidSeq == 0 && vidActive
-// vramWE should be asserted on tock pulses of write sequences
-wire [14:0] writeAddr;
-reg vidBufSel;
-wire nvramCE0cpu, nvramCE1cpu;
-
-
-reg nvramWEpre;
-
-always @(negedge pixClk or negedge nReset) begin
-    if(nReset) begin
-        nvramWEpre <= 1;
-    end else if(!pixClk && vidSeq != 0 && (!ncpuLDS || !ncpuUDS) && tock) begin
-        
+// when cpu addresses the framebuffer, set our enable signal
+/* Main framebuffer starts $5900 below the top of RAM, alt frame buffer is
+ * $8000 below the main frame buffer
+ * ramSize is used to mask the CPU Address bits [21:19] to select the amount
+ * of memory installed in the computer. Not all possible ramSize selections
+ * are valid memory sizes when using 30-pin SIMMs in the Mac SE. 
+ * They may be possible using PDS RAM expansion cards.
+ * ramSize mainBuffer altBuffer ramTop+1 ramSize Valid?      Installed SIMMs
+ *    $7    $3fa700    $3f2700   $400000  4.0MB    Y    [ 1MB   1MB ][ 1MB   1MB ]
+ *    $6    $37a700    $372700   $380000  3.5MB    N
+ *    $5    $2fa700    $2f2700   $300000  3.0MB    N
+ *    $4    $27a700    $272700   $280000  2.5MB    Y    [ 1MB   1MB ][256kB 256kB]
+ *    $3    $1fa700    $1f2700   $200000  2.0MB    Y    [ 1MB   1MB ][ ---   --- ]
+ *    $2    $17a700    $172700   $180000  1.5MB    N  
+ *    $1    $0fa700    $0f2700   $100000  1.0MB    Y    [256kB 256kB][256kB 256kB]
+ *    $0    $07a700    $072700   $080000  0.5MB    Y    [256kB 256kB][ ---   --- ]
+ */
+wire cpuBufSel = ~cpuAddr[14];
+wire cpuBufAddr;
+always_comb begin
+    // remember cpuAddr is shifted right by one since 68000 does not output A0
+    if(!ncpuAS && !cpuRnW
+            && cpuAddr[22:21] == 2'b00          // initial constant
+            && ramSize == cpuAddr[20:18]        // ram size selection
+            && cpuAddr[17:15] == 3'b111         // trailing constant
+                                                // next bit is main/alt select
+            && (cpuAddr[13:0] >= 14'h1380       // bottom of buffer range (0x2700>>1)
+                && cpuAddr[13:0] <= 14'h3e3f)   // top of buffer range (0x7C70>>1)
+            ) begin
+        cpuBufAddr <= 1'b1;
+    end else begin
+        cpuBufAddr <= 1'b0;
     end
 end
 
-/*
-// link module that snoops cpu writes
-cpusnoop cpusnp(    
-    .nReset(nReset),
-    .pixClock(pixClk),
-    .seq(hCount[2:0]),
-    .cpuAddr(cpuAddr),
-    .cpuData(cpuData),
-    .ncpuAS(ncpuAS),
-    .ncpuUDS(ncpuUDS),
-    .ncpuLDS(ncpuLDS),
-    .cpuRnW(cpuRnW),
-    .cpuClk(cpuClk),
-    .vramAddr(cpuVramAddr),
-    .vramDataOut(cpuVramData),
-    .nvramWE(nvramWEpre),
-    .nvramCE0(nvramCE0pre),
-    .nvramCE1(nvramCE1pre),
-    .vidBufSelOut(vidBufSel),
-    .ramSize(ramSize)
-);
-*/
+wire [14:0] writeAddr;
+reg vidBufSel;
+wire nvramCE0cpu, nvramCE1cpu, nvramWEcpu;
+reg [1:0] snoopCycleState;
 
-/*
-cpusnoop cpusnp(
-    .nReset(nReset),
-    .pixClock(pixClk),
-    .seq(vidSeq),
-    .cpuAddr(cpuAddr),
-    .cpuData(cpuData),
-    .ncpuAS(ncpuAS),
-    .ncpuUDS(ncpuUDS),
-    .ncpuLDS(ncpuLDS),
-    .cpuRnW(cpuRnW),
-    .cpuClk(cpuClk),
-    .vramAddr(writeAddr),
-    .vramDataOut(),
-    .nvramWE(),
-    .nvramCE0(nvramCE0cpu),
-    .nvramCE1(nvramCE1cpu),
-    .vidBufSelOut(),
-    .ramSize(ramSize)
-);
-*/
+// define state machine states
+parameter
+    S0  =   2'b00,  // idle
+    S1  =   2'b01,  // write high-order byte
+    S2  =   2'b11,  // write low-order byte
+    S3  =   2'b10;  // wait for CPU cycle end
+
+always @(negedge pixClk or negedge nReset) begin
+    if(!nReset) begin snoopCycleState <= S0;
+    else begin
+        case (snoopCycleState)
+            S0 : begin
+                // idle, waiting for cpu to start a bus cycle
+                // if we're on a tock state and not about to go into a VRAM
+                // read cycle, and the CPU has asserted ncpuUDS, then we'll 
+                // move to S1 to handle the high-order byte write.
+                // If ncpuUDS is not asserted, but ncpuLDS is, and we're on a 
+                // tick state, then we'll skip on down to S2.
+                // Otherwise, we'll stay here on S0
+                if(cpuBufAddr && tock && !ncpuUDS && vidSeq != 7) snoopCycleState <= S1;
+                else if(cpuBufAddr && tick && !ncpuLDS && vidSeq != 1) snoopCycleState <= S2;
+                else snoopCycleState <= S0;
+            end
+            S1 : begin
+                // writing high-order byte to VRAM
+                // if we also need to write a low-order byte, then move to S2,
+                // else move to S3 to wait for the CPU cycle to end
+                if(!ncpuLDS) snoopCycleState <= S2;
+                else snoopCycleState <= S3;
+            end
+            S2 : begin
+                // writing low-order byte to VRAM
+                // this state will always be followed by S3
+                snoopCycleState <= S3;
+            end
+            S3 : begin
+                // waiting for CPU to end bus cycle 
+                if(!ncpuLDS || !ncpuUDS) snoopCycleState <= S3;
+                else snoopCycleState <= S0;
+            end
+            default: begin
+                // shouldn't ever be here
+                snoopCycleState <= S0;
+            end 
+        endcase
+    end
+end
+
+always_comb begin
+    if(snoopCycleState == S1) nvramCE0cpu <= 0;
+    else nvramCE0cpu <= 1;
+    if(snoopCycleState == S2) nvramCE1cpu <= 0;
+    else nvramCE1cpu <= 1;
+    if(snoopCycleState == S1 || snoopCycleState == S2) nvramWEcpu <= 0;
+    else nvramWEcpu <= 1;
+    
+    if(snoopCycleState == S1) vramData <= cpuData[15:8];
+    else if(snoopCycleState == S2) vramData <= cpuData[7:0];
+    else vramData <= 8'hZ;
+
+    writeAddr[13:0] <= cpuAddr[14:1];
+    writeAddr[14] <= cpuBufSel;
+end
+
+// Pull everything together
 
 always_comb begin
     if(nvramOE == 0) vramAddr <= readAddr;
-    else if(nvramWE == 0) vramAddr <= writeAddr;
+    else if(nvramWEcpu == 0) vramAddr <= writeAddr;
     else vramAddr <= 0;
 
     if(nvramOE == 0) begin
@@ -223,6 +266,8 @@ always_comb begin
         nvramCE0 <= 1;
         nvramCE1 <= 1;
     end
+
+    nvramWE <= nvramWEcpu;
 end
 
 endmodule
\ No newline at end of file

From 97b0b72794309abaf8ce9de6d3a93b597d573819 Mon Sep 17 00:00:00 2001
From: techav-homebrew <76832805+techav-homebrew@users.noreply.github.com>
Date: Thu, 7 Oct 2021 21:35:29 -0500
Subject: [PATCH 06/14] VIA snooping

---
 se-xga.sv | 23 +++++++++++++++++------
 1 file changed, 17 insertions(+), 6 deletions(-)

diff --git a/se-xga.sv b/se-xga.sv
index 62121ee..a9ce10d 100644
--- a/se-xga.sv
+++ b/se-xga.sv
@@ -183,14 +183,15 @@ end
 wire [14:0] writeAddr;
 reg vidBufSel;
 wire nvramCE0cpu, nvramCE1cpu, nvramWEcpu;
-reg [1:0] snoopCycleState;
+reg [2:0] snoopCycleState;
 
 // define state machine states
 parameter
-    S0  =   2'b00,  // idle
-    S1  =   2'b01,  // write high-order byte
-    S2  =   2'b11,  // write low-order byte
-    S3  =   2'b10;  // wait for CPU cycle end
+    S0  =   2'b000,   // idle
+    S1  =   2'b001,   // write high-order byte
+    S2  =   2'b011,   // write low-order byte
+    S3  =   2'b010,   // wait for CPU cycle end
+    S4  =   2'b110;   // VIA write cycle
 
 always @(negedge pixClk or negedge nReset) begin
     if(!nReset) begin snoopCycleState <= S0;
@@ -206,6 +207,9 @@ always @(negedge pixClk or negedge nReset) begin
                 // Otherwise, we'll stay here on S0
                 if(cpuBufAddr && tock && !ncpuUDS && vidSeq != 7) snoopCycleState <= S1;
                 else if(cpuBufAddr && tick && !ncpuLDS && vidSeq != 1) snoopCycleState <= S2;
+                else if(!ncpuAS && !ncpuUDS && !cpuRnW 
+                            && cpuAddr[22:18] == 5'h1D
+                            && cpuAddr[11:7]  == 5'h1F) snoopCycleState <= S4;
                 else snoopCycleState <= S0;
             end
             S1 : begin
@@ -225,6 +229,13 @@ always @(negedge pixClk or negedge nReset) begin
                 if(!ncpuLDS || !ncpuUDS) snoopCycleState <= S3;
                 else snoopCycleState <= S0;
             end
+            S4 : begin
+                // CPU is addressing VIA Port A. Bit 6 will select the active 
+                // screen buffer. 1=Main, 0=Alt
+                // After saving the selection, move to S3 to wait for cycle end
+                vidBufSel <= !cpuData[14];
+                snoopCycleState <= S3
+            end
             default: begin
                 // shouldn't ever be here
                 snoopCycleState <= S0;
@@ -245,7 +256,7 @@ always_comb begin
     else if(snoopCycleState == S2) vramData <= cpuData[7:0];
     else vramData <= 8'hZ;
 
-    writeAddr[13:0] <= cpuAddr[14:1];
+    writeAddr[13:0] <= cpuAddr[14:1] - 14'h1380;
     writeAddr[14] <= cpuBufSel;
 end
 

From 373b0ec9b5c4f2d00ef36461add52dc54ac7d20d Mon Sep 17 00:00:00 2001
From: techav <76832805+techav-homebrew@users.noreply.github.com>
Date: Sat, 9 Oct 2021 14:47:53 -0500
Subject: [PATCH 07/14] Debugging VRAM Write Timing

---
 se-xga.sv | 91 +++++++++++++++++++++++++++++--------------------------
 1 file changed, 48 insertions(+), 43 deletions(-)

diff --git a/se-xga.sv b/se-xga.sv
index a9ce10d..760b950 100644
--- a/se-xga.sv
+++ b/se-xga.sv
@@ -9,7 +9,7 @@
 
 module sevga (
     input wire              nReset,     // System reset signal
-    input wire              pixClk,     // 25.175MHz pixel clock
+    input wire              pixClk,     // 65MHz pixel clock
     output wire             nhSync,     // HSync signal
     output wire             nvSync,     // VSync signal
     output wire             vidOut,     // 1-bit Monochrome video signal
@@ -38,31 +38,33 @@ module sevga (
  *****************************************************************************/
 logic [10:0] hCount;    // 0..1343
 logic [9:0] vCount;     // 0..805
+wire nhSyncInner;
 
 // horizontal counter
 always @(negedge pixClk or negedge nReset) begin
     if(!nReset) hCount <= 0;
-    else if(!pixClk) begin
-        if(hCount < 1343) hCount <= hCount + 11'd1;
-        else hCount <= 0;
+    else begin
+        if(hCount < 11'd1343) hCount <= hCount + 11'd1;
+        else hCount <= 11'd0;
     end
 end
 
 // vertical counter
-always @(negedge nhSync or negedge nReset) begin
+always @(negedge nhSyncInner or negedge nReset) begin
     if(!nReset) vCount <= 0;
-    else if(!pixClk) begin
-        if(vCount < 805) vCount <= vCount + 10'd1;
-        else vCount <= 0;
+    else begin
+        if(vCount < 10'd805) vCount <= vCount + 10'd1;
+        else vCount <= 10'd0;
     end
 end
 
 // horizontal and vertical sync signals
 always_comb begin
-    if(hCount >= 1049 && hCount < 1184) nhSync <= 0;
-    else nhSync <= 1;
+    if(hCount >= 11'd1048 && hCount < 11'd1184) nhSyncInner <= 0;
+    else nhSyncInner <= 1;
+    nhSync <= nhSyncInner;
 
-    if(vCount >= 729 && vCount < 735) nvSync <= 0;
+    if(vCount >= 10'd729 && vCount < 10'd735) nvSync <= 0;
     else nvSync <= 1;
 end
 
@@ -78,7 +80,7 @@ wire hLoad;                 // load pixel data from vram when asserted
 assign vidActive = hActive & vActive;
 
 always_comb begin
-    if(hCount >= 1 && hCount < 1025) hActive <= 1;
+    if(hCount >= 0 && hCount < 1024) hActive <= 1;
     else hActive <= 0;
 
     if(vCount >= 0 && vCount < 684) vActive <= 1;
@@ -107,20 +109,19 @@ always @(negedge pixClk or negedge nReset) begin
     if(!nReset) vidData <= 0;
     else if(!pixClk) begin
         if(tock && hLoad && vidSeq == 3'd0) begin
-            // store the VRAM data in vidData[8:1]
-            //vidData[0] <= vidData[1]; // this should actually have already been done
-            vidData[8:1] <= vramData;
+            // store the VRAM data in vidData[7:0]
+            vidData[7:0] <= vramData;
         end else if(tick && hLoad) begin
             // shift vidData
-            vidData[7:0] <= vidData[8:1];
-            vidData[8] <= 0;
+            vidData[8:1] <= vidData[7:0];
+            vidData[0] <= 0;
         end
     end
 end
 
 always_comb begin
     // here is where the shifted video data actually gets output
-    if(vidActive) vidOut <= ~vidData[0];
+    if(vidActive) vidOut <= ~vidData[8];
     else vidOut <= 0;
 
     // vram read signal can be asserted here
@@ -162,17 +163,17 @@ end
  *    $1    $0fa700    $0f2700   $100000  1.0MB    Y    [256kB 256kB][256kB 256kB]
  *    $0    $07a700    $072700   $080000  0.5MB    Y    [256kB 256kB][ ---   --- ]
  */
-wire cpuBufSel = ~cpuAddr[14];
+wire cpuBufSel = ~cpuAddr[15];
 wire cpuBufAddr;
 always_comb begin
     // remember cpuAddr is shifted right by one since 68000 does not output A0
     if(!ncpuAS && !cpuRnW
-            && cpuAddr[22:21] == 2'b00          // initial constant
-            && ramSize == cpuAddr[20:18]        // ram size selection
-            && cpuAddr[17:15] == 3'b111         // trailing constant
+            && cpuAddr[23:22] == 2'b00          // initial constant
+            && ramSize == cpuAddr[21:19]        // ram size selection
+            && cpuAddr[18:16] == 3'b111         // trailing constant
                                                 // next bit is main/alt select
-            && (cpuAddr[13:0] >= 14'h1380       // bottom of buffer range (0x2700>>1)
-                && cpuAddr[13:0] <= 14'h3e3f)   // top of buffer range (0x7C70>>1)
+            && (cpuAddr[14:1] >= 14'h1380       // bottom of buffer range (0x2700>>1)
+                && cpuAddr[14:1] <= 14'h3e3f)   // top of buffer range (0x7C70>>1)
             ) begin
         cpuBufAddr <= 1'b1;
     end else begin
@@ -187,14 +188,14 @@ reg [2:0] snoopCycleState;
 
 // define state machine states
 parameter
-    S0  =   2'b000,   // idle
-    S1  =   2'b001,   // write high-order byte
-    S2  =   2'b011,   // write low-order byte
-    S3  =   2'b010,   // wait for CPU cycle end
-    S4  =   2'b110;   // VIA write cycle
+    S0  =   3'b000,   // idle
+    S1  =   3'b001,   // write high-order byte
+    S2  =   3'b011,   // write low-order byte
+    S3  =   3'b010,   // wait for CPU cycle end
+    S4  =   3'b110;   // VIA write cycle
 
 always @(negedge pixClk or negedge nReset) begin
-    if(!nReset) begin snoopCycleState <= S0;
+    if(!nReset) snoopCycleState <= S0;
     else begin
         case (snoopCycleState)
             S0 : begin
@@ -205,24 +206,26 @@ always @(negedge pixClk or negedge nReset) begin
                 // If ncpuUDS is not asserted, but ncpuLDS is, and we're on a 
                 // tick state, then we'll skip on down to S2.
                 // Otherwise, we'll stay here on S0
-                if(cpuBufAddr && tock && !ncpuUDS && vidSeq != 7) snoopCycleState <= S1;
-                else if(cpuBufAddr && tick && !ncpuLDS && vidSeq != 1) snoopCycleState <= S2;
+                if(cpuBufAddr && tock && !ncpuUDS && vidSeq != 7 && tock) snoopCycleState <= S1;
+                else if(cpuBufAddr && tick && !ncpuLDS && vidSeq != 1 && tock) snoopCycleState <= S2;
                 else if(!ncpuAS && !ncpuUDS && !cpuRnW 
-                            && cpuAddr[22:18] == 5'h1D
-                            && cpuAddr[11:7]  == 5'h1F) snoopCycleState <= S4;
+                            && cpuAddr[23:19] == 5'h1D
+                            && cpuAddr[12:8]  == 5'h1F) snoopCycleState <= S4;
                 else snoopCycleState <= S0;
             end
             S1 : begin
                 // writing high-order byte to VRAM
                 // if we also need to write a low-order byte, then move to S2,
                 // else move to S3 to wait for the CPU cycle to end
-                if(!ncpuLDS) snoopCycleState <= S2;
-                else snoopCycleState <= S3;
+                if(!ncpuLDS && tock) snoopCycleState <= S2;
+                else if(tock) snoopCycleState <= S3;
+                else snoopCycleState <= S1;
             end
             S2 : begin
                 // writing low-order byte to VRAM
                 // this state will always be followed by S3
-                snoopCycleState <= S3;
+                if(tock) snoopCycleState <= S3;
+                else snoopCycleState <= S2;
             end
             S3 : begin
                 // waiting for CPU to end bus cycle 
@@ -234,10 +237,10 @@ always @(negedge pixClk or negedge nReset) begin
                 // screen buffer. 1=Main, 0=Alt
                 // After saving the selection, move to S3 to wait for cycle end
                 vidBufSel <= !cpuData[14];
-                snoopCycleState <= S3
+                snoopCycleState <= S3;
             end
             default: begin
-                // shouldn't ever be here
+                // generally shouldn't be here
                 snoopCycleState <= S0;
             end 
         endcase
@@ -245,9 +248,9 @@ always @(negedge pixClk or negedge nReset) begin
 end
 
 always_comb begin
-    if(snoopCycleState == S1) nvramCE0cpu <= 0;
+    if(snoopCycleState == S1 && tick) nvramCE0cpu <= 0;
     else nvramCE0cpu <= 1;
-    if(snoopCycleState == S2) nvramCE1cpu <= 0;
+    if(snoopCycleState == S2 && tick) nvramCE1cpu <= 0;
     else nvramCE1cpu <= 1;
     if(snoopCycleState == S1 || snoopCycleState == S2) nvramWEcpu <= 0;
     else nvramWEcpu <= 1;
@@ -270,7 +273,7 @@ always_comb begin
     if(nvramOE == 0) begin
         nvramCE0 <= hCount[4];
         nvramCE1 <= ~hCount[4];
-    end else if(nvramWE == 0) begin
+    end else if(!nvramWEcpu) begin
         nvramCE0 <= nvramCE0cpu;
         nvramCE1 <= nvramCE1cpu;
     end else begin
@@ -278,7 +281,9 @@ always_comb begin
         nvramCE1 <= 1;
     end
 
-    nvramWE <= nvramWEcpu;
+    // make sure vram WE and OE signals aren't asserted simultaneously
+    if(!nvramWEcpu && nvramOE) nvramWE <= 0;
+    else nvramWE <= 1;
 end
 
 endmodule
\ No newline at end of file

From 6f2f67ef050ae41c58b53dd648b2a3db4a1352fc Mon Sep 17 00:00:00 2001
From: techav <76832805+techav-homebrew@users.noreply.github.com>
Date: Mon, 11 Oct 2021 16:25:40 -0500
Subject: [PATCH 08/14] New State Machine

---
 se-xga.sv | 336 +++++++++++++++++++++++++++++++++++-------------------
 1 file changed, 221 insertions(+), 115 deletions(-)

diff --git a/se-xga.sv b/se-xga.sv
index 760b950..76b06d0 100644
--- a/se-xga.sv
+++ b/se-xga.sv
@@ -90,6 +90,179 @@ always_comb begin
     else hLoad <= 0;
 end
 
+/******************************************************************************
+ * Primary State Machine
+ * This is the primary state machine which runs the entire system, handling
+ * VRAM reads, VRAM writes, VIA writes, and idle states
+ *****************************************************************************/
+
+// define state machine states (Gray code)
+parameter
+    P0  =   4'b0000,    // VRAM Read 0
+    P1  =   4'b0001,    // VRAM Read 1
+    P2  =   4'b0011,    // Idle 0
+    P3  =   4'b0010,    // Idle 1
+    P4  =   4'b0110,    // VRAM Write Upper 0
+    P5  =   4'b0111,    // VRAM Write Upper 1
+    P6  =   4'b0101,    // VRAM Write Lower 0
+    P7  =   4'b0100,    // VRAM Write Lower 1
+    P8  =   4'b1100,    // VIA Write 0
+    P9  =   4'b1101,    // VIA Write 1
+    P10 =   4'b1111,    // undefined
+    P11 =   4'b1110,    // undefined
+    P12 =   4'b1010,    // undefined
+    P13 =   4'b1011,    // undefined
+    P14 =   4'b1001,    // undefined
+    P15 =   4'b1000;    // undefined
+
+logic [3:0] pState;
+
+always @(negedge pixClk or negedge nReset) begin
+    if(!nReset) pState <= P0;
+    else begin
+        case (pState)
+            P0  :   begin
+                // first VRAM read state, always move to P1
+                pState <= P1;
+            end
+            P1  :   begin
+                // move to appropriate VRAM write state or idle
+                if(cpuUWriteReq && !cpuUWriteSrv) pState <= P4;
+                else if(cpuLWriteReq && !cpuLWriteSrv) pState <= P6;
+                else if(cpuVIAReq && !cpuVIASrv) pState <= P8;
+                else pState <= P2;
+            end
+            P2  :   begin
+                // first idle state.
+                // we'll use this state to make sure we're synchronized with 
+                // the tick-tock clock states, so if we've made it here on a
+                // tock state, stay here until the next tick state.
+                if(tick) pState <= P3;
+                else pState <= P2;
+            end
+            P3  :   begin
+                // second idle state. Here is where things get fun.
+                case (vidSeq)
+                    7 : begin
+                        pState <= P0;
+                    end
+                    6 : begin
+                        if(cpuUWriteReq && !cpuUWriteSrv && !cpuLWriteReq) pState <= P4;
+                        else if(cpuLWriteReq && !cpuLWriteSrv) pState <= P6;
+                        else if(cpuVIAReq && !cpuVIASrv) pState <= P8;
+                        else pState <= P2;
+                    end
+                    default: begin
+                        if(cpuUWriteReq && !cpuUWriteSrv) pState <= P4;
+                        else if(cpuLWriteReq && !cpuLWriteSrv) pState <= P6;
+                        else if(cpuVIAReq && !cpuVIASrv) pState <= P8;
+                        else pState <= P2;
+                    end
+                endcase
+            end
+            P4  :   begin
+                // first VRAM Write Upper state, always move to P5
+                pState <= P5;
+            end
+            P5  :   begin
+                // second VRAM Write Upper state,
+                if(vidSeq == 7) pState <= P0;
+                else if(cpuBufAddr && !ncpuLDS) pState <= P6;
+                else pState <= P2;
+            end
+            P6  :   begin
+                // first VRAM Write Lower state, always move to P7
+                pState <= P7;
+            end
+            P7  :   begin
+                // second VRAM Write Lower state
+                if(vidSeq == 7) pState <= P0;
+                else pState <= P2;
+            end
+            P8  :   begin
+                // first VIA write state, always move to P9
+                pState <= P9;
+            end
+            P9  :   begin
+                // second VIA write state
+                vidBufSel <= ~cpuData[14];
+                if(vidSeq == 7) pState <= P0;
+                else pState <= P2;
+            end
+            default: begin
+                // how did we end up here? We need to align with the sequence 
+                // counter before we move to S0
+                if(vidSeq == 7 && tock) pState <= P0;
+                else if(tick) pState <= P3;
+                else pState <= P2;
+            end
+        endcase
+    end
+end
+
+// primary signal combination, based on the state machine above
+always_comb begin
+    // VRAM Read strobe
+    if((pState == P0 || pState == P1) && vidActive) nvramOE <= 0;
+    else nvramOE <= 1;
+
+    // VRAM Write strobe
+    if(pState == P4 || pState == P6) nvramWE <= 0;
+    else nvramWE <= 1;
+
+    // VRAM Chip Enable signals
+    case(pState)
+        P0, P1 : begin
+            if(vidActive) begin
+                nvramCE0 <= hCount[4];
+                nvramCE1 <= ~hCount[4];
+            end else begin
+                nvramCE0 <= 1;
+                nvramCE1 <= 1;
+            end
+        end
+        P4, P5 : begin
+            nvramCE0 <= 0;
+            nvramCE1 <= 1;
+        end
+        P6, P7 : begin
+            nvramCE0 <= 1;
+            nvramCE1 <= 0;
+        end
+        default: begin
+            nvramCE0 <= 1;
+            nvramCE1 <= 1;
+        end
+    endcase
+
+    // VRAM Address bus
+    case(pState)
+        P0, P1 : begin
+            if(hLoad) begin
+                vramAddr[14] <= vidBufSel;
+                vramAddr[13:5] <= vCount[9:1];
+                vramAddr[4:0] <= hCount[9:5];
+            end else begin
+                vramAddr <= 0;
+            end
+        end
+        P4, P5, P6, P7 : begin
+            vramAddr[14] <= cpuBufSel;
+            vramAddr[13:0] <= cpuAddr[14:1] - 14'h1380;
+        end
+        default: begin
+            vramAddr <= 0;
+        end
+    endcase
+
+    // VRAM Data bus
+    case(pState)
+        P4, P5 : vramData <= cpuData[15:8];
+        P6, P7 : vramData <= cpuData[7:0];
+        default: vramData <= 8'hZ;
+    endcase
+end
+
 /******************************************************************************
  * Video Output Sequencing
  * Here is the primary video output shift register sequencing.
@@ -99,16 +272,20 @@ end
 logic [8:0] vidData;        // the video data we are displaying
 wire  [2:0] vidSeq;         // sequence counter, derived from hCount
 wire tick, tock;            // even/odd pulses of pixel clock divided by 2
-wire [14:0] readAddr;       // VRAM read address
 
 assign vidSeq = hCount[3:1];
 assign tick = !hCount[0];
 assign tock = hCount[0];
 
+// for some reason changing this function to use pState==P1 instead of the old
+// tock && vidSeq==0 caused utilization to jump up 10 macrocells, and the 
+// monitor reported sync out of range. No idea what happened there so we'll 
+// leave this function as it is, since it seems to be working. 
 always @(negedge pixClk or negedge nReset) begin
     if(!nReset) vidData <= 0;
-    else if(!pixClk) begin
+    else begin
         if(tock && hLoad && vidSeq == 3'd0) begin
+        //if(pState == P1 && hLoad) begin
             // store the VRAM data in vidData[7:0]
             vidData[7:0] <= vramData;
         end else if(tick && hLoad) begin
@@ -123,17 +300,6 @@ always_comb begin
     // here is where the shifted video data actually gets output
     if(vidActive) vidOut <= ~vidData[8];
     else vidOut <= 0;
-
-    // vram read signal can be asserted here
-    if(vidActive && vidSeq == 3'd0) nvramOE <= 0;
-    else nvramOE <= 1;
-
-    // we'll be interleaving VRAM accesses, so the highest address bit will be
-    // used to select between Main & Aux video buffers.
-    // hCount[4] will be used to select between SRAM chips
-    readAddr[14] <= vidBufSel;
-    readAddr[13:5] <= vCount[9:1];
-    readAddr[4:0] <= hCount[9:5];
 end
 
 
@@ -146,7 +312,6 @@ end
  * machine waits for the CPU cycle to end before returning to idle.
  *****************************************************************************/
 
-// when cpu addresses the framebuffer, set our enable signal
 /* Main framebuffer starts $5900 below the top of RAM, alt frame buffer is
  * $8000 below the main frame buffer
  * ramSize is used to mask the CPU Address bits [21:19] to select the amount
@@ -163,8 +328,15 @@ end
  *    $1    $0fa700    $0f2700   $100000  1.0MB    Y    [256kB 256kB][256kB 256kB]
  *    $0    $07a700    $072700   $080000  0.5MB    Y    [256kB 256kB][ ---   --- ]
  */
+
+// keep track of pending CPU write requests and whether they have been serviced
+wire cpuUWriteReq, cpuLWriteReq, cpuVIAReq;
+reg  cpuUWriteSrv, cpuLWriteSrv, cpuVIASrv;
 wire cpuBufSel = ~cpuAddr[15];
 wire cpuBufAddr;
+reg vidBufSel;
+
+// these are some helpful signals that shortcut the CPU buffer & VIA addresses
 always_comb begin
     // remember cpuAddr is shifted right by one since 68000 does not output A0
     if(!ncpuAS && !cpuRnW
@@ -179,111 +351,45 @@ always_comb begin
     end else begin
         cpuBufAddr <= 1'b0;
     end
+
+    if(cpuBufAddr && !ncpuUDS) cpuUWriteReq <= 1;
+    else cpuUWriteReq <= 0;
+    if(cpuBufAddr && !ncpuLDS) cpuLWriteReq <= 1;
+    else cpuLWriteReq <= 0;
+
+    if(!ncpuAS && !cpuRnW && !ncpuUDS
+            && cpuAddr[23:19] == 5'h1D
+            && cpuAddr[12:8]  == 5'h1F) cpuVIAReq <= 1;
+    else cpuVIAReq <= 0;
 end
 
-wire [14:0] writeAddr;
-reg vidBufSel;
-wire nvramCE0cpu, nvramCE1cpu, nvramWEcpu;
-reg [2:0] snoopCycleState;
-
-// define state machine states
-parameter
-    S0  =   3'b000,   // idle
-    S1  =   3'b001,   // write high-order byte
-    S2  =   3'b011,   // write low-order byte
-    S3  =   3'b010,   // wait for CPU cycle end
-    S4  =   3'b110;   // VIA write cycle
-
-always @(negedge pixClk or negedge nReset) begin
-    if(!nReset) snoopCycleState <= S0;
-    else begin
-        case (snoopCycleState)
-            S0 : begin
-                // idle, waiting for cpu to start a bus cycle
-                // if we're on a tock state and not about to go into a VRAM
-                // read cycle, and the CPU has asserted ncpuUDS, then we'll 
-                // move to S1 to handle the high-order byte write.
-                // If ncpuUDS is not asserted, but ncpuLDS is, and we're on a 
-                // tick state, then we'll skip on down to S2.
-                // Otherwise, we'll stay here on S0
-                if(cpuBufAddr && tock && !ncpuUDS && vidSeq != 7 && tock) snoopCycleState <= S1;
-                else if(cpuBufAddr && tick && !ncpuLDS && vidSeq != 1 && tock) snoopCycleState <= S2;
-                else if(!ncpuAS && !ncpuUDS && !cpuRnW 
-                            && cpuAddr[23:19] == 5'h1D
-                            && cpuAddr[12:8]  == 5'h1F) snoopCycleState <= S4;
-                else snoopCycleState <= S0;
-            end
-            S1 : begin
-                // writing high-order byte to VRAM
-                // if we also need to write a low-order byte, then move to S2,
-                // else move to S3 to wait for the CPU cycle to end
-                if(!ncpuLDS && tock) snoopCycleState <= S2;
-                else if(tock) snoopCycleState <= S3;
-                else snoopCycleState <= S1;
-            end
-            S2 : begin
-                // writing low-order byte to VRAM
-                // this state will always be followed by S3
-                if(tock) snoopCycleState <= S3;
-                else snoopCycleState <= S2;
-            end
-            S3 : begin
-                // waiting for CPU to end bus cycle 
-                if(!ncpuLDS || !ncpuUDS) snoopCycleState <= S3;
-                else snoopCycleState <= S0;
-            end
-            S4 : begin
-                // CPU is addressing VIA Port A. Bit 6 will select the active 
-                // screen buffer. 1=Main, 0=Alt
-                // After saving the selection, move to S3 to wait for cycle end
-                vidBufSel <= !cpuData[14];
-                snoopCycleState <= S3;
-            end
-            default: begin
-                // generally shouldn't be here
-                snoopCycleState <= S0;
-            end 
-        endcase
-    end
-end
-
-always_comb begin
-    if(snoopCycleState == S1 && tick) nvramCE0cpu <= 0;
-    else nvramCE0cpu <= 1;
-    if(snoopCycleState == S2 && tick) nvramCE1cpu <= 0;
-    else nvramCE1cpu <= 1;
-    if(snoopCycleState == S1 || snoopCycleState == S2) nvramWEcpu <= 0;
-    else nvramWEcpu <= 1;
-    
-    if(snoopCycleState == S1) vramData <= cpuData[15:8];
-    else if(snoopCycleState == S2) vramData <= cpuData[7:0];
-    else vramData <= 8'hZ;
-
-    writeAddr[13:0] <= cpuAddr[14:1] - 14'h1380;
-    writeAddr[14] <= cpuBufSel;
-end
-
-// Pull everything together
-
-always_comb begin
-    if(nvramOE == 0) vramAddr <= readAddr;
-    else if(nvramWEcpu == 0) vramAddr <= writeAddr;
-    else vramAddr <= 0;
-
-    if(nvramOE == 0) begin
-        nvramCE0 <= hCount[4];
-        nvramCE1 <= ~hCount[4];
-    end else if(!nvramWEcpu) begin
-        nvramCE0 <= nvramCE0cpu;
-        nvramCE1 <= nvramCE1cpu;
+// if there's an active CPU request and we've reached the state for servicing
+// that CPU request, then set a flag to mark that we have serviced it
+always @(posedge pixClk or posedge ncpuAS) begin
+    if(ncpuAS) begin
+        cpuUWriteSrv <= 0;
+        cpuLWriteSrv <= 0;
+        cpuVIASrv    <= 0;
     end else begin
-        nvramCE0 <= 1;
-        nvramCE1 <= 1;
+        if(ncpuAS) begin
+            cpuUWriteSrv <= 0;
+            cpuLWriteSrv <= 0;
+            cpuVIASrv    <= 0;
+        end else begin
+            if(cpuUWriteReq && pState == P4) cpuUWriteSrv <= 1;
+            if(cpuLWriteReq && pState == P6) cpuLWriteSrv <= 1;
+            if(cpuVIAReq    && pState == P8) cpuVIASrv    <= 1;
+        end
     end
-
-    // make sure vram WE and OE signals aren't asserted simultaneously
-    if(!nvramWEcpu && nvramOE) nvramWE <= 0;
-    else nvramWE <= 1;
 end
 
+// when servicing a CPU VIA request, read the CPU data bus to set the video
+// buffer selection bit. Main: 1, Alt: 0
+/*always @(posedge pixClk or negedge nReset) begin
+    if(!nReset) vidBufSel <= 1;
+    else if(pState == P8) begin
+        vidBufSel <= ~cpuData[14];
+    end
+end*/
+
 endmodule
\ No newline at end of file

From 5377d058954347f3e41ad882ad58205fbfac61e7 Mon Sep 17 00:00:00 2001
From: techav <76832805+techav-homebrew@users.noreply.github.com>
Date: Mon, 11 Oct 2021 21:25:28 -0500
Subject: [PATCH 09/14] Rebuilt state machine again

---
 se-xga.sv | 303 ++++++++++++++++++++++--------------------------------
 1 file changed, 122 insertions(+), 181 deletions(-)

diff --git a/se-xga.sv b/se-xga.sv
index 76b06d0..9d66adf 100644
--- a/se-xga.sv
+++ b/se-xga.sv
@@ -40,19 +40,11 @@ logic [10:0] hCount;    // 0..1343
 logic [9:0] vCount;     // 0..805
 wire nhSyncInner;
 
-// horizontal counter
-always @(negedge pixClk or negedge nReset) begin
-    if(!nReset) hCount <= 0;
-    else begin
-        if(hCount < 11'd1343) hCount <= hCount + 11'd1;
-        else hCount <= 11'd0;
-    end
-end
-
-// vertical counter
-always @(negedge nhSyncInner or negedge nReset) begin
-    if(!nReset) vCount <= 0;
+// Primary video sync counters -- Now more synchronous!
+always @(negedge pixClk) begin
+    if(hCount < 11'd1343) hCount <= hCount + 11'd1;
     else begin
+        hCount <= 11'd0;
         if(vCount < 10'd805) vCount <= vCount + 10'd1;
         else vCount <= 10'd0;
     end
@@ -96,138 +88,79 @@ end
  * VRAM reads, VRAM writes, VIA writes, and idle states
  *****************************************************************************/
 
+// used to align primary state machine with horizontal counter
+wire [3:0] vSeq = hCount[3:0];
+
 // define state machine states (Gray code)
 parameter
-    P0  =   4'b0000,    // VRAM Read 0
-    P1  =   4'b0001,    // VRAM Read 1
-    P2  =   4'b0011,    // Idle 0
-    P3  =   4'b0010,    // Idle 1
-    P4  =   4'b0110,    // VRAM Write Upper 0
-    P5  =   4'b0111,    // VRAM Write Upper 1
-    P6  =   4'b0101,    // VRAM Write Lower 0
-    P7  =   4'b0100,    // VRAM Write Lower 1
-    P8  =   4'b1100,    // VIA Write 0
-    P9  =   4'b1101,    // VIA Write 1
-    P10 =   4'b1111,    // undefined
-    P11 =   4'b1110,    // undefined
-    P12 =   4'b1010,    // undefined
-    P13 =   4'b1011,    // undefined
-    P14 =   4'b1001,    // undefined
-    P15 =   4'b1000;    // undefined
+    S0  =   4'b0000,    // VRAM Read 0
+    S1  =   4'b0001,    // VRAM Read 1
+    S2  =   4'b0011,    // Idle
+    S3  =   4'b0010,    // VRAM Write Upper 0
+    S4  =   4'b0110,    // VRAM Write Upper 1
+    S5  =   4'b0111,    // VRAM Write Lower 0
+    S6  =   4'b0101,    // VRAM Write Lower 1
+    S7  =   4'b0100,    // VIA Write
+    S8  =   4'b1100,    // VSync (to be added later)
+    S9  =   4'b1101,    // undefined
+    S10 =   4'b1111,    // undefined
+    S11 =   4'b1110,    // undefined
+    S12 =   4'b1010,    // undefined
+    S13 =   4'b1011,    // undefined
+    S14 =   4'b1001,    // undefined
+    S15 =   4'b1000;    // undefined
 
 logic [3:0] pState;
 
+// And here is the much simplified primary state machine
 always @(negedge pixClk or negedge nReset) begin
-    if(!nReset) pState <= P0;
+    if(!nReset) pState <= S2;   // resync on reset by jumping to idle state
     else begin
-        case (pState)
-            P0  :   begin
-                // first VRAM read state, always move to P1
-                pState <= P1;
-            end
-            P1  :   begin
-                // move to appropriate VRAM write state or idle
-                if(cpuUWriteReq && !cpuUWriteSrv) pState <= P4;
-                else if(cpuLWriteReq && !cpuLWriteSrv) pState <= P6;
-                else if(cpuVIAReq && !cpuVIASrv) pState <= P8;
-                else pState <= P2;
-            end
-            P2  :   begin
-                // first idle state.
-                // we'll use this state to make sure we're synchronized with 
-                // the tick-tock clock states, so if we've made it here on a
-                // tock state, stay here until the next tick state.
-                if(tick) pState <= P3;
-                else pState <= P2;
-            end
-            P3  :   begin
-                // second idle state. Here is where things get fun.
-                case (vidSeq)
-                    7 : begin
-                        pState <= P0;
-                    end
-                    6 : begin
-                        if(cpuUWriteReq && !cpuUWriteSrv && !cpuLWriteReq) pState <= P4;
-                        else if(cpuLWriteReq && !cpuLWriteSrv) pState <= P6;
-                        else if(cpuVIAReq && !cpuVIASrv) pState <= P8;
-                        else pState <= P2;
-                    end
-                    default: begin
-                        if(cpuUWriteReq && !cpuUWriteSrv) pState <= P4;
-                        else if(cpuLWriteReq && !cpuLWriteSrv) pState <= P6;
-                        else if(cpuVIAReq && !cpuVIASrv) pState <= P8;
-                        else pState <= P2;
-                    end
-                endcase
-            end
-            P4  :   begin
-                // first VRAM Write Upper state, always move to P5
-                pState <= P5;
-            end
-            P5  :   begin
-                // second VRAM Write Upper state,
-                if(vidSeq == 7) pState <= P0;
-                else if(cpuBufAddr && !ncpuLDS) pState <= P6;
-                else pState <= P2;
-            end
-            P6  :   begin
-                // first VRAM Write Lower state, always move to P7
-                pState <= P7;
-            end
-            P7  :   begin
-                // second VRAM Write Lower state
-                if(vidSeq == 7) pState <= P0;
-                else pState <= P2;
-            end
-            P8  :   begin
-                // first VIA write state, always move to P9
-                pState <= P9;
-            end
-            P9  :   begin
-                // second VIA write state
-                vidBufSel <= ~cpuData[14];
-                if(vidSeq == 7) pState <= P0;
-                else pState <= P2;
-            end
-            default: begin
-                // how did we end up here? We need to align with the sequence 
-                // counter before we move to S0
-                if(vidSeq == 7 && tock) pState <= P0;
-                else if(tick) pState <= P3;
-                else pState <= P2;
+        case(pState)
+            S0: pState <= S1;   // first VRAM read state, always move to S1
+            S3: pState <= S4;   // first UDS write state, always move to S4
+            S5: pState <= S6;   // first LDS write state, always move to S6
+            /*S7: begin
+                
+                pState <= S2;
+            end*/
+            S2: begin
+                // here is where everything actually happens.
+                if(vSeq == 4'hF) pState <= S0;   // time for a read state
+                else if(cpuUWriteReq && !cpuUWriteSrv && vSeq < 4'hD) pState <= S3;
+                else if(cpuLWriteReq && !cpuLWriteSrv && vSeq < 4'hD) pState <= S5;
+                else if(cpuVIAReq    && !cpuVIASrv    && vSeq < 4'hE) pState <= S7;
+                else pState <= S2;
             end
+            default: pState <= S2; // everyone ends up at S2 (idle)
         endcase
     end
 end
 
-// primary signal combination, based on the state machine above
+// primary VRAM signal combination, based on the primary state machine
 always_comb begin
-    // VRAM Read strobe
-    if((pState == P0 || pState == P1) && vidActive) nvramOE <= 0;
+    // VRAM Read Strobe
+    if((pState == S0 || pState == S1) && hLoad) nvramOE <= 0;
     else nvramOE <= 1;
 
-    // VRAM Write strobe
-    if(pState == P4 || pState == P6) nvramWE <= 0;
+    // VRAM Write Strobe
+    if(pState == S3 || pState == S5) nvramWE <= 0;
     else nvramWE <= 1;
-
-    // VRAM Chip Enable signals
+    
+    // VRAM Chip Enable Signals
     case(pState)
-        P0, P1 : begin
-            if(vidActive) begin
-                nvramCE0 <= hCount[4];
-                nvramCE1 <= ~hCount[4];
+        S0, S1: begin
+            if(hLoad) begin
+                nvramCE0 <= ~vidBufSel;
+                nvramCE1 <= vidBufSel;
             end else begin
                 nvramCE0 <= 1;
                 nvramCE1 <= 1;
             end
         end
-        P4, P5 : begin
-            nvramCE0 <= 0;
-            nvramCE1 <= 1;
-        end
-        P6, P7 : begin
-            nvramCE0 <= 1;
-            nvramCE1 <= 0;
+        S3, S4, S5, S6: begin
+            nvramCE0 <= ~cpuBufSel;
+            nvramCE1 <= cpuBufSel;
         end
         default: begin
             nvramCE0 <= 1;
@@ -235,30 +168,37 @@ always_comb begin
         end
     endcase
 
-    // VRAM Address bus
+    // VRAM Address Bus
     case(pState)
-        P0, P1 : begin
+        S0, S1: begin
+            // address bus for read cycles
             if(hLoad) begin
-                vramAddr[14] <= vidBufSel;
-                vramAddr[13:5] <= vCount[9:1];
-                vramAddr[4:0] <= hCount[9:5];
+                vramAddr[14:6] <= vCount[9:1];
+                vramAddr[5:0] <= hCount[9:4];
             end else begin
                 vramAddr <= 0;
             end
         end
-        P4, P5, P6, P7 : begin
-            vramAddr[14] <= cpuBufSel;
-            vramAddr[13:0] <= cpuAddr[14:1] - 14'h1380;
+        S3, S4: begin
+            // address bus for upper write cycles
+            vramAddr[14:1] <= cpuAddr[14:1] - 14'h1380;
+            vramAddr[0] <= 0;
+        end
+        S5, S6: begin
+            // address bus for lower write cycles
+            vramAddr[14:1] <= cpuAddr[14:1] - 14'h1380;
+            vramAddr[0] <= 1;
         end
         default: begin
+            // address bus for idle cycles
             vramAddr <= 0;
         end
     endcase
 
     // VRAM Data bus
     case(pState)
-        P4, P5 : vramData <= cpuData[15:8];
-        P6, P7 : vramData <= cpuData[7:0];
+        S3, S4 : vramData <= cpuData[15:8];
+        S5, S6 : vramData <= cpuData[7:0];
         default: vramData <= 8'hZ;
     endcase
 end
@@ -270,39 +210,27 @@ end
  * signals and see the strapped pattern output on screen.
  *****************************************************************************/
 logic [8:0] vidData;        // the video data we are displaying
-wire  [2:0] vidSeq;         // sequence counter, derived from hCount
-wire tick, tock;            // even/odd pulses of pixel clock divided by 2
+//wire  [2:0] vidSeq;         // sequence counter, derived from hCount
+//wire tick, tock;            // even/odd pulses of pixel clock divided by 2
 
-assign vidSeq = hCount[3:1];
-assign tick = !hCount[0];
-assign tock = hCount[0];
-
-// for some reason changing this function to use pState==P1 instead of the old
-// tock && vidSeq==0 caused utilization to jump up 10 macrocells, and the 
-// monitor reported sync out of range. No idea what happened there so we'll 
-// leave this function as it is, since it seems to be working. 
-always @(negedge pixClk or negedge nReset) begin
-    if(!nReset) vidData <= 0;
-    else begin
-        if(tock && hLoad && vidSeq == 3'd0) begin
-        //if(pState == P1 && hLoad) begin
-            // store the VRAM data in vidData[7:0]
-            vidData[7:0] <= vramData;
-        end else if(tick && hLoad) begin
-            // shift vidData
-            vidData[8:1] <= vidData[7:0];
-            vidData[0] <= 0;
-        end
+// output shift register
+always @(posedge pixClk) begin
+    if(pState == S1 && hLoad) begin
+        // store VRAM data in shift register
+        vidData[7:0] <= vramData;
+    end else if(!hCount[0] && vidActive) begin
+        // shift out video data
+        vidData[8:1] <= vidData[7:0];
+        vidData[0] <= 0;
     end
 end
 
+// final video output
 always_comb begin
-    // here is where the shifted video data actually gets output
     if(vidActive) vidOut <= ~vidData[8];
     else vidOut <= 0;
 end
 
-
 /******************************************************************************
  * CPU Bus Snooping
  * Watch the CPU bus for writes to the video buffer regions of memory and write
@@ -332,34 +260,49 @@ end
 // keep track of pending CPU write requests and whether they have been serviced
 wire cpuUWriteReq, cpuLWriteReq, cpuVIAReq;
 reg  cpuUWriteSrv, cpuLWriteSrv, cpuVIASrv;
-wire cpuBufSel = ~cpuAddr[15];
+wire cpuBufSel;
 wire cpuBufAddr;
 reg vidBufSel;
 
 // these are some helpful signals that shortcut the CPU buffer & VIA addresses
 always_comb begin
-    // remember cpuAddr is shifted right by one since 68000 does not output A0
     if(!ncpuAS && !cpuRnW
-            && cpuAddr[23:22] == 2'b00          // initial constant
-            && ramSize == cpuAddr[21:19]        // ram size selection
-            && cpuAddr[18:16] == 3'b111         // trailing constant
-                                                // next bit is main/alt select
-            && (cpuAddr[14:1] >= 14'h1380       // bottom of buffer range (0x2700>>1)
-                && cpuAddr[14:1] <= 14'h3e3f)   // top of buffer range (0x7C70>>1)
-            ) begin
-        cpuBufAddr <= 1'b1;
+            && !cpuAddr[23] && !cpuAddr[22]     // first two bits always 0
+            && !(cpuAddr[21] ^ ramSize[2])      // compare with RAM Size bits
+            && !(cpuAddr[20] ^ ramSize[1])
+            && !(cpuAddr[19] ^ ramSize[0])
+            && cpuAddr[18] && cpuAddr[17]       // next three bits always 1
+            && cpuAddr[16]                      // skip 15, it selects buffers
+            && (cpuAddr[14] || cpuAddr[13])     // if neither 13|14 then not buffer
+    ) begin
+        cpuBufAddr <= 1;
     end else begin
-        cpuBufAddr <= 1'b0;
+        cpuBufAddr <= 0;
     end
+    cpuBufSel <= ~cpuAddr[15];                   // address bit 15 selects buffer
 
     if(cpuBufAddr && !ncpuUDS) cpuUWriteReq <= 1;
     else cpuUWriteReq <= 0;
     if(cpuBufAddr && !ncpuLDS) cpuLWriteReq <= 1;
     else cpuLWriteReq <= 0;
 
-    if(!ncpuAS && !cpuRnW && !ncpuUDS
-            && cpuAddr[23:19] == 5'h1D
-            && cpuAddr[12:8]  == 5'h1F) cpuVIAReq <= 1;
+    // VIA is in address block $E8,0000 - $EF,FFFF
+    // VIA register select pins (RS[3:0]) are wired to cpuAddr[12:9]
+    // VIA Output Register A is selected when RS[3:0]==$F
+    /*if(!ncpuAS && !cpuRnW && !ncpuUDS
+            && cpuAddr[23] && cpuAddr[22]       // VIA Address Select
+            && cpuAddr[21] && !cpuAddr[20]
+            && cpuAddr[19]
+            && cpuAddr[12] && cpuAddr[11]       // VIA ORA
+            && cpuAddr[10] && cpuAddr[9]
+    ) cpuVIAReq <= 1;
+    else cpuVIAReq <= 0;*/
+    // Mac ROM addresses Data Register A as vBase+vBufA:
+    // $EF,E1FE + (512*15) = $EF,FFFE
+    // shift right by one because no A0 and we get $77,FFFF
+    // This bit is giving me hell, so let's expand it
+    if(ncpuAS==0 && cpuRnW==0 && ncpuUDS==0
+            && cpuAddr == 22'h77FFFF) cpuVIAReq <= 1;
     else cpuVIAReq <= 0;
 end
 
@@ -376,20 +319,18 @@ always @(posedge pixClk or posedge ncpuAS) begin
             cpuLWriteSrv <= 0;
             cpuVIASrv    <= 0;
         end else begin
-            if(cpuUWriteReq && pState == P4) cpuUWriteSrv <= 1;
-            if(cpuLWriteReq && pState == P6) cpuLWriteSrv <= 1;
-            if(cpuVIAReq    && pState == P8) cpuVIASrv    <= 1;
+            if(cpuUWriteReq && pState == S3) cpuUWriteSrv <= 1;
+            if(cpuLWriteReq && pState == S5) cpuLWriteSrv <= 1;
+            if(cpuVIAReq    && pState == S7) cpuVIASrv    <= 1;
         end
     end
 end
 
-// when servicing a CPU VIA request, read the CPU data bus to set the video
-// buffer selection bit. Main: 1, Alt: 0
-/*always @(posedge pixClk or negedge nReset) begin
-    if(!nReset) vidBufSel <= 1;
-    else if(pState == P8) begin
-        vidBufSel <= ~cpuData[14];
-    end
-end*/
+// store the video buffer selection bit
+always @(posedge pixClk or negedge nReset) begin
+    if(!nReset) vidBufSel <= 0;
+    // fine. no video buffer select. we use Main only.
+    //else if(pState == S7) vidBufSel <= ~cpuData[14];
+end
 
 endmodule
\ No newline at end of file

From 4be7d63105fed83ae5a8b1d6d3e184f49736b6af Mon Sep 17 00:00:00 2001
From: techav <76832805+techav-homebrew@users.noreply.github.com>
Date: Tue, 12 Oct 2021 23:28:59 -0500
Subject: [PATCH 10/14] Fixed image overwrite issues

---
 se-xga.sv | 21 +++++++++++++--------
 1 file changed, 13 insertions(+), 8 deletions(-)

diff --git a/se-xga.sv b/se-xga.sv
index 9d66adf..8d57bef 100644
--- a/se-xga.sv
+++ b/se-xga.sv
@@ -52,7 +52,8 @@ end
 
 // horizontal and vertical sync signals
 always_comb begin
-    if(hCount >= 11'd1048 && hCount < 11'd1184) nhSyncInner <= 0;
+    //if(hCount >= 11'd1048 && hCount < 11'd1184) nhSyncInner <= 0;
+    if(hCount >= 11'd1052 && hCount < 11'd1187) nhSyncInner <= 0;
     else nhSyncInner <= 1;
     nhSync <= nhSyncInner;
 
@@ -72,7 +73,7 @@ wire hLoad;                 // load pixel data from vram when asserted
 assign vidActive = hActive & vActive;
 
 always_comb begin
-    if(hCount >= 0 && hCount < 1024) hActive <= 1;
+    if(hCount >= 3 && hCount < 1027) hActive <= 1;
     else hActive <= 0;
 
     if(vCount >= 0 && vCount < 684) vActive <= 1;
@@ -181,12 +182,12 @@ always_comb begin
         end
         S3, S4: begin
             // address bus for upper write cycles
-            vramAddr[14:1] <= cpuAddr[14:1] - 14'h1380;
+            vramAddr[14:1] <= cpuAddrShift;
             vramAddr[0] <= 0;
         end
         S5, S6: begin
             // address bus for lower write cycles
-            vramAddr[14:1] <= cpuAddr[14:1] - 14'h1380;
+            vramAddr[14:1] <= cpuAddrShift;
             vramAddr[0] <= 1;
         end
         default: begin
@@ -210,8 +211,6 @@ end
  * signals and see the strapped pattern output on screen.
  *****************************************************************************/
 logic [8:0] vidData;        // the video data we are displaying
-//wire  [2:0] vidSeq;         // sequence counter, derived from hCount
-//wire tick, tock;            // even/odd pulses of pixel clock divided by 2
 
 // output shift register
 always @(posedge pixClk) begin
@@ -221,7 +220,7 @@ always @(posedge pixClk) begin
     end else if(!hCount[0] && vidActive) begin
         // shift out video data
         vidData[8:1] <= vidData[7:0];
-        vidData[0] <= 0;
+        vidData[0] <= 1;
     end
 end
 
@@ -263,9 +262,15 @@ reg  cpuUWriteSrv, cpuLWriteSrv, cpuVIASrv;
 wire cpuBufSel;
 wire cpuBufAddr;
 reg vidBufSel;
+wire [13:0] cpuAddrShift = cpuAddr[14:1] - 14'h1380;
+wire cpuBufRange;
 
 // these are some helpful signals that shortcut the CPU buffer & VIA addresses
 always_comb begin
+    /*if(cpuAddr[14:1] >= 14'h1380
+        && cpuAddr[14:1] < 14'h3E40) cpuBufRange <= 1;
+    else cpuBufRange <= 0;*/
+    cpuBufRange <= (cpuAddr[14:1] >= 14'h1380) & (cpuAddr[14:1] < 14'h3E40);
     if(!ncpuAS && !cpuRnW
             && !cpuAddr[23] && !cpuAddr[22]     // first two bits always 0
             && !(cpuAddr[21] ^ ramSize[2])      // compare with RAM Size bits
@@ -273,7 +278,7 @@ always_comb begin
             && !(cpuAddr[19] ^ ramSize[0])
             && cpuAddr[18] && cpuAddr[17]       // next three bits always 1
             && cpuAddr[16]                      // skip 15, it selects buffers
-            && (cpuAddr[14] || cpuAddr[13])     // if neither 13|14 then not buffer
+            && cpuBufRange                      // only select buffer addresses
     ) begin
         cpuBufAddr <= 1;
     end else begin

From 7e2413150f5b54d56a57fb76c16c833a50775ff3 Mon Sep 17 00:00:00 2001
From: techav <76832805+techav-homebrew@users.noreply.github.com>
Date: Sun, 17 Oct 2021 01:24:22 -0500
Subject: [PATCH 11/14] Cleanup

---
 cpusnoop.sv => old/cpusnoop.sv | 0
 1 file changed, 0 insertions(+), 0 deletions(-)
 rename cpusnoop.sv => old/cpusnoop.sv (100%)

diff --git a/cpusnoop.sv b/old/cpusnoop.sv
similarity index 100%
rename from cpusnoop.sv
rename to old/cpusnoop.sv

From 3c12b07c7036bc51af010689e368874679cebaa8 Mon Sep 17 00:00:00 2001
From: techav-homebrew <76832805+techav-homebrew@users.noreply.github.com>
Date: Sun, 17 Oct 2021 01:25:27 -0500
Subject: [PATCH 12/14] Another fresh start

---
 rev3.sv | 230 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 230 insertions(+)
 create mode 100644 rev3.sv

diff --git a/rev3.sv b/rev3.sv
new file mode 100644
index 0000000..1d7e836
--- /dev/null
+++ b/rev3.sv
@@ -0,0 +1,230 @@
+/******************************************************************************
+ * SE-VGA
+ * Top-level module 
+ * techav
+ * 2021-10-16
+ ******************************************************************************
+ * Trying again again again
+ *****************************************************************************/
+
+module sevga (
+    input wire              nReset,     // System reset signal
+    input wire              pixClk,     // 65MHz pixel clock
+    output reg              nhSync,     // HSync signal
+    output reg              nvSync,     // VSync signal
+    output reg              vidOut,     // 1-bit Monochrome video signal
+
+    output logic [14:0]     vramAddr,   // VRAM Address bus
+    inout logic [7:0]       vramData,   // VRAM Data bus
+    output reg              nvramOE,    // VRAM Read strobe
+    output reg              nvramWE,    // VRAM Write strobe
+    output reg              nvramCE0,   // VRAM Main chip select signal
+    output reg              nvramCE1,   // VRAM Alt chip select signal
+
+    input wire [23:1]       cpuAddr,    // CPU Address bus
+    input wire [15:0]       cpuData,    // CPU Data bus
+    input wire              ncpuAS,     // CPU Address Strobe signal
+    input wire              ncpuUDS,    // CPU Upper Data Strobe signal
+    input wire              ncpuLDS,    // CPU Lower Data Strobe signal
+    input wire              cpuRnW,     // CPU Read/Write select signal
+    input logic [2:0]       ramSize     // Select installed RAM size
+);
+
+/******************************************************************************
+ * Initial Video Signal Timing
+ * The following functions establish the basic XGA signal timing and 
+ * assert the horizontal and vertical sync signals as appropriate.
+ * These functions are the minimum required for a signal presence detect test.
+ *****************************************************************************/
+
+// Primary sync counters
+logic [10:0] hCount;    // 0..1343
+logic [9:0] vCount;     // 0..805
+always @(negedge pixClk) begin
+    if(hCount < 1343) hCount <= hCount + 1;
+    else begin
+        hCount <= 0;
+        if(vCount <= 805) vCount <= vCount + 1;
+        else vCount <= 0;
+    end
+end
+
+// Horizontal sync
+always @(negedge pixClk) begin
+    if(hCount == 0) nhSyncR <= 1;
+    else if(hCount == 1052) nhSync <= 0;
+    else if(hCount == 1186) nhSync <= 1;
+end
+
+// Vertical sync
+always @(negedge pixClk) begin
+    if(vCount == 0) nvSync <= 1;
+    else if(vCount == 729) nvSync <= 0;
+    else if(vCount == 734) nvSync <= 0;
+end
+
+/******************************************************************************
+ * Useful signals
+ * Here we break out a few useful signals, derived from the timing above, that
+ * will help us elsewhere.
+ *****************************************************************************/
+
+// Horizontal active
+reg hActive;
+always @(negedge pixClk) begin
+    if(hCount == 0) hActive <= 1;
+    else if(hCount == 1023) hActive <= 0;
+    else if(hCount == 1343) hActive <= 1;
+end
+
+// Vertical active
+reg vActive;
+always @(negedge pixClk) begin
+    if(vCount == 0) vActive <= 1;
+    else if(vCount == 683) vActive <= 0;
+    else if(vCount == 805) vActive <= 1;
+end
+
+// Horizontal fetch active
+// asserted just before active video to enable video data pre-fetch
+reg fhActive;
+always @(negedge pixClk) begin
+    if(hCount == 0) fhActive <= 1;
+    else if(hCount == 1022) fhActive <= 0;
+    else if(hCount == 1342) fhActive <= 1;
+end
+
+// Vertical fetch active
+// 
+reg fvActive;
+always @(negedge pixClk) begin
+    if(vCount == 0) fvActive <= 1;
+    else if(vCount == 684) fvActive <= 0;
+    if(vCount == 805) fvActive <= 1; 
+end
+
+// combined active signals
+wire vidActive = hActive & vActive;
+wire fetchActive = fhActive & fvActive;
+
+/******************************************************************************
+ * VRAM State Machine
+ * Coordinates VRAM load/store actions
+ *****************************************************************************/
+
+// rising edge signals: nvramWE, nvramOE, nvramCE[1:0]
+// falling edge signals: vramAddr, vramData
+
+// VRAM read signal
+always @(posedge pixClk) begin nvramOE <= ~(hCount == 7); end
+
+// VRAM write signal
+always @(posedge pixClk) begin
+    if(hCount[3:1] == 0) nvramWEr <= 1;
+    else if(hCount[3:1] == 1) nvramWE <= 0;
+    else if(hCount[3:1] == 6) nvramWE <= 1;
+end
+
+// VRAM data/address busses
+always @(negedge pixClk) begin
+    if(hCount[0] && !hCount[1]) begin
+        case(hCount[3:2])
+            3: begin
+                // start read cycle
+                vramData <= 8'hZ;
+                vramAddr[14:6] <= vCount[9:1];
+                vramAddr[5:0] <= hCount[9:4];
+            end
+            default: begin
+                // write slots
+                vramAddr[14:1] <= cpuAddr[14:1] - 14'h1380;
+                if(!ncpuUDSr && !cpuLDSsrv) begin
+                    vramAddr[0] <= 0;
+                    //cpuLDSsrv <= 1;
+                    vramData <= cpuData[15:8];
+                end else if(!ncpuLDSr && !cpuLDSsrv) begin
+                    vramAddr[0] <= 1;
+                    //cpuLDSsrv <= 1;
+                    vramData <= cpuData[7:0];
+                end
+            end
+        endcase
+    end
+end
+
+// VRAM chip enable signals
+always @(posedge pixClk) begin
+    if(!hCount[0]) begin
+        if(hCount[3:1] == 7) begin
+            // read cycle
+            if(fetchActive) begin
+                nvramCE0 <= ~vidBufSel;
+                nvramCE1 <= vidBufSel;
+            end else begin
+                nvramCE0 <= 1;
+                nvramCE1 <= 1;
+            end
+        end else if(hCount[1]) begin
+            // write cycle
+            if(!ncpuUDSr && !cpuUDSsrv) begin
+                nvramCE0 <= ~vramAddr[15];
+                nvramCE1 <= vramAddr[15];
+                cpuUDSsrv <= 1;
+            end else if(!ncpuLDSr && !cpuLDSsrv) begin
+                nvramCE0 <= ~vramAddr[15];
+                nvramCE1 <= vramAddr[15];
+                cpuLDSsrv <= 1;
+            end else begin
+                nvramCE0 <= 1;
+                nvramCE1 <= 1;
+            end
+        end
+    end else begin
+        nvramCE0 <= 1;
+        nvramCE1 <= 1;
+    end
+    // reset the upper/lower serve signals when cycle ended by CPU
+    if(ncpuLDS) cpuLDSsrv <= 0;
+    if(ncpuUDS) cpuUDSsrv <= 0;
+end
+
+// Video data shift register & output
+reg [7:0] vidShiftr;
+always @(negedge pixClk) begin
+    if(hCount[3:0] == 4'hF) vidShiftr <= ~vramData;
+    else if(hCount[0]) begin
+        vidShiftr[7:1] <= vidShiftr[6:0];
+        vidShiftr[0] <= 0;
+    end
+end
+always_comb begin
+    if(vidActive) vidOut = vidShiftr[7];
+    else vidOut <= 0;
+end
+
+/******************************************************************************
+ * CPU Bus Snooping
+ * Watches the CPU bus and aligns its operations with the pixel clock
+ *****************************************************************************/
+reg ncpuUDSr, ncpuLDSr;
+always @(negedge pixClk) begin
+    // this condition evaluates true when cpu is writing to video buffer
+    if(!ncpuAS && !cpuRnW
+        && !cpuAddr[23] && !cpuAddr[22]
+        && !(cpuAddr[21] ^ ramSize[2])
+        && !(cpuAddr[20] ^ ramSize[1])
+        && !(cpuAddr[19] ^ ramSize[0])
+        && cpuAddr[18] && cpuAddr[17]
+        && cpuAddr[16]
+        && ((cpuAddr[14:1] >= 14'h1380)
+        && (cpuAddr[14:1] < 14'h3E40))) 
+    begin
+        if(!ncpuUDS) ncpuUDSr <= 0;
+        else ncpuUDSr <= 1;
+        if(!ncpuLDS) ncpuLDSr <= 0;
+        else ncpuLDSr <= 1;
+    end else begin
+        ncpuUDSr <= 1;
+        ncpuLDSr <= 1;
+    end
+end

From 1137244a39e6dc2299f1ae3b1a50694ebe19efd5 Mon Sep 17 00:00:00 2001
From: techav <76832805+techav-homebrew@users.noreply.github.com>
Date: Sun, 17 Oct 2021 03:41:04 -0500
Subject: [PATCH 13/14] Rewrite again

---
 old/se-xga.sv | 342 +++++++++++++++++++++++++++++++++++++++++
 rev3.sv       | 230 ---------------------------
 se-xga.sv     | 418 ++++++++++++++++++--------------------------------
 3 files changed, 495 insertions(+), 495 deletions(-)
 create mode 100644 old/se-xga.sv
 delete mode 100644 rev3.sv

diff --git a/old/se-xga.sv b/old/se-xga.sv
new file mode 100644
index 0000000..12c0e64
--- /dev/null
+++ b/old/se-xga.sv
@@ -0,0 +1,342 @@
+/******************************************************************************
+ * SE-VGA
+ * Top-level module 
+ * techav
+ * 2021-10-12
+ ******************************************************************************
+ * This is ... mostly working. It has some write glitches and a vertical line
+ * five pixels from the left side of the screen.
+ *****************************************************************************/
+
+module sevga (
+    input wire              nReset,     // System reset signal
+    input wire              pixClk,     // 65MHz pixel clock
+    output wire             nhSync,     // HSync signal
+    output wire             nvSync,     // VSync signal
+    output wire             vidOut,     // 1-bit Monochrome video signal
+
+    output logic [14:0]     vramAddr,   // VRAM Address bus
+    inout logic [7:0]       vramData,   // VRAM Data bus
+    output wire             nvramOE,    // VRAM Read strobe
+    output wire             nvramWE,    // VRAM Write strobe
+    output wire             nvramCE0,   // VRAM Main chip select signal
+    output wire             nvramCE1,   // VRAM Alt chip select signal
+
+    input logic [23:1]      cpuAddr,    // CPU Address bus
+    input logic [15:0]      cpuData,    // CPU Data bus
+    input wire              ncpuAS,     // CPU Address Strobe signal
+    input wire              ncpuUDS,    // CPU Upper Data Strobe signal
+    input wire              ncpuLDS,    // CPU Lower Data Strobe signal
+    input wire              cpuRnW,     // CPU Read/Write select signal
+    input logic [2:0]       ramSize     // Select installed RAM size
+);
+
+/******************************************************************************
+ * Initial Video Signal Timing
+ * The following four functions establish the basic XGA signal timing and 
+ * assert the horizontal and vertical sync signals as appropriate.
+ * These functions are the minimum required for a signal presence detect test.
+ *****************************************************************************/
+logic [10:0] hCount;    // 0..1343
+logic [9:0] vCount;     // 0..805
+wire nhSyncInner;
+
+// Primary video sync counters -- Now more synchronous!
+always @(negedge pixClk) begin
+    if(hCount < 11'd1343) hCount <= hCount + 11'd1;
+    else begin
+        hCount <= 11'd0;
+        if(vCount < 10'd805) vCount <= vCount + 10'd1;
+        else vCount <= 10'd0;
+    end
+end
+
+// horizontal and vertical sync signals
+always_comb begin
+    //if(hCount >= 11'd1048 && hCount < 11'd1184) nhSyncInner <= 0;
+    if(hCount >= 11'd1052 && hCount < 11'd1187) nhSyncInner <= 0;
+    else nhSyncInner <= 1;
+    nhSync <= nhSyncInner;
+
+    if(vCount >= 10'd729 && vCount < 10'd735) nvSync <= 0;
+    else nvSync <= 1;
+end
+
+/******************************************************************************
+ * Useful signals
+ * Here we break out a few useful signals, derived from the timing above, that
+ * will help us elsewhere.
+ *****************************************************************************/
+wire hActive, vActive;      // active video signals. vidout black when negated
+wire vidActive;             // active when both hActive and vActive asserted
+wire hLoad;                 // load pixel data from vram when asserted
+
+assign vidActive = hActive & vActive;
+
+always_comb begin
+    if(hCount >= 3 && hCount < 1027) hActive <= 1;
+    else hActive <= 0;
+
+    if(vCount >= 0 && vCount < 684) vActive <= 1;
+    else vActive <= 0;
+
+    if(hCount >= 0 && hCount < 1024 && vActive) hLoad <= 1;
+    else hLoad <= 0;
+end
+
+/******************************************************************************
+ * Primary State Machine
+ * This is the primary state machine which runs the entire system, handling
+ * VRAM reads, VRAM writes, VIA writes, and idle states
+ *****************************************************************************/
+
+// used to align primary state machine with horizontal counter
+wire [3:0] vSeq = hCount[3:0];
+
+// define state machine states (Gray code)
+parameter
+    S0  =   4'b0000,    // VRAM Read 0
+    S1  =   4'b0001,    // VRAM Read 1
+    S2  =   4'b0011,    // Idle
+    S3  =   4'b0010,    // VRAM Write Upper 0
+    S4  =   4'b0110,    // VRAM Write Upper 1
+    S5  =   4'b0111,    // VRAM Write Lower 0
+    S6  =   4'b0101,    // VRAM Write Lower 1
+    S7  =   4'b0100,    // VIA Write
+    S8  =   4'b1100,    // VSync (to be added later)
+    S9  =   4'b1101,    // undefined
+    S10 =   4'b1111,    // undefined
+    S11 =   4'b1110,    // undefined
+    S12 =   4'b1010,    // undefined
+    S13 =   4'b1011,    // undefined
+    S14 =   4'b1001,    // undefined
+    S15 =   4'b1000;    // undefined
+
+logic [3:0] pState;
+
+// And here is the much simplified primary state machine
+always @(negedge pixClk or negedge nReset) begin
+    if(!nReset) pState <= S2;   // resync on reset by jumping to idle state
+    else begin
+        case(pState)
+            S0: pState <= S1;   // first VRAM read state, always move to S1
+            S3: pState <= S4;   // first UDS write state, always move to S4
+            S5: pState <= S6;   // first LDS write state, always move to S6
+            /*S7: begin
+                
+                pState <= S2;
+            end*/
+            S2: begin
+                // here is where everything actually happens.
+                if(vSeq == 4'hF) pState <= S0;   // time for a read state
+                else if(cpuUWriteReq && !cpuUWriteSrv && vSeq < 4'hD) pState <= S3;
+                else if(cpuLWriteReq && !cpuLWriteSrv && vSeq < 4'hD) pState <= S5;
+                else if(cpuVIAReq    && !cpuVIASrv    && vSeq < 4'hE) pState <= S7;
+                else pState <= S2;
+            end
+            default: pState <= S2; // everyone ends up at S2 (idle)
+        endcase
+    end
+end
+
+// primary VRAM signal combination, based on the primary state machine
+always_comb begin
+    // VRAM Read Strobe
+    if((pState == S0 || pState == S1) && hLoad) nvramOE <= 0;
+    else nvramOE <= 1;
+
+    // VRAM Write Strobe
+    if(pState == S3 || pState == S5) nvramWE <= 0;
+    else nvramWE <= 1;
+    
+    // VRAM Chip Enable Signals
+    case(pState)
+        S0, S1: begin
+            if(hLoad) begin
+                nvramCE0 <= ~vidBufSel;
+                nvramCE1 <= vidBufSel;
+            end else begin
+                nvramCE0 <= 1;
+                nvramCE1 <= 1;
+            end
+        end
+        S3, S4, S5, S6: begin
+            nvramCE0 <= ~cpuBufSel;
+            nvramCE1 <= cpuBufSel;
+        end
+        default: begin
+            nvramCE0 <= 1;
+            nvramCE1 <= 1;
+        end
+    endcase
+
+    // VRAM Address Bus
+    case(pState)
+        S0, S1: begin
+            // address bus for read cycles
+            if(hLoad) begin
+                vramAddr[14:6] <= vCount[9:1];
+                vramAddr[5:0] <= hCount[9:4];
+            end else begin
+                vramAddr <= 0;
+            end
+        end
+        S3, S4: begin
+            // address bus for upper write cycles
+            vramAddr[14:1] <= cpuAddrShift;
+            vramAddr[0] <= 0;
+        end
+        S5, S6: begin
+            // address bus for lower write cycles
+            vramAddr[14:1] <= cpuAddrShift;
+            vramAddr[0] <= 1;
+        end
+        default: begin
+            // address bus for idle cycles
+            vramAddr <= 0;
+        end
+    endcase
+
+    // VRAM Data bus
+    case(pState)
+        S3, S4 : vramData <= cpuData[15:8];
+        S5, S6 : vramData <= cpuData[7:0];
+        default: vramData <= 8'hZ;
+    endcase
+end
+
+/******************************************************************************
+ * Video Output Sequencing
+ * Here is the primary video output shift register sequencing.
+ * With these functions in place, it should be possible to strap the VRAM data
+ * signals and see the strapped pattern output on screen.
+ *****************************************************************************/
+logic [8:0] vidData;        // the video data we are displaying
+
+// output shift register
+always @(posedge pixClk) begin
+    if(pState == S1 && hLoad) begin
+        // store VRAM data in shift register
+        vidData[7:0] <= vramData;
+    end else if(!hCount[0] && vidActive) begin
+        // shift out video data
+        vidData[8:1] <= vidData[7:0];
+        vidData[0] <= 1;
+    end
+end
+
+// final video output
+always_comb begin
+    if(vidActive) vidOut <= ~vidData[8];
+    else vidOut <= 0;
+end
+
+/******************************************************************************
+ * CPU Bus Snooping
+ * Watch the CPU bus for writes to the video buffer regions of memory and write
+ * that data to VRAM. VRAM write cycles can occur during vidSeq 1 through 7.
+ * High-order bytes are passed to VRAM on tick states and low-order bytes are 
+ * passed to VRAM on tock states. After the VRAM writes are complete, state
+ * machine waits for the CPU cycle to end before returning to idle.
+ *****************************************************************************/
+
+/* Main framebuffer starts $5900 below the top of RAM, alt frame buffer is
+ * $8000 below the main frame buffer
+ * ramSize is used to mask the CPU Address bits [21:19] to select the amount
+ * of memory installed in the computer. Not all possible ramSize selections
+ * are valid memory sizes when using 30-pin SIMMs in the Mac SE. 
+ * They may be possible using PDS RAM expansion cards.
+ * ramSize mainBuffer altBuffer ramTop+1 ramSize Valid?      Installed SIMMs
+ *    $7    $3fa700    $3f2700   $400000  4.0MB    Y    [ 1MB   1MB ][ 1MB   1MB ]
+ *    $6    $37a700    $372700   $380000  3.5MB    N
+ *    $5    $2fa700    $2f2700   $300000  3.0MB    N
+ *    $4    $27a700    $272700   $280000  2.5MB    Y    [ 1MB   1MB ][256kB 256kB]
+ *    $3    $1fa700    $1f2700   $200000  2.0MB    Y    [ 1MB   1MB ][ ---   --- ]
+ *    $2    $17a700    $172700   $180000  1.5MB    N  
+ *    $1    $0fa700    $0f2700   $100000  1.0MB    Y    [256kB 256kB][256kB 256kB]
+ *    $0    $07a700    $072700   $080000  0.5MB    Y    [256kB 256kB][ ---   --- ]
+ */
+
+// keep track of pending CPU write requests and whether they have been serviced
+wire cpuUWriteReq, cpuLWriteReq, cpuVIAReq;
+reg  cpuUWriteSrv, cpuLWriteSrv, cpuVIASrv;
+wire cpuBufSel;
+wire cpuBufAddr;
+reg vidBufSel;
+wire [13:0] cpuAddrShift = cpuAddr[14:1] - 14'h1380;
+wire cpuBufRange;
+
+// these are some helpful signals that shortcut the CPU buffer & VIA addresses
+always_comb begin
+    /*if(cpuAddr[14:1] >= 14'h1380
+        && cpuAddr[14:1] < 14'h3E40) cpuBufRange <= 1;
+    else cpuBufRange <= 0;*/
+    cpuBufRange <= (cpuAddr[14:1] >= 14'h1380) & (cpuAddr[14:1] < 14'h3E40);
+    if(!ncpuAS && !cpuRnW
+            && !cpuAddr[23] && !cpuAddr[22]     // first two bits always 0
+            && !(cpuAddr[21] ^ ramSize[2])      // compare with RAM Size bits
+            && !(cpuAddr[20] ^ ramSize[1])
+            && !(cpuAddr[19] ^ ramSize[0])
+            && cpuAddr[18] && cpuAddr[17]       // next three bits always 1
+            && cpuAddr[16]                      // skip 15, it selects buffers
+            && cpuBufRange                      // only select buffer addresses
+    ) begin
+        cpuBufAddr <= 1;
+    end else begin
+        cpuBufAddr <= 0;
+    end
+    cpuBufSel <= ~cpuAddr[15];                   // address bit 15 selects buffer
+
+    if(cpuBufAddr && !ncpuUDS) cpuUWriteReq <= 1;
+    else cpuUWriteReq <= 0;
+    if(cpuBufAddr && !ncpuLDS) cpuLWriteReq <= 1;
+    else cpuLWriteReq <= 0;
+
+    // VIA is in address block $E8,0000 - $EF,FFFF
+    // VIA register select pins (RS[3:0]) are wired to cpuAddr[12:9]
+    // VIA Output Register A is selected when RS[3:0]==$F
+    /*if(!ncpuAS && !cpuRnW && !ncpuUDS
+            && cpuAddr[23] && cpuAddr[22]       // VIA Address Select
+            && cpuAddr[21] && !cpuAddr[20]
+            && cpuAddr[19]
+            && cpuAddr[12] && cpuAddr[11]       // VIA ORA
+            && cpuAddr[10] && cpuAddr[9]
+    ) cpuVIAReq <= 1;
+    else cpuVIAReq <= 0;*/
+    // Mac ROM addresses Data Register A as vBase+vBufA:
+    // $EF,E1FE + (512*15) = $EF,FFFE
+    // shift right by one because no A0 and we get $77,FFFF
+    // This bit is giving me hell, so let's expand it
+    if(ncpuAS==0 && cpuRnW==0 && ncpuUDS==0
+            && cpuAddr == 22'h77FFFF) cpuVIAReq <= 1;
+    else cpuVIAReq <= 0;
+end
+
+// if there's an active CPU request and we've reached the state for servicing
+// that CPU request, then set a flag to mark that we have serviced it
+always @(posedge pixClk or posedge ncpuAS) begin
+    if(ncpuAS) begin
+        cpuUWriteSrv <= 0;
+        cpuLWriteSrv <= 0;
+        cpuVIASrv    <= 0;
+    end else begin
+        if(ncpuAS) begin
+            cpuUWriteSrv <= 0;
+            cpuLWriteSrv <= 0;
+            cpuVIASrv    <= 0;
+        end else begin
+            if(cpuUWriteReq && pState == S3) cpuUWriteSrv <= 1;
+            if(cpuLWriteReq && pState == S5) cpuLWriteSrv <= 1;
+            if(cpuVIAReq    && pState == S7) cpuVIASrv    <= 1;
+        end
+    end
+end
+
+// store the video buffer selection bit
+always @(posedge pixClk or negedge nReset) begin
+    if(!nReset) vidBufSel <= 0;
+    // fine. no video buffer select. we use Main only.
+    //else if(pState == S7) vidBufSel <= ~cpuData[14];
+end
+
+endmodule
\ No newline at end of file
diff --git a/rev3.sv b/rev3.sv
deleted file mode 100644
index 1d7e836..0000000
--- a/rev3.sv
+++ /dev/null
@@ -1,230 +0,0 @@
-/******************************************************************************
- * SE-VGA
- * Top-level module 
- * techav
- * 2021-10-16
- ******************************************************************************
- * Trying again again again
- *****************************************************************************/
-
-module sevga (
-    input wire              nReset,     // System reset signal
-    input wire              pixClk,     // 65MHz pixel clock
-    output reg              nhSync,     // HSync signal
-    output reg              nvSync,     // VSync signal
-    output reg              vidOut,     // 1-bit Monochrome video signal
-
-    output logic [14:0]     vramAddr,   // VRAM Address bus
-    inout logic [7:0]       vramData,   // VRAM Data bus
-    output reg              nvramOE,    // VRAM Read strobe
-    output reg              nvramWE,    // VRAM Write strobe
-    output reg              nvramCE0,   // VRAM Main chip select signal
-    output reg              nvramCE1,   // VRAM Alt chip select signal
-
-    input wire [23:1]       cpuAddr,    // CPU Address bus
-    input wire [15:0]       cpuData,    // CPU Data bus
-    input wire              ncpuAS,     // CPU Address Strobe signal
-    input wire              ncpuUDS,    // CPU Upper Data Strobe signal
-    input wire              ncpuLDS,    // CPU Lower Data Strobe signal
-    input wire              cpuRnW,     // CPU Read/Write select signal
-    input logic [2:0]       ramSize     // Select installed RAM size
-);
-
-/******************************************************************************
- * Initial Video Signal Timing
- * The following functions establish the basic XGA signal timing and 
- * assert the horizontal and vertical sync signals as appropriate.
- * These functions are the minimum required for a signal presence detect test.
- *****************************************************************************/
-
-// Primary sync counters
-logic [10:0] hCount;    // 0..1343
-logic [9:0] vCount;     // 0..805
-always @(negedge pixClk) begin
-    if(hCount < 1343) hCount <= hCount + 1;
-    else begin
-        hCount <= 0;
-        if(vCount <= 805) vCount <= vCount + 1;
-        else vCount <= 0;
-    end
-end
-
-// Horizontal sync
-always @(negedge pixClk) begin
-    if(hCount == 0) nhSyncR <= 1;
-    else if(hCount == 1052) nhSync <= 0;
-    else if(hCount == 1186) nhSync <= 1;
-end
-
-// Vertical sync
-always @(negedge pixClk) begin
-    if(vCount == 0) nvSync <= 1;
-    else if(vCount == 729) nvSync <= 0;
-    else if(vCount == 734) nvSync <= 0;
-end
-
-/******************************************************************************
- * Useful signals
- * Here we break out a few useful signals, derived from the timing above, that
- * will help us elsewhere.
- *****************************************************************************/
-
-// Horizontal active
-reg hActive;
-always @(negedge pixClk) begin
-    if(hCount == 0) hActive <= 1;
-    else if(hCount == 1023) hActive <= 0;
-    else if(hCount == 1343) hActive <= 1;
-end
-
-// Vertical active
-reg vActive;
-always @(negedge pixClk) begin
-    if(vCount == 0) vActive <= 1;
-    else if(vCount == 683) vActive <= 0;
-    else if(vCount == 805) vActive <= 1;
-end
-
-// Horizontal fetch active
-// asserted just before active video to enable video data pre-fetch
-reg fhActive;
-always @(negedge pixClk) begin
-    if(hCount == 0) fhActive <= 1;
-    else if(hCount == 1022) fhActive <= 0;
-    else if(hCount == 1342) fhActive <= 1;
-end
-
-// Vertical fetch active
-// 
-reg fvActive;
-always @(negedge pixClk) begin
-    if(vCount == 0) fvActive <= 1;
-    else if(vCount == 684) fvActive <= 0;
-    if(vCount == 805) fvActive <= 1; 
-end
-
-// combined active signals
-wire vidActive = hActive & vActive;
-wire fetchActive = fhActive & fvActive;
-
-/******************************************************************************
- * VRAM State Machine
- * Coordinates VRAM load/store actions
- *****************************************************************************/
-
-// rising edge signals: nvramWE, nvramOE, nvramCE[1:0]
-// falling edge signals: vramAddr, vramData
-
-// VRAM read signal
-always @(posedge pixClk) begin nvramOE <= ~(hCount == 7); end
-
-// VRAM write signal
-always @(posedge pixClk) begin
-    if(hCount[3:1] == 0) nvramWEr <= 1;
-    else if(hCount[3:1] == 1) nvramWE <= 0;
-    else if(hCount[3:1] == 6) nvramWE <= 1;
-end
-
-// VRAM data/address busses
-always @(negedge pixClk) begin
-    if(hCount[0] && !hCount[1]) begin
-        case(hCount[3:2])
-            3: begin
-                // start read cycle
-                vramData <= 8'hZ;
-                vramAddr[14:6] <= vCount[9:1];
-                vramAddr[5:0] <= hCount[9:4];
-            end
-            default: begin
-                // write slots
-                vramAddr[14:1] <= cpuAddr[14:1] - 14'h1380;
-                if(!ncpuUDSr && !cpuLDSsrv) begin
-                    vramAddr[0] <= 0;
-                    //cpuLDSsrv <= 1;
-                    vramData <= cpuData[15:8];
-                end else if(!ncpuLDSr && !cpuLDSsrv) begin
-                    vramAddr[0] <= 1;
-                    //cpuLDSsrv <= 1;
-                    vramData <= cpuData[7:0];
-                end
-            end
-        endcase
-    end
-end
-
-// VRAM chip enable signals
-always @(posedge pixClk) begin
-    if(!hCount[0]) begin
-        if(hCount[3:1] == 7) begin
-            // read cycle
-            if(fetchActive) begin
-                nvramCE0 <= ~vidBufSel;
-                nvramCE1 <= vidBufSel;
-            end else begin
-                nvramCE0 <= 1;
-                nvramCE1 <= 1;
-            end
-        end else if(hCount[1]) begin
-            // write cycle
-            if(!ncpuUDSr && !cpuUDSsrv) begin
-                nvramCE0 <= ~vramAddr[15];
-                nvramCE1 <= vramAddr[15];
-                cpuUDSsrv <= 1;
-            end else if(!ncpuLDSr && !cpuLDSsrv) begin
-                nvramCE0 <= ~vramAddr[15];
-                nvramCE1 <= vramAddr[15];
-                cpuLDSsrv <= 1;
-            end else begin
-                nvramCE0 <= 1;
-                nvramCE1 <= 1;
-            end
-        end
-    end else begin
-        nvramCE0 <= 1;
-        nvramCE1 <= 1;
-    end
-    // reset the upper/lower serve signals when cycle ended by CPU
-    if(ncpuLDS) cpuLDSsrv <= 0;
-    if(ncpuUDS) cpuUDSsrv <= 0;
-end
-
-// Video data shift register & output
-reg [7:0] vidShiftr;
-always @(negedge pixClk) begin
-    if(hCount[3:0] == 4'hF) vidShiftr <= ~vramData;
-    else if(hCount[0]) begin
-        vidShiftr[7:1] <= vidShiftr[6:0];
-        vidShiftr[0] <= 0;
-    end
-end
-always_comb begin
-    if(vidActive) vidOut = vidShiftr[7];
-    else vidOut <= 0;
-end
-
-/******************************************************************************
- * CPU Bus Snooping
- * Watches the CPU bus and aligns its operations with the pixel clock
- *****************************************************************************/
-reg ncpuUDSr, ncpuLDSr;
-always @(negedge pixClk) begin
-    // this condition evaluates true when cpu is writing to video buffer
-    if(!ncpuAS && !cpuRnW
-        && !cpuAddr[23] && !cpuAddr[22]
-        && !(cpuAddr[21] ^ ramSize[2])
-        && !(cpuAddr[20] ^ ramSize[1])
-        && !(cpuAddr[19] ^ ramSize[0])
-        && cpuAddr[18] && cpuAddr[17]
-        && cpuAddr[16]
-        && ((cpuAddr[14:1] >= 14'h1380)
-        && (cpuAddr[14:1] < 14'h3E40))) 
-    begin
-        if(!ncpuUDS) ncpuUDSr <= 0;
-        else ncpuUDSr <= 1;
-        if(!ncpuLDS) ncpuLDSr <= 0;
-        else ncpuLDSr <= 1;
-    end else begin
-        ncpuUDSr <= 1;
-        ncpuLDSr <= 1;
-    end
-end
diff --git a/se-xga.sv b/se-xga.sv
index 8d57bef..e5a4cd1 100644
--- a/se-xga.sv
+++ b/se-xga.sv
@@ -2,27 +2,27 @@
  * SE-VGA
  * Top-level module 
  * techav
- * 2021-08-04
+ * 2021-10-16
  ******************************************************************************
- * Pulls together all the smaller modules to form the SE-VGA adapter
+ * Trying again again again
  *****************************************************************************/
 
 module sevga (
     input wire              nReset,     // System reset signal
     input wire              pixClk,     // 65MHz pixel clock
-    output wire             nhSync,     // HSync signal
-    output wire             nvSync,     // VSync signal
-    output wire             vidOut,     // 1-bit Monochrome video signal
+    output reg              nhSync,     // HSync signal
+    output reg              nvSync,     // VSync signal
+    output reg              vidOut,     // 1-bit Monochrome video signal
 
     output logic [14:0]     vramAddr,   // VRAM Address bus
     inout logic [7:0]       vramData,   // VRAM Data bus
-    output wire             nvramOE,    // VRAM Read strobe
-    output wire             nvramWE,    // VRAM Write strobe
-    output wire             nvramCE0,   // VRAM Main chip select signal
-    output wire             nvramCE1,   // VRAM Alt chip select signal
+    output reg              nvramOE,    // VRAM Read strobe
+    output reg              nvramWE,    // VRAM Write strobe
+    output reg              nvramCE0,   // VRAM Main chip select signal
+    output reg              nvramCE1,   // VRAM Alt chip select signal
 
-    input logic [23:1]      cpuAddr,    // CPU Address bus
-    input logic [15:0]      cpuData,    // CPU Data bus
+    input wire [23:1]       cpuAddr,    // CPU Address bus
+    input wire [15:0]       cpuData,    // CPU Data bus
     input wire              ncpuAS,     // CPU Address Strobe signal
     input wire              ncpuUDS,    // CPU Upper Data Strobe signal
     input wire              ncpuLDS,    // CPU Lower Data Strobe signal
@@ -32,33 +32,35 @@ module sevga (
 
 /******************************************************************************
  * Initial Video Signal Timing
- * The following four functions establish the basic XGA signal timing and 
+ * The following functions establish the basic XGA signal timing and 
  * assert the horizontal and vertical sync signals as appropriate.
  * These functions are the minimum required for a signal presence detect test.
  *****************************************************************************/
+
+// Primary sync counters
 logic [10:0] hCount;    // 0..1343
 logic [9:0] vCount;     // 0..805
-wire nhSyncInner;
-
-// Primary video sync counters -- Now more synchronous!
 always @(negedge pixClk) begin
-    if(hCount < 11'd1343) hCount <= hCount + 11'd1;
+    if(hCount < 1343) hCount <= hCount + 11'h1;
     else begin
-        hCount <= 11'd0;
-        if(vCount < 10'd805) vCount <= vCount + 10'd1;
-        else vCount <= 10'd0;
+        hCount <= 0;
+        if(vCount <= 805) vCount <= vCount + 10'h1;
+        else vCount <= 0;
     end
 end
 
-// horizontal and vertical sync signals
-always_comb begin
-    //if(hCount >= 11'd1048 && hCount < 11'd1184) nhSyncInner <= 0;
-    if(hCount >= 11'd1052 && hCount < 11'd1187) nhSyncInner <= 0;
-    else nhSyncInner <= 1;
-    nhSync <= nhSyncInner;
+// Horizontal sync
+always @(negedge pixClk) begin
+    if(hCount == 0) nhSync <= 1;
+    else if(hCount == 1052) nhSync <= 0;
+    else if(hCount == 1186) nhSync <= 1;
+end
 
-    if(vCount >= 10'd729 && vCount < 10'd735) nvSync <= 0;
-    else nvSync <= 1;
+// Vertical sync
+always @(negedge pixClk) begin
+    if(vCount == 0) nvSync <= 1;
+    else if(vCount == 729) nvSync <= 0;
+    else if(vCount == 734) nvSync <= 0;
 end
 
 /******************************************************************************
@@ -66,276 +68,162 @@ end
  * Here we break out a few useful signals, derived from the timing above, that
  * will help us elsewhere.
  *****************************************************************************/
-wire hActive, vActive;      // active video signals. vidout black when negated
-wire vidActive;             // active when both hActive and vActive asserted
-wire hLoad;                 // load pixel data from vram when asserted
 
-assign vidActive = hActive & vActive;
-
-always_comb begin
-    if(hCount >= 3 && hCount < 1027) hActive <= 1;
-    else hActive <= 0;
-
-    if(vCount >= 0 && vCount < 684) vActive <= 1;
-    else vActive <= 0;
-
-    if(hCount >= 0 && hCount < 1024 && vActive) hLoad <= 1;
-    else hLoad <= 0;
+// Horizontal active
+reg hActive;
+always @(negedge pixClk) begin
+    if(hCount == 0) hActive <= 1;
+    else if(hCount == 1023) hActive <= 0;
+    else if(hCount == 1343) hActive <= 1;
 end
 
+// Vertical active
+reg vActive;
+always @(negedge pixClk) begin
+    if(vCount == 0) vActive <= 1;
+    else if(vCount == 683) vActive <= 0;
+    else if(vCount == 805) vActive <= 1;
+end
+
+// Horizontal fetch active
+// asserted just before active video to enable video data pre-fetch
+reg fhActive;
+always @(negedge pixClk) begin
+    if(hCount == 0) fhActive <= 1;
+    else if(hCount == 1022) fhActive <= 0;
+    else if(hCount == 1342) fhActive <= 1;
+end
+
+// Vertical fetch active
+// 
+reg fvActive;
+always @(negedge pixClk) begin
+    if(vCount == 0) fvActive <= 1;
+    else if(vCount == 684) fvActive <= 0;
+    if(vCount == 805) fvActive <= 1; 
+end
+
+// combined active signals
+wire vidActive = hActive & vActive;
+wire fetchActive = fhActive & fvActive;
+
 /******************************************************************************
- * Primary State Machine
- * This is the primary state machine which runs the entire system, handling
- * VRAM reads, VRAM writes, VIA writes, and idle states
+ * VRAM State Machine
+ * Coordinates VRAM load/store actions
  *****************************************************************************/
 
-// used to align primary state machine with horizontal counter
-wire [3:0] vSeq = hCount[3:0];
+// rising edge signals: nvramWE, nvramOE, nvramCE[1:0]
+// falling edge signals: vramAddr, vramData
 
-// define state machine states (Gray code)
-parameter
-    S0  =   4'b0000,    // VRAM Read 0
-    S1  =   4'b0001,    // VRAM Read 1
-    S2  =   4'b0011,    // Idle
-    S3  =   4'b0010,    // VRAM Write Upper 0
-    S4  =   4'b0110,    // VRAM Write Upper 1
-    S5  =   4'b0111,    // VRAM Write Lower 0
-    S6  =   4'b0101,    // VRAM Write Lower 1
-    S7  =   4'b0100,    // VIA Write
-    S8  =   4'b1100,    // VSync (to be added later)
-    S9  =   4'b1101,    // undefined
-    S10 =   4'b1111,    // undefined
-    S11 =   4'b1110,    // undefined
-    S12 =   4'b1010,    // undefined
-    S13 =   4'b1011,    // undefined
-    S14 =   4'b1001,    // undefined
-    S15 =   4'b1000;    // undefined
+// VRAM read signal
+//always @(posedge pixClk) begin nvramOE <= ~(hCount == 7); end
 
-logic [3:0] pState;
+// VRAM write signal
+always @(posedge pixClk) begin
+    if(hCount[3:1] == 0) nvramWE <= 1;
+    else if(hCount[3:1] == 1) nvramWE <= 0;
+    else if(hCount[3:1] == 6) nvramWE <= 1;
+end
 
-// And here is the much simplified primary state machine
-always @(negedge pixClk or negedge nReset) begin
-    if(!nReset) pState <= S2;   // resync on reset by jumping to idle state
-    else begin
-        case(pState)
-            S0: pState <= S1;   // first VRAM read state, always move to S1
-            S3: pState <= S4;   // first UDS write state, always move to S4
-            S5: pState <= S6;   // first LDS write state, always move to S6
-            /*S7: begin
-                
-                pState <= S2;
-            end*/
-            S2: begin
-                // here is where everything actually happens.
-                if(vSeq == 4'hF) pState <= S0;   // time for a read state
-                else if(cpuUWriteReq && !cpuUWriteSrv && vSeq < 4'hD) pState <= S3;
-                else if(cpuLWriteReq && !cpuLWriteSrv && vSeq < 4'hD) pState <= S5;
-                else if(cpuVIAReq    && !cpuVIASrv    && vSeq < 4'hE) pState <= S7;
-                else pState <= S2;
+// VRAM data/address busses
+always @(negedge pixClk) begin
+    if(hCount[0] && !hCount[1]) begin
+        case(hCount[3:2])
+            3: begin
+                // start read cycle
+                vramData <= 8'hZ;
+                vramAddr[14:6] <= vCount[9:1];
+                vramAddr[5:0] <= hCount[9:4];
+            end
+            default: begin
+                // write slots
+                vramAddr[14:1] <= cpuAddr[14:1] - 14'h1380;
+                if(!ncpuUDSr && !cpuLDSsrv) begin
+                    vramAddr[0] <= 0;
+                    vramData <= cpuData[15:8];
+                end else if(!ncpuLDSr && !cpuLDSsrv) begin
+                    vramAddr[0] <= 1;
+                    vramData <= cpuData[7:0];
+                end
             end
-            default: pState <= S2; // everyone ends up at S2 (idle)
         endcase
     end
 end
 
-// primary VRAM signal combination, based on the primary state machine
-always_comb begin
-    // VRAM Read Strobe
-    if((pState == S0 || pState == S1) && hLoad) nvramOE <= 0;
-    else nvramOE <= 1;
-
-    // VRAM Write Strobe
-    if(pState == S3 || pState == S5) nvramWE <= 0;
-    else nvramWE <= 1;
-    
-    // VRAM Chip Enable Signals
-    case(pState)
-        S0, S1: begin
-            if(hLoad) begin
-                nvramCE0 <= ~vidBufSel;
-                nvramCE1 <= vidBufSel;
-            end else begin
-                nvramCE0 <= 1;
-                nvramCE1 <= 1;
-            end
-        end
-        S3, S4, S5, S6: begin
-            nvramCE0 <= ~cpuBufSel;
-            nvramCE1 <= cpuBufSel;
-        end
-        default: begin
+// VRAM chip enable signals
+reg cpuUDSsrv, cpuLDSsrv;
+always @(posedge pixClk) begin
+    if(hCount[3:1] == 7 && fetchActive) begin
+        nvramCE0 <= vidBufSel;
+        nvramCE1 <= ~vidBufSel;
+        nvramOE <= 0;
+    end else if(!hCount[0] && hCount[1]) begin
+        // write cycle
+        if(!ncpuUDSr && !cpuUDSsrv) begin
+            nvramCE0 <= ~cpuAddr[15];
+            nvramCE1 <= cpuAddr[15];
+            cpuUDSsrv <= 1;
+        end else if(!ncpuLDSr && !cpuLDSsrv) begin
+            nvramCE0 <= ~cpuAddr[15];
+            nvramCE1 <= cpuAddr[15];
+            cpuLDSsrv <= 1;
+        end else begin
             nvramCE0 <= 1;
             nvramCE1 <= 1;
         end
-    endcase
-
-    // VRAM Address Bus
-    case(pState)
-        S0, S1: begin
-            // address bus for read cycles
-            if(hLoad) begin
-                vramAddr[14:6] <= vCount[9:1];
-                vramAddr[5:0] <= hCount[9:4];
-            end else begin
-                vramAddr <= 0;
-            end
-        end
-        S3, S4: begin
-            // address bus for upper write cycles
-            vramAddr[14:1] <= cpuAddrShift;
-            vramAddr[0] <= 0;
-        end
-        S5, S6: begin
-            // address bus for lower write cycles
-            vramAddr[14:1] <= cpuAddrShift;
-            vramAddr[0] <= 1;
-        end
-        default: begin
-            // address bus for idle cycles
-            vramAddr <= 0;
-        end
-    endcase
-
-    // VRAM Data bus
-    case(pState)
-        S3, S4 : vramData <= cpuData[15:8];
-        S5, S6 : vramData <= cpuData[7:0];
-        default: vramData <= 8'hZ;
-    endcase
+        nvramOE <= 1;
+    end else begin
+        nvramCE0 <= 1;
+        nvramCE1 <= 1;
+        nvramOE <= 1;
+    end
+    // reset the upper/lower serve signals when cycle ended by CPU
+    if(ncpuLDS) cpuLDSsrv <= 0;
+    if(ncpuUDS) cpuUDSsrv <= 0;
 end
 
-/******************************************************************************
- * Video Output Sequencing
- * Here is the primary video output shift register sequencing.
- * With these functions in place, it should be possible to strap the VRAM data
- * signals and see the strapped pattern output on screen.
- *****************************************************************************/
-logic [8:0] vidData;        // the video data we are displaying
-
-// output shift register
-always @(posedge pixClk) begin
-    if(pState == S1 && hLoad) begin
-        // store VRAM data in shift register
-        vidData[7:0] <= vramData;
-    end else if(!hCount[0] && vidActive) begin
-        // shift out video data
-        vidData[8:1] <= vidData[7:0];
-        vidData[0] <= 1;
+// Video data shift register & output
+reg [7:0] vidShiftr;
+always @(negedge pixClk) begin
+    if(hCount[3:0] == 4'hF) vidShiftr <= ~vramData;
+    else if(hCount[0]) begin
+        vidShiftr[7:1] <= vidShiftr[6:0];
+        vidShiftr[0] <= 0;
     end
 end
-
-// final video output
 always_comb begin
-    if(vidActive) vidOut <= ~vidData[8];
+    if(vidActive) vidOut = vidShiftr[7];
     else vidOut <= 0;
 end
 
 /******************************************************************************
  * CPU Bus Snooping
- * Watch the CPU bus for writes to the video buffer regions of memory and write
- * that data to VRAM. VRAM write cycles can occur during vidSeq 1 through 7.
- * High-order bytes are passed to VRAM on tick states and low-order bytes are 
- * passed to VRAM on tock states. After the VRAM writes are complete, state
- * machine waits for the CPU cycle to end before returning to idle.
+ * Watches the CPU bus and aligns its operations with the pixel clock
  *****************************************************************************/
-
-/* Main framebuffer starts $5900 below the top of RAM, alt frame buffer is
- * $8000 below the main frame buffer
- * ramSize is used to mask the CPU Address bits [21:19] to select the amount
- * of memory installed in the computer. Not all possible ramSize selections
- * are valid memory sizes when using 30-pin SIMMs in the Mac SE. 
- * They may be possible using PDS RAM expansion cards.
- * ramSize mainBuffer altBuffer ramTop+1 ramSize Valid?      Installed SIMMs
- *    $7    $3fa700    $3f2700   $400000  4.0MB    Y    [ 1MB   1MB ][ 1MB   1MB ]
- *    $6    $37a700    $372700   $380000  3.5MB    N
- *    $5    $2fa700    $2f2700   $300000  3.0MB    N
- *    $4    $27a700    $272700   $280000  2.5MB    Y    [ 1MB   1MB ][256kB 256kB]
- *    $3    $1fa700    $1f2700   $200000  2.0MB    Y    [ 1MB   1MB ][ ---   --- ]
- *    $2    $17a700    $172700   $180000  1.5MB    N  
- *    $1    $0fa700    $0f2700   $100000  1.0MB    Y    [256kB 256kB][256kB 256kB]
- *    $0    $07a700    $072700   $080000  0.5MB    Y    [256kB 256kB][ ---   --- ]
- */
-
-// keep track of pending CPU write requests and whether they have been serviced
-wire cpuUWriteReq, cpuLWriteReq, cpuVIAReq;
-reg  cpuUWriteSrv, cpuLWriteSrv, cpuVIASrv;
-wire cpuBufSel;
-wire cpuBufAddr;
-reg vidBufSel;
-wire [13:0] cpuAddrShift = cpuAddr[14:1] - 14'h1380;
-wire cpuBufRange;
-
-// these are some helpful signals that shortcut the CPU buffer & VIA addresses
-always_comb begin
-    /*if(cpuAddr[14:1] >= 14'h1380
-        && cpuAddr[14:1] < 14'h3E40) cpuBufRange <= 1;
-    else cpuBufRange <= 0;*/
-    cpuBufRange <= (cpuAddr[14:1] >= 14'h1380) & (cpuAddr[14:1] < 14'h3E40);
+reg ncpuUDSr, ncpuLDSr;
+always @(negedge pixClk) begin
+    // this condition evaluates true when cpu is writing to video buffer
     if(!ncpuAS && !cpuRnW
-            && !cpuAddr[23] && !cpuAddr[22]     // first two bits always 0
-            && !(cpuAddr[21] ^ ramSize[2])      // compare with RAM Size bits
-            && !(cpuAddr[20] ^ ramSize[1])
-            && !(cpuAddr[19] ^ ramSize[0])
-            && cpuAddr[18] && cpuAddr[17]       // next three bits always 1
-            && cpuAddr[16]                      // skip 15, it selects buffers
-            && cpuBufRange                      // only select buffer addresses
-    ) begin
-        cpuBufAddr <= 1;
+        && !cpuAddr[23] && !cpuAddr[22]
+        && !(cpuAddr[21] ^ ramSize[2])
+        && !(cpuAddr[20] ^ ramSize[1])
+        && !(cpuAddr[19] ^ ramSize[0])
+        && cpuAddr[18] && cpuAddr[17]
+        && cpuAddr[16]
+        && ((cpuAddr[14:1] >= 14'h1380)
+        && (cpuAddr[14:1] < 14'h3E40))) 
+    begin
+        if(!ncpuUDS) ncpuUDSr <= 0;
+        else ncpuUDSr <= 1;
+        if(!ncpuLDS) ncpuLDSr <= 0;
+        else ncpuLDSr <= 1;
     end else begin
-        cpuBufAddr <= 0;
-    end
-    cpuBufSel <= ~cpuAddr[15];                   // address bit 15 selects buffer
-
-    if(cpuBufAddr && !ncpuUDS) cpuUWriteReq <= 1;
-    else cpuUWriteReq <= 0;
-    if(cpuBufAddr && !ncpuLDS) cpuLWriteReq <= 1;
-    else cpuLWriteReq <= 0;
-
-    // VIA is in address block $E8,0000 - $EF,FFFF
-    // VIA register select pins (RS[3:0]) are wired to cpuAddr[12:9]
-    // VIA Output Register A is selected when RS[3:0]==$F
-    /*if(!ncpuAS && !cpuRnW && !ncpuUDS
-            && cpuAddr[23] && cpuAddr[22]       // VIA Address Select
-            && cpuAddr[21] && !cpuAddr[20]
-            && cpuAddr[19]
-            && cpuAddr[12] && cpuAddr[11]       // VIA ORA
-            && cpuAddr[10] && cpuAddr[9]
-    ) cpuVIAReq <= 1;
-    else cpuVIAReq <= 0;*/
-    // Mac ROM addresses Data Register A as vBase+vBufA:
-    // $EF,E1FE + (512*15) = $EF,FFFE
-    // shift right by one because no A0 and we get $77,FFFF
-    // This bit is giving me hell, so let's expand it
-    if(ncpuAS==0 && cpuRnW==0 && ncpuUDS==0
-            && cpuAddr == 22'h77FFFF) cpuVIAReq <= 1;
-    else cpuVIAReq <= 0;
-end
-
-// if there's an active CPU request and we've reached the state for servicing
-// that CPU request, then set a flag to mark that we have serviced it
-always @(posedge pixClk or posedge ncpuAS) begin
-    if(ncpuAS) begin
-        cpuUWriteSrv <= 0;
-        cpuLWriteSrv <= 0;
-        cpuVIASrv    <= 0;
-    end else begin
-        if(ncpuAS) begin
-            cpuUWriteSrv <= 0;
-            cpuLWriteSrv <= 0;
-            cpuVIASrv    <= 0;
-        end else begin
-            if(cpuUWriteReq && pState == S3) cpuUWriteSrv <= 1;
-            if(cpuLWriteReq && pState == S5) cpuLWriteSrv <= 1;
-            if(cpuVIAReq    && pState == S7) cpuVIASrv    <= 1;
-        end
+        ncpuUDSr <= 1;
+        ncpuLDSr <= 1;
     end
 end
 
-// store the video buffer selection bit
-always @(posedge pixClk or negedge nReset) begin
-    if(!nReset) vidBufSel <= 0;
-    // fine. no video buffer select. we use Main only.
-    //else if(pState == S7) vidBufSel <= ~cpuData[14];
-end
+// hold low for now
+reg vidBufSel = 0;
 
 endmodule
\ No newline at end of file

From a9b119fb6df737fdc3f7b6c54c0178f02c116927 Mon Sep 17 00:00:00 2001
From: techav <76832805+techav-homebrew@users.noreply.github.com>
Date: Fri, 22 Oct 2021 22:18:44 -0500
Subject: [PATCH 14/14] Mostly working

---
 Compiled/sevga.jed | 2590 +++++++++++++++++++++-----------------------
 Compiled/sevga.pof |  Bin 8023 -> 8022 bytes
 old/se-xga.sv      |  342 ------
 old/se-xga_bad.sv  |  229 ++++
 se-xga.sv          |  419 ++++---
 5 files changed, 1740 insertions(+), 1840 deletions(-)
 delete mode 100644 old/se-xga.sv
 create mode 100644 old/se-xga_bad.sv

diff --git a/Compiled/sevga.jed b/Compiled/sevga.jed
index be682cb..bcb670d 100644
--- a/Compiled/sevga.jed
+++ b/Compiled/sevga.jed
@@ -1,1501 +1,1401 @@
  Version 4.45.1 
 JEDEC file for: ATF1508 TQFP100
-Created on: Sat May 22 20:09:59 2021
+Created on: Fri Oct 22 22:15:01 2021
 
 *
 QF74136* QP100 * F0*
 NOTE 
 0         0         0         0         0         *
+L0
+1111111111111111
+1111110111111111111111111111111111111110
+1111111111111111111111111111111111111111*  NOTE PT 5 of MC 16(LAB A) *
 L96
-1111110000111111
-1111111111110111111111111111111110111111
-1111111111111111111111111111111111111111*  NOTE PT 4 of MC 16(LAB A) *
+1111111111111111
+1101011110011001100101010111010101011110
+0101100110101101110101100111010111111111*  NOTE PT 4 of MC 16(LAB A) *
 L192
 1111111111111111
-1111111111111111111111111111111111111111
-1101111111111111111111111101111111111111*  NOTE PT 3 of MC 16(LAB A) *
+1101011110011001100101010111010101011110
+0101100110111101100101100111010111111111*  NOTE PT 3 of MC 16(LAB A) *
 L288
 1111111111111111
-1111111111111111111111011111110111111111
-1111111101111111011101111110111111111111*  NOTE PT 2 of MC 16(LAB A) *
-L576
+1101011110011001100101010111010101011110
+0101100110111101110101100110010111111111*  NOTE PT 2 of MC 16(LAB A) *
+L384
 1111111111111111
-1111111111110111111111111111111101111111
-1111111111011111111111111111111111111111*  NOTE PT 2 of MC 15(LAB A) *
-L672
-1111111111111111
-1111111111011111110111111110111111101111
-1111111111110111110111110111111111111111*  NOTE PT 3 of MC 15(LAB A) *
-L768
-1111111111111111
-1111111111011111110111111111111110111111
-1111111111110111110111110111111111111111*  NOTE PT 4 of MC 15(LAB A) *
-L864
-1111111111111111
-1111111111011011110111111111111111111111
-1111111111110111110111110111111111111111*  NOTE PT 5 of MC 15(LAB A) *
-L960
-1011011111111111
-1111111111111111111111111111111111111111
-1111111111111111110111111111111111111111*  NOTE PT 5 of MC 14(LAB A) *
-L1056
-1011111111111111
-1111111111011111110111111111111111111111
-1111111111111111111011110111111111111111*  NOTE PT 4 of MC 14(LAB A) *
-L1152
-1111011111111111
-1111111111111111111111111110111111101111
-1111111111101111110111111111111111111111*  NOTE PT 3 of MC 14(LAB A) *
-L1248
-1111111111111111
-1111111111011111110111111110111111101111
-1111111111101111111011110111111111111111*  NOTE PT 2 of MC 14(LAB A) *
-L1536
-1111111111111111
-1111111111111111111111011111111111111111
-1111111101111111011101111110111111111111*  NOTE PT 2 of MC 13(LAB A) *
-L1632
+1111111111111111111111111111111111110110
+1111111111111111111111111111111111111111*  NOTE PT 1 of MC 16(LAB A) *
+L5760
 1111111111111111
 1111111111111111111111111111110111111111
-1111111111111111111111111101111111111111*  NOTE PT 3 of MC 13(LAB A) *
-L1728
-1111110000111111
-1111111111110111111111111111111110111111
-1111111111111111111111111111111111111111*  NOTE PT 4 of MC 13(LAB A) *
-L1920
-1111111111111111
-1111111111101111111111111111111111111111
-1111111111111111111111111011111111111111*  NOTE PT 5 of MC 12(LAB A) *
-L2016
-1111111111111111
-1111111111110111111111111101111101111111
-1111111111111111111111111111111111111111*  NOTE PT 4 of MC 12(LAB A) *
-L2112
-1111111111111111
-1111111111110111111111111111111101111111
-1111111111011111111111111111111111111111*  NOTE PT 3 of MC 12(LAB A) *
-L2208
-1111111111111111
-1111111111110111111111111111111101011111
-1111111111111111111111111111111111111111*  NOTE PT 2 of MC 12(LAB A) *
-L2304
-1111111111111111
-1111111111011111111111111111111111111111
-1111111111111111111111110111111111111111*  NOTE PT 1 of MC 12(LAB A) *
-L2496
-1111111111111111
-1111111111011111111011111110111111101111
-1111111111101111111111110111111111111111*  NOTE PT 2 of MC 11(LAB A) *
-L2592
-0111111111111111
-1111111111111111110111111110111111101111
-1111111111101111111111111111111111111111*  NOTE PT 3 of MC 11(LAB A) *
-L2688
-1011111111111111
-1111111111011111111011111111111111111111
-1111111111111111111111110111111111111111*  NOTE PT 4 of MC 11(LAB A) *
-L2784
-0011111111111111
-1111111111111111110111111111111111111111
-1111111111111111111111111111111111111111*  NOTE PT 5 of MC 11(LAB A) *
-L2976
-1111111111111111
-1111111111110111111111111101111101111111
-1111111111111111111111111111111111111111*  NOTE PT 4 of MC 10(LAB A) *
-L3072
-1111111111111111
-1111111111011011110111111111111111111111
-1111111111010111110111110111111111111111*  NOTE PT 3 of MC 10(LAB A) *
-L3168
-1111111111111111
-1111111111011111110111111111111110111111
-1111111111010111110111110111111111111111*  NOTE PT 2 of MC 10(LAB A) *
-L3264
-1111111111111111
-1111111111111111111111111111111111011111
-1111111111010111111111111111111111111111*  NOTE PT 1 of MC 10(LAB A) *
-L3360
-1111111111111111
-1111111111111111111111111101111111011111
-1111111111111111111111111111111111111111*  NOTE PT 1 of MC 9(LAB A) *
-L3456
-1111111111111111
-1111111111011111110111111101111110111111
-1111111111010111110111110111111111111111*  NOTE PT 2 of MC 9(LAB A) *
-L3552
-1111111111111111
-1111111111011011110111111101111111111111
-1111111111010111110111110111111111111111*  NOTE PT 3 of MC 9(LAB A) *
-L3648
-1111111111111111
-1111111111110111111111111111111101011111
-1111111111111111111111111111111111111111*  NOTE PT 4 of MC 9(LAB A) *
-L3840
-1111111111111111
-1111111111011111110111111101111111011111
-1111111111010111110111110111111111111111*  NOTE PT 5 of MC 8(LAB A) *
-L3936
-1111111111111111
-1111111111110111111111111111111101111111
-1111111111011111111111111111111111111111*  NOTE PT 4 of MC 8(LAB A) *
-L4032
-1111111111111111
-1111111111110111111111111101111101111111
-1111111111111111111111111111111111111111*  NOTE PT 3 of MC 8(LAB A) *
-L4128
-1111111111111111
-1111111111110111111111111111111101011111
-1111111111111111111111111111111111111111*  NOTE PT 2 of MC 8(LAB A) *
-L4224
-1111111111111111
-1111111111111111111111111111111111101111
-1111111111101011111111111111111111111111*  NOTE PT 1 of MC 8(LAB A) *
-L4320
-1111111111111111
-1111111111111111111111111110111111101111
-1111111111111111111111111111111111111111*  NOTE PT 1 of MC 7(LAB A) *
-L4416
-1111111111111111
-1111111111111111111111011111110111111111
-1101111101111111011101111110111111111111*  NOTE PT 2 of MC 7(LAB A) *
-L4512
-1111111111111111
-1111111111111111111111111111111111111111
-1111011111111111111111111101111111111111*  NOTE PT 3 of MC 7(LAB A) *
-L4608
-1111110000111111
-1111111111110111111111111111111110111111
-1111111111111111111111111111111111111111*  NOTE PT 4 of MC 7(LAB A) *
-L4800
-1111111111111111
-1111111111111011111111101111101111111111
-1110111110111111111111111110111111111111*  NOTE PT 5 of MC 6(LAB A) *
-L4896
-1111111111111111
-1111111111111011111111111111101011111111
-1110111111111111111111111110111111111111*  NOTE PT 4 of MC 6(LAB A) *
-L4992
-1111111111111111
-1111111111111011111111111111101111111111
-1111101111111111111111111110111111111111*  NOTE PT 3 of MC 6(LAB A) *
-L5088
-1111111111111111
-1111111111111011111111111111111111111111
-1111111111111111111111101110111111111111*  NOTE PT 2 of MC 6(LAB A) *
-L5184
-1111111111111111
-1111111111111011111111101111101111111111
-1110111111111111111110111110111111111111*  NOTE PT 1 of MC 6(LAB A) *
-L5280
-1111111111111111
-1111111111011111110111111111111111111111
-1111111111111111111111110111111111111111*  NOTE PT 1 of MC 5(LAB A) *
-L5376
-1111111111111111
-1111111111110111111111111110111111101111
-1111111111101111111111111111111111111111*  NOTE PT 2 of MC 5(LAB A) *
-L5472
-1111111111111111
-1111111111110111111111111111111110111111
-1111111111111111111111111111111111111111*  NOTE PT 3 of MC 5(LAB A) *
-L5568
-1111111111111111
-1111111111011011110111111101111101011111
-1111111111010111110111110111111111111111*  NOTE PT 4 of MC 5(LAB A) *
+1111111111111101111111111111111111111111*  NOTE PT 5 of MC 4(LAB A) *
 L5856
 1111111111111111
-1111111111111011111111111111111111111111
-1111111111111111111111111011111111111111*  NOTE PT 4 of MC 4(LAB A) *
+1111111111111111111101111111011111111111
+0111111111111101111111111111111111111111*  NOTE PT 4 of MC 4(LAB A) *
 L5952
 1111111111111111
-1111111111111111111111111111111110111111
-1111111111111111111111111011111111111111*  NOTE PT 3 of MC 4(LAB A) *
+1111111111111111111111110111111111111111
+1111111111111101111111111111111111111111*  NOTE PT 3 of MC 4(LAB A) *
 L6048
 1111111111111111
-1111111111111111111111111110111111101111
-1111111111101111111111111011111111111111*  NOTE PT 2 of MC 4(LAB A) *
-L6144
-1111111111111111
-1111111111011111110111111111111111111111
-1111111111111111110111110111111111111111*  NOTE PT 1 of MC 4(LAB A) *
-L6240
-1111111111111111
-1111111111111111111111111111111111111111
-1111111101111111101111111110111111111111*  NOTE PT 1 of MC 3(LAB A) *
-L6336
-1111111111111111
-1111111111111111111111111111101011111111
-1110101101111111101110101111111111111111*  NOTE PT 2 of MC 3(LAB A) *
-L6432
-1111111111111111
-1111111111111111111111111111111111111111
-1111111110111111011101111110111111111111*  NOTE PT 3 of MC 3(LAB A) *
-L6528
-1111110000111111
-1111111111110111111111111111111110111111
-1111111111111111111111111111111111111111*  NOTE PT 4 of MC 3(LAB A) *
-L6624
-1111111111111111
-1111111111111111111111111111111111111111
-1111111101111111111110111110111111111111*  NOTE PT 5 of MC 3(LAB A) *
-L6816
-1111111111111111
-1111111111111111111111111111101011111111
-1110101110111111011101101111111111111111*  NOTE PT 4 of MC 2(LAB A) *
-L6912
-1111111111111111
-1111111111111111111111101111101011111111
-1110101101111111101111101111111111111111*  NOTE PT 3 of MC 2(LAB A) *
-L7008
-1111111111111111
-1111111111111111111111101111101011111111
-1110101101111111111110101111111111111111*  NOTE PT 2 of MC 2(LAB A) *
-L7104
-1111111111111111
-1111111111110111111111111111111101111111
-1111111111111111111111111111111111111111*  NOTE PT 1 of MC 2(LAB A) *
-L7200
-1111111111111111
-1111111111011111111111111111111111111111
-1111111111111111111111110111111111111111*  NOTE PT 1 of MC 1(LAB A) *
+1111111111111111111111111111111111101111
+1111111111111111111111111111111111111111*  NOTE PT 2 of MC 4(LAB A) *
 L7296
 1111111111111111
-1111111111011111110111111110111111101111
-1111111111101011110111110111111111111111*  NOTE PT 2 of MC 1(LAB A) *
+1111111111111111111111111111111111111111
+1111111111111111111111111111111111111111*  NOTE PT 2 of MC 1(LAB A) *
 L7392
-1110111111111111
-1111111111111111111111111110111111101111
-1111111111100111111111111111111111111111*  NOTE PT 3 of MC 1(LAB A) *
+1111111111111111
+1111111101111111111111111111111111111111
+1111111111111111111111111111111111111111*  NOTE PT 3 of MC 1(LAB A) *
 L7488
-1011111111111111
-1111111111011111110111111111111111111111
-1111111111111011110111110111111111111111*  NOTE PT 4 of MC 1(LAB A) *
-L7584
-1010111111111111
-1111111111111111111111111111111111111111
-1111111111110111111111111111111111111111*  NOTE PT 5 of MC 1(LAB A) *
-L7776
 1111111111111111
-1110011110111101111111101111111111111111
-1111111111111111111111111111111111111111*  NOTE PT 4 of MC 32(LAB B) *
-L7968
-1111111111111111
-1111111111111111111111111111111111111101
-1111111111111111111111111111111111111111*  NOTE PT 2 of MC 32(LAB B) *
-L8256
-1111111111111111
-1111111111111111111111111111111111111111
-1111111111111111111111111111110111111111*  NOTE PT 2 of MC 31(LAB B) *
-L8448
-1111111111111111
-1110011110111101111111101111111111111111
-1111111111111111111111111111111111111111*  NOTE PT 4 of MC 31(LAB B) *
-L8736
-1111111111111111
-1110011110111101111111101111111111111111
-1111111111111111111111111111111111111111*  NOTE PT 4 of MC 30(LAB B) *
-L8928
-1111111111111111
-1111111111111111111111111111111111111111
-0111111111111111111111111111111111111111*  NOTE PT 2 of MC 30(LAB B) *
-L9216
-1111111111111111
-1111111111111111111111111111111110111111
-1111111111111111111111111111111111111111*  NOTE PT 2 of MC 29(LAB B) *
-L9408
-1111111111111111
-1110011110111101111111101111111111111111
-1111111111111111111111111111111111111111*  NOTE PT 4 of MC 29(LAB B) *
-L9696
-1111111111111111
-1110011110111101111111101111111111111111
-1111111111111111111111111111111111111111*  NOTE PT 4 of MC 28(LAB B) *
-L9888
-1111111111111111
-1111111111111111111111111111110111111111
-1111111111111111111111111111111111111111*  NOTE PT 2 of MC 28(LAB B) *
-L10176
-1111111111111111
-1111111111111111111111111111111111111111
-1111110111111111111111111111111111111111*  NOTE PT 2 of MC 27(LAB B) *
-L10368
-1111111111111111
-1110011110111101111111101111111111111111
-1111111111111111111111111111111111111111*  NOTE PT 4 of MC 27(LAB B) *
-L11136
-1111111111111111
-1111111111111111111101111111111111111111
-1111111111111111111111111111111111111111*  NOTE PT 2 of MC 25(LAB B) *
-L11328
-1111111111111111
-1110011110111101111111101111111111111111
-1111111111111111111111111111111111111111*  NOTE PT 4 of MC 25(LAB B) *
-L11616
-1111111111111111
-1110011110111101111111101111111111111111
-1111111111111111111111111111111111111111*  NOTE PT 4 of MC 24(LAB B) *
-L11808
-1111111111111111
-1111110111111111111111111111111111111111
-1111111111111111111111111111111111111111*  NOTE PT 2 of MC 24(LAB B) *
-L12096
-1111111111111111
-1111111111111111111111111111111111111111
-1111111111111111111101111111111111111111*  NOTE PT 2 of MC 23(LAB B) *
-L12288
-1111111111111111
-1110011110111101111111101111111111111111
-1111111111111111111111111111111111111111*  NOTE PT 4 of MC 23(LAB B) *
-L12576
-1111111111111111
-1110011110111101111111101111111111111111
-1111111111111111111111111111111111111111*  NOTE PT 4 of MC 22(LAB B) *
-L12768
+1101011010011001110101010111010101011001
+0101100110111101110101100111010111111111*  NOTE PT 4 of MC 1(LAB A) *
+L7872
 1111111111111111
 1111111111111111111111111101111111111111
-1111111111111111111111111111111111111111*  NOTE PT 2 of MC 22(LAB B) *
-L13056
+1111111111111111111111111101111111111111*  NOTE PT 3 of MC 32(LAB B) *
+L7968
 1111111111111111
-1111111111011111111111111111111111111111
-1111111111111111111111111111111111111111*  NOTE PT 2 of MC 21(LAB B) *
-L13248
+1111110111111111111111111110111111011111
+1111111111111111111111111111011111111111*  NOTE PT 2 of MC 32(LAB B) *
+L8256
 1111111111111111
-1110011110111101111111101111111111111111
-1111111111111111111111111111111111111111*  NOTE PT 4 of MC 21(LAB B) *
-L13440
+1111111011111111111111111110111111111111
+1111111111111111111111111111111111111111*  NOTE PT 2 of MC 31(LAB B) *
+L9216
 1111111111111111
-1111111111111111011111111111111111111111
-1110111111111111111111101111011111111111*  NOTE PT 5 of MC 20(LAB B) *
-L13536
+0111110101111111011111111110111111011111
+0111111101111111111101111101011111111111*  NOTE PT 2 of MC 29(LAB B) *
+L9312
 1111111111111111
-1111111111111111101111111111111111111111
-1101111111111111111111101111011111111111*  NOTE PT 4 of MC 20(LAB B) *
-L13632
+1111111111111111110111111101111111111111
+1111111111111111111111111111111111111111*  NOTE PT 3 of MC 29(LAB B) *
+L9600
+1111111111111111
+1111101111111111111111111111111111111111
+1111111111111111111111111111111111111111*  NOTE PT 5 of MC 28(LAB B) *
+L9696
+1111111111111111
+1110111111111111111111111111111111111111
+1111101111101110111111111011111011111111*  NOTE PT 4 of MC 28(LAB B) *
+L9792
 1111111111111111
 1111111111111111111111111111111111111111
-1111101111011111111111101111011111111111*  NOTE PT 3 of MC 20(LAB B) *
-L13728
+1111101111101011111111111011111011111111*  NOTE PT 3 of MC 28(LAB B) *
+L9888
+1111111111111111
+1111111111111011111111111111111111111111
+1111101111111111111111111111111011111111*  NOTE PT 2 of MC 28(LAB B) *
+L9984
 1111111111111111
 1111111111111111111111111111111111111111
-1111111111111111111111101111011111111111*  NOTE PT 2 of MC 20(LAB B) *
-L13824
-0111111111111111
-1111111111111111111111111011111111101111
-1111111111111111111111101110011111111111*  NOTE PT 1 of MC 20(LAB B) *
-L13920
-1111111111111111
+1111111011111111111111111111111111111111*  NOTE PT 1 of MC 28(LAB B) *
+L10176
+0000011111111111
 1111111111111111111111111111111111111111
-1111011111101111111111101111011111111111*  NOTE PT 1 of MC 19(LAB B) *
-L14016
+1111111111111111111111111111111111111111*  NOTE PT 2 of MC 27(LAB B) *
+L10368
 1111111111111111
-1111111111111111111111111111111111101111
-1111111111111111111011101111011111111111*  NOTE PT 2 of MC 19(LAB B) *
-L14112
+1111111111111111110111111111110111111111
+1111111111111111111111111111111111111111*  NOTE PT 4 of MC 27(LAB B) *
+L10560
 1111111111111111
-1111111111110111111111111111111111111111
-1111111111110111111111101111011111111111*  NOTE PT 3 of MC 19(LAB B) *
-L14208
+1111101111111111111001111111111111111111
+1111111111101111111111101011111011111111*  NOTE PT 5 of MC 26(LAB B) *
+L10656
 1111111111111111
-1111111111111111111011111111011111111111
-1111111111111111111111101111011111111111*  NOTE PT 4 of MC 19(LAB B) *
-L14304
+1111101111111011111001111111111111111111
+1111111111111111111111101111111011111111*  NOTE PT 4 of MC 26(LAB B) *
+L10752
 1111111111111111
-1111111111111111110111111111101111111111
-1111111111111111111111101111011111111111*  NOTE PT 5 of MC 19(LAB B) *
-L14880
+1111101111111111111001111111111111111111
+1111101111111111111111101111111111111111*  NOTE PT 3 of MC 26(LAB B) *
+L10848
 1111111111111111
-1111111111111111111111111111111101111111
-1111111111111111011111111111111111111111*  NOTE PT 1 of MC 17(LAB B) *
-L14976
+1111111111111111111001111111111111111111
+1111111011111111111111101111111111111111*  NOTE PT 2 of MC 26(LAB B) *
+L10944
 1111111111111111
-1111111111111111111111111111111111110111
-1111111111111111111111111111111111111111*  NOTE PT 2 of MC 17(LAB B) *
-L15168
+1111101111111111111001111111111111111111
+1111111111111011111111101011111011111111*  NOTE PT 1 of MC 26(LAB B) *
+L11040
 1111111111111111
-1110011110111101111111101111111111111111
-1111111111111111111111111111111111111111*  NOTE PT 4 of MC 17(LAB B) *
-L15456
+1111110111111111111111111111111111011111
+1111111111111111111111111111111111111111*  NOTE PT 1 of MC 25(LAB B) *
+L11136
 1111111111111111
-1111011011111111111111111011111111111110
-1111111111111111110111111111111111111111*  NOTE PT 4 of MC 48(LAB C) *
-L15648
+1111111101111111110111111111111111111111
+1111111101111111111111111111111111111111*  NOTE PT 2 of MC 25(LAB B) *
+L11232
 1111111111111111
-1111111111111111111111111111111111111111
-1101111111111111111111111111111111111111*  NOTE PT 2 of MC 48(LAB C) *
-L15936
-1111111111111111
-1111111111101111111111111111111111111111
-1011111011111111111101111111111111111111*  NOTE PT 2 of MC 47(LAB C) *
-L16416
-1111111111111111
-1111011011111111111111111011111111111110
-1111111111111111110111111111111111111111*  NOTE PT 4 of MC 46(LAB C) *
-L16608
-1111111111111111
-1111111111111111111111111111111111011111
-1111111111111111111111111111111111111111*  NOTE PT 2 of MC 46(LAB C) *
-L16896
-1111111111111111
-1111111111111111111111111111110111111111
-1111111111111111111111111111111111111111*  NOTE PT 2 of MC 45(LAB C) *
-L17088
-1111111111111111
-1111011011111111111111111011111111111110
-1111111111111111110111111111111111111111*  NOTE PT 4 of MC 45(LAB C) *
-L17568
-1111111111111111
-1101111111111111111111111111111111111111
-1111111111111111111111111111111111111111*  NOTE PT 2 of MC 44(LAB C) *
-L17856
-1111111111111111
-1111111111111111111111111111111111111111
-1111111111110111111111111111111111111111*  NOTE PT 2 of MC 43(LAB C) *
-L18048
-1111111111111111
-1111011011111111111111111011111111111110
-1111111111111111110111111111111111111111*  NOTE PT 4 of MC 43(LAB C) *
-L18336
-1111111111111111
-1111011011111111111111111011111111111110
-1111111111111111110111111111111111111111*  NOTE PT 4 of MC 42(LAB C) *
-L18528
+1111111101111111010111111111111111111111
+1111111111111111111111111111111111111111*  NOTE PT 3 of MC 25(LAB B) *
+L11328
 1111111111111111
 1111111111111111110111111111111111111111
-1111111111111111111111111111111111111111*  NOTE PT 2 of MC 42(LAB C) *
-L18816
+0111111111111111111111111111111111111111*  NOTE PT 4 of MC 25(LAB B) *
+L11424
 1111111111111111
-1111111111101111111111111111111111111111
-1011111011111111011111111111111111111111*  NOTE PT 2 of MC 41(LAB C) *
-L18912
+1111111011111111111111111111111111101111
+1111111111111111111111111111111111111111*  NOTE PT 5 of MC 25(LAB B) *
+L11520
+1111111111111111
+1111111111111111110111111111111111111111
+1111111111111111111111111111011111111111*  NOTE PT 5 of MC 24(LAB B) *
+L11616
+1111111111111111
+1011111110111111101011111111111111111111
+1011111110111111111110111110101111111111*  NOTE PT 4 of MC 24(LAB B) *
+L11712
+1111111111111111
+1111011111111111111111111111111111111111
+1111110111111111111111111111111111111111*  NOTE PT 3 of MC 24(LAB B) *
+L11808
 1111111111111111
 1111111111111111111111111111111111111111
-1111110101111111111111111111111111111111*  NOTE PT 3 of MC 41(LAB C) *
-L19008
+1111010111111111111111111111110111111111*  NOTE PT 2 of MC 24(LAB B) *
+L11904
 1111111111111111
-1111111111111111111111111111111111111111
-0111111101111111111111111111111111111111*  NOTE PT 4 of MC 41(LAB C) *
-L19104
+1111110111111111111111111111111111111111
+1111111111111111111111111111111111111111*  NOTE PT 1 of MC 24(LAB B) *
+L12000
 1111111111111111
-1111111111011111111111111111111111111111
-1111111101111111111111111111111111111111*  NOTE PT 5 of MC 41(LAB C) *
-L19296
-1111111111111111
-1111011011111111111111111011111111111110
-1111111111111111110111111111111111111111*  NOTE PT 4 of MC 40(LAB C) *
-L19488
+1111111111111111110111111111111111111111
+0111111111111111111111111111111111111111*  NOTE PT 1 of MC 23(LAB B) *
+L12096
 1111111111111111
 1111111111110111111111111111111111111111
-1111111111111111111111111111111111111111*  NOTE PT 2 of MC 40(LAB C) *
-L19776
+1111010111010111111111111111111111111111*  NOTE PT 2 of MC 23(LAB B) *
+L12192
 1111111111111111
-1111111111111111111111111110111111111111
-1111111111111111111111111111111111111111*  NOTE PT 2 of MC 39(LAB C) *
-L19968
+1111111111110111111111111111111111111111
+1111010111111111111111110111111111111111*  NOTE PT 3 of MC 23(LAB B) *
+L12288
 1111111111111111
-1111011011111111111111111011011111111110
-1111111111111111110111111111111111111111*  NOTE PT 4 of MC 39(LAB C) *
-L20256
+1111111111111111110111111111111111111111
+1111111111111111111101111111111111111111*  NOTE PT 4 of MC 23(LAB B) *
+L12384
 1111111111111111
-1111011011111111111111111011111111111110
-1111111111111111110111111111111111111111*  NOTE PT 4 of MC 38(LAB C) *
-L20448
+1111111111111111110111111111111111111111
+1111111111111111111111111101111111111111*  NOTE PT 5 of MC 23(LAB B) *
+L12480
+1111111111111111
+1111111111111111010111111111111111111111
+1111111111111111111111111111111111111111*  NOTE PT 5 of MC 22(LAB B) *
+L12576
+1111111111111111
+1111111111111111110111111111111111111111
+1111111101111111111111111111111111111111*  NOTE PT 4 of MC 22(LAB B) *
+L12672
+1111111111111111
+0111111111111111110111111111111111111111
+1111111111111111111111111111111111111111*  NOTE PT 3 of MC 22(LAB B) *
+L12768
+1111111111111111
+1111111101111111110111111111111111111111
+1111111111111111111111111111111111111111*  NOTE PT 2 of MC 22(LAB B) *
+L12960
+1111111111111111
+1111101111111111111111111111111111111111
+1111110111111111111111111111111111111111*  NOTE PT 1 of MC 21(LAB B) *
+L13056
+1111111111111111
+1111110111111111111111111110111111011111
+1111111111111111111111111101011111111111*  NOTE PT 2 of MC 21(LAB B) *
+L13152
+1111111111111111
+1111111111111111111111111101111111111111
+1111111111111111111101111111111111111111*  NOTE PT 3 of MC 21(LAB B) *
+L13632
+1111111111111111
+1111111101111111111111111101111111111111
+1111111111111111111111111111111111111111*  NOTE PT 3 of MC 20(LAB B) *
+L13728
+1111111111111111
+0111110111111111011111111110111111011111
+1111111101111111111101111101011111111111*  NOTE PT 2 of MC 20(LAB B) *
+L13824
+1111111111111111
+1101011111110111111111111111111111111111
+1111011011010101111111110111110111111111*  NOTE PT 1 of MC 20(LAB B) *
+L13920
+1111111111111111
+1111111111111011111111111111111111111111
+1111100111111111111111111111111011111111*  NOTE PT 1 of MC 19(LAB B) *
+L14016
+1111111111111111
+1111110111111111111111111110111111011111
+1111111111111111111101111101011111111111*  NOTE PT 2 of MC 19(LAB B) *
+L14112
+1111111111111111
+0111111111111111111111111101111111111111
+1111111111111111111111111111111111111111*  NOTE PT 3 of MC 19(LAB B) *
+L14592
+1111111111111111
+1111111111111111111111111101111111111111
+1111111111111111111111111111011111111111*  NOTE PT 3 of MC 18(LAB B) *
+L14688
+1111111111111111
+1111110111111111111111111110111111011111
+1111111111111111111111111111111111111111*  NOTE PT 2 of MC 18(LAB B) *
+L14784
 1111111111111111
 1111111111111111111111111111111111111111
-1111111111111111111111111101111111111111*  NOTE PT 2 of MC 38(LAB C) *
-L20736
+1111100111101011111111111011111011111111*  NOTE PT 1 of MC 18(LAB B) *
+L14880
 1111111111111111
-1111111111111111111111111111111101111111
-1111111111111111111111111111111111111111*  NOTE PT 2 of MC 37(LAB C) *
-L20928
+1110111111111111111111111111111111111111
+1111100111101110111111111011111011111111*  NOTE PT 1 of MC 17(LAB B) *
+L14976
 1111111111111111
-1111011011111111111111111011111111111110
-1111111111111111110111111111111111111111*  NOTE PT 4 of MC 37(LAB C) *
-L21216
+1111111110111111110111111111111111111111
+1011111111111111111111111111111111111111*  NOTE PT 2 of MC 17(LAB B) *
+L15456
 1111111111111111
-1111011011111111111111111011111111111110
-1111111111111111110111111111111111111111*  NOTE PT 4 of MC 36(LAB C) *
-L21408
+1111111111111111111111111111111111111101
+1111110111111111111111111111111111111111*  NOTE PT 4 of MC 48(LAB C) *
+L15648
 1111111111111111
-1111111111111101111111111111111111111111
-1111111111111111111111111111111111111111*  NOTE PT 2 of MC 36(LAB C) *
-L21696
+1111111111111111111111111101111111111111
+1111111111111110111111111111111111111111*  NOTE PT 2 of MC 48(LAB C) *
+L15936
 1111111111111111
 1111111111111111111111111111111111111111
-1111111111111111111111011111111111111111*  NOTE PT 2 of MC 35(LAB C) *
-L21888
+1111111101111111111111111111110111111111*  NOTE PT 2 of MC 47(LAB C) *
+L16032
 1111111111111111
-1111011011111111111111111011111111111110
-1111111111111111110111111111111111111111*  NOTE PT 4 of MC 35(LAB C) *
-L22176
-1111111111111111
-1111011011111111111111111011111111111110
-1111111111111111110111111111111111111111*  NOTE PT 4 of MC 34(LAB C) *
-L22368
+1111111111111111111111111111111111111111
+1111101110111111111111111101111111111111*  NOTE PT 3 of MC 47(LAB C) *
+L16128
 1111111111111111
 1111111111111111111111011111111111111111
-1111111111111111111111111111111111111111*  NOTE PT 2 of MC 34(LAB C) *
-L22656
+1111011110111111111111111111111111111111*  NOTE PT 4 of MC 47(LAB C) *
+L16320
+1111111111101111
+1111111111111111011111111111111111011111
+1111111111101101111111111111111111111111*  NOTE PT 5 of MC 46(LAB C) *
+L16416
 1111111111111111
-1111111111101111111111111111111111111111
-1011111011111111111111111111110111111111*  NOTE PT 2 of MC 33(LAB C) *
-L22752
+1111111111111111111111111111111111111101
+1111110111111111111111111111111111111111*  NOTE PT 4 of MC 46(LAB C) *
+L16512
+1111111111011111
+1010111110111111111111111111111111111111
+1111111111011111111111111111111111111111*  NOTE PT 3 of MC 46(LAB C) *
+L16608
 1111111111111111
+1010111110111111011111111111111111011111
+1111111111101101111111111111111111111111*  NOTE PT 2 of MC 46(LAB C) *
+L16704
+1111111111001111
 1111111111111111111111111111111111111111
-1111010111111111111111111111111111111111*  NOTE PT 3 of MC 33(LAB C) *
-L22848
-1111111111111111
-1111111111111111111111111111111111111111
-0111011111111111111111111111111111111111*  NOTE PT 4 of MC 33(LAB C) *
-L22944
-1111111111111111
-1111111111011111111111111111111111111111
-1111011111111111111111111111111111111111*  NOTE PT 5 of MC 33(LAB C) *
-L23040
-1111111111111111
-0111011110111110111110111111111101010111
-1111111111011101111111111101111111111111*  NOTE PT 5 of MC 64(LAB D) *
-L23136
-1111111111111111
-0111011110111110111110111111111111010111
-1111111111011101011111111101111111111111*  NOTE PT 4 of MC 64(LAB D) *
-L23232
-1111111111111111
-0111011110111110111110111111111111010111
-1101111111011101111111111101111111111111*  NOTE PT 3 of MC 64(LAB D) *
-L23328
-1111111111111111
-1111011110111110111110111111111111111111
-1111111111011111111111111111111111111111*  NOTE PT 2 of MC 64(LAB D) *
-L23424
-1111111111111111
-1011011110111110111110111111111111101011
-1111111111011111111111111110111111111111*  NOTE PT 1 of MC 64(LAB D) *
-L27456
-1111111111111111
-1111111111101111111111111111111111111111
-1011111011111111111111011111111111111111*  NOTE PT 2 of MC 55(LAB D) *
-L27552
-1111111111111111
-1111111111111111111111111111111111111111
-1111110111111111111111111111011111111111*  NOTE PT 3 of MC 55(LAB D) *
-L27648
-1111111111111111
-1111111111111111111111111111111111111111
-0111111111111111111111111111011111111111*  NOTE PT 4 of MC 55(LAB D) *
-L27744
-1111111111111111
-1111111111011111111111111111111111111111
-1111111111111111111111111111011111111111*  NOTE PT 5 of MC 55(LAB D) *
-L27840
-1111111111111111
-1111111111011111111111111111111111111111
-1111111111111111110111111111111111111111*  NOTE PT 5 of MC 54(LAB D) *
-L27936
-1111111111111111
-1111111111111111111111111111111111111111
-0111111111111111110111111111111111111111*  NOTE PT 4 of MC 54(LAB D) *
-L28032
-1111111111111111
-1111111111111111111111111111111111111111
-1111110111111111110111111111111111111111*  NOTE PT 3 of MC 54(LAB D) *
-L28128
-1111111111111111
-1111111111101111111111111111111111111111
-1011111011111111111111110111111111111111*  NOTE PT 2 of MC 54(LAB D) *
-L28416
-1111111111111111
-1111111111101111111111011111111111111111
-1011111011111111111111111111111111111111*  NOTE PT 2 of MC 53(LAB D) *
-L28512
-1111111111111111
-1111111111111111111111111111111111111111
-1111110111111111111101111111111111111111*  NOTE PT 3 of MC 53(LAB D) *
-L28608
-1111111111111111
-1111111111111111111111111111111111111111
-0111111111111111111101111111111111111111*  NOTE PT 4 of MC 53(LAB D) *
-L28704
-1111111111111111
-1111111111011111111111111111111111111111
-1111111111111111111101111111111111111111*  NOTE PT 5 of MC 53(LAB D) *
-L29376
-1111111111111111
-1111111111101111111111111101111111111111
-1011111011111111111111111111111111111111*  NOTE PT 2 of MC 51(LAB D) *
-L29472
-1111111111111111
-1111111111110111111111111111111111111111
-1111110111111111111111111111111111111111*  NOTE PT 3 of MC 51(LAB D) *
-L29568
-1111111111111111
-1111111111110111111111111111111111111111
-0111111111111111111111111111111111111111*  NOTE PT 4 of MC 51(LAB D) *
-L29664
-1111111111111111
-1111111111010111111111111111111111111111
-1111111111111111111111111111111111111111*  NOTE PT 5 of MC 51(LAB D) *
-L29760
-1111111111111111
-1111111111111111111111111111111101110111
-1111111111111101011111111111111111111111*  NOTE PT 5 of MC 50(LAB D) *
-L29856
-1111111111111111
-1111111011111111110111111011111111111110
-1111111101111111111111111111111111111111*  NOTE PT 4 of MC 50(LAB D) *
-L29952
-1111111111111111
-0111111111111111111111111111111111111111
-1111111111111101111111111111111111111111*  NOTE PT 3 of MC 50(LAB D) *
-L30048
+1111111111011111111111111111111111111111*  NOTE PT 1 of MC 46(LAB C) *
+L16800
+1111111101111111
+1111111111111111111111110111110111111111
+1111111111111111111111111111111111111111*  NOTE PT 1 of MC 45(LAB C) *
+L16896
 1111111111111111
 1111111111111111111111111111111111101111
-1111111111111111111111111111111111111111*  NOTE PT 2 of MC 50(LAB D) *
-L30144
+1111111111111110111111111111111111111111*  NOTE PT 2 of MC 45(LAB C) *
+L16992
+1111111111111111
+1111111111111111111111111111111111011111
+1111111111111101111111111111111111111111*  NOTE PT 3 of MC 45(LAB C) *
+L17088
+1111111111111111
+1111111111111111111111111111111111111101
+1111110111111111111111111111111111111111*  NOTE PT 4 of MC 45(LAB C) *
+L17184
+1111111110111111
+0111111111111111111111110111110111111111
+1111111111111111111111111111111111111111*  NOTE PT 5 of MC 45(LAB C) *
+L17376
+1111111111111111
+1111111111011111111111111111111111111111
+1111011110111111111111111111111111111111*  NOTE PT 4 of MC 44(LAB C) *
+L17472
+1111111111111111
+1111111111111111111111011111111111111111
+1111101110111111111111111111111111111111*  NOTE PT 3 of MC 44(LAB C) *
+L17568
 1111111111111111
 1111111111111111111111111111111111111111
-1111111111111101111111111101111111111111*  NOTE PT 1 of MC 50(LAB D) *
+1111111101111111011111111111111111111111*  NOTE PT 2 of MC 44(LAB C) *
+L17664
+1111111111111111
+1111111111111111111111110111110111111111
+1111111111111111111111111111111111111111*  NOTE PT 1 of MC 44(LAB C) *
+L17760
+1111111111111111
+1111111111111111011111111111111111011111
+1111111111111101111111111111111111111111*  NOTE PT 1 of MC 43(LAB C) *
+L17856
+1111111111111111
+1111111111011111111111111111111111111111
+1111111111111111111111111111111111111111*  NOTE PT 2 of MC 43(LAB C) *
+L18048
+1111111111111111
+1111111111111111111111111111111111111111
+1111101110111111111111111111111111111111*  NOTE PT 4 of MC 43(LAB C) *
+L18336
+1111111111111111
+1111111111111111111111111111111111111111
+1111011110111111111111111101111111111111*  NOTE PT 4 of MC 42(LAB C) *
+L18432
+1111111111111111
+1111011111111111111111111111111111111111
+1111101110111111111111111111111111111111*  NOTE PT 3 of MC 42(LAB C) *
+L18528
+1111111111111111
+1111111111111111111111111111111111111111
+1111111101111111110111111111111111111111*  NOTE PT 2 of MC 42(LAB C) *
+L18624
+1111111111111111
+1111111111111111101111111111101111111111
+1111111111101111111111111111111111111111*  NOTE PT 1 of MC 42(LAB C) *
+L18720
+1111111111111111
+1110111110111111111111111111111111111111
+1111111111111111111111111111111111111111*  NOTE PT 1 of MC 41(LAB C) *
+L18816
+1111111111111111
+0111111111111111011111111011011111011111
+1111111111011101111111111111111111111111*  NOTE PT 2 of MC 41(LAB C) *
+L18912
+1111111111111111
+0111111111111111011111111111011011011111
+1111111111011101111111111111111111111111*  NOTE PT 3 of MC 41(LAB C) *
+L19008
+1111111111111111
+1111111111111111111111111111111111111101
+1111110111111111111111111111111111111111*  NOTE PT 4 of MC 41(LAB C) *
+L19104
+1111111111111111
+1101111111111111111111110111110111111111
+1111111111111111111111111111111111111111*  NOTE PT 5 of MC 41(LAB C) *
+L19200
+1111111111111111
+0101111111111111111111110111110111111111
+1111111111111111111111111111111111111111*  NOTE PT 5 of MC 40(LAB C) *
+L19296
+1111111111111111
+1111111111111111111111111111111111111101
+1111110111111111111111111111111111111111*  NOTE PT 4 of MC 40(LAB C) *
+L19392
+1111111111111111
+1111111111111111011111111111011011011111
+1111111111011101111111111111111111111111*  NOTE PT 3 of MC 40(LAB C) *
+L19488
+1111111111111111
+1111111111111111011111111011011111011111
+1111111111011101111111111111111111111111*  NOTE PT 2 of MC 40(LAB C) *
+L19584
+1111111111111111
+0111111101111111111111110111110111111111
+1111111111111111111111111111111111111111*  NOTE PT 1 of MC 40(LAB C) *
+L19680
+1111111111111111
+1110111110111111011111111111011111011111
+1111111111011101111111111111111111111111*  NOTE PT 1 of MC 39(LAB C) *
+L19776
+1111111111111111
+0111111111111111111111110111110111111111
+1111111111011111111111111111111111111111*  NOTE PT 2 of MC 39(LAB C) *
+L19872
+1111111111111111
+0111111111111111111111110111010111111111
+1111111111111111111111111111111111111111*  NOTE PT 3 of MC 39(LAB C) *
+L19968
+1111111111111111
+0111111111111111011111110111110111111111
+1111111111111101111111111111111111111111*  NOTE PT 4 of MC 39(LAB C) *
+L20064
+1111111111111111
+0111111111111111011111110111110111011111
+1111111111111111111111111111111111111111*  NOTE PT 5 of MC 39(LAB C) *
+L20160
+1111111111111111
+1110111110111111111111110111101111101111
+1111111111101110111111111111111111111111*  NOTE PT 5 of MC 38(LAB C) *
+L20256
+1111111111111111
+1111111111111111111111111111111111111101
+1111110111111111111111111111111111111111*  NOTE PT 4 of MC 38(LAB C) *
+L20352
+1111111111111111
+1110111110111111101111110111101111111111
+1111111111101111111111111111111111111111*  NOTE PT 3 of MC 38(LAB C) *
+L20448
+1111111111111111
+1010111110111111111111110111111111111111
+1111111111111111111111111111111111111111*  NOTE PT 2 of MC 38(LAB C) *
+L20544
+1111011111111111
+1111111111111111111111110111111011111111
+1111111111111111111111111111111111111111*  NOTE PT 1 of MC 38(LAB C) *
+L20640
+1111111111111111
+0101111101111111011111111111011111011111
+1111111111011101111111111111111111111111*  NOTE PT 1 of MC 37(LAB C) *
+L20736
+1111111111111111
+0101111101111111011111111011011111011111
+1111111111011101111111111111111111111111*  NOTE PT 2 of MC 37(LAB C) *
+L21120
+1111111111111111
+0111111111111111011111110111110111011111
+1111111111111111111111111111111111111111*  NOTE PT 5 of MC 36(LAB C) *
+L21216
+1111111111111111
+1111111111111111111111111111111111111101
+1111110111111111111111111111111111111111*  NOTE PT 4 of MC 36(LAB C) *
+L21312
+1111111111111111
+1111111111111111101111111111111111111111
+1111111111111110111111111111111111111111*  NOTE PT 3 of MC 36(LAB C) *
+L21408
+1111111111111111
+1111111111111111101111111111111111101111
+1111111111111111111111111111111111111111*  NOTE PT 2 of MC 36(LAB C) *
+L21504
+1111111111111111
+1111111111111111011111111111111111011111
+1111111111111101111111111111111111111111*  NOTE PT 1 of MC 36(LAB C) *
+L21600
+1111111111111111
+1111111101111111111111110111110111111111
+1111111111111111111111111111111111111111*  NOTE PT 1 of MC 35(LAB C) *
+L21696
+1111111111111111
+0111111111111111111111110111110111111111
+1111111111011111111111111111111111111111*  NOTE PT 2 of MC 35(LAB C) *
+L21792
+1111111111111111
+0111111111111111111111110111010111111111
+1111111111111111111111111111111111111111*  NOTE PT 3 of MC 35(LAB C) *
+L21888
+1111111111111111
+0111111111111111011111110111110111111111
+1111111111111101111111111111111111111111*  NOTE PT 4 of MC 35(LAB C) *
+L21984
+1111111111111111
+1101111111111111111111110111110111111111
+1111111111111111111111111111111111111111*  NOTE PT 5 of MC 35(LAB C) *
+L22080
+1111111111111111
+1111111101111111111111110111110111111111
+1111111111111111111111111111111111111111*  NOTE PT 5 of MC 34(LAB C) *
+L22176
+1111111111111111
+1111111111111111111111111111111111111101
+1111110111111111111111111111111111111111*  NOTE PT 4 of MC 34(LAB C) *
+L22272
+1111111111111111
+0101111111111111011111111111011011011111
+1111111111011101111111111111111111111111*  NOTE PT 3 of MC 34(LAB C) *
+L22368
+1111111111111111
+0101111111111111011111111011011111011111
+1111111111011101111111111111111111111111*  NOTE PT 2 of MC 34(LAB C) *
+L22464
+1111111111111111
+1111111111111111011111111111111111011111
+1111111111011101111111111111111111111111*  NOTE PT 1 of MC 34(LAB C) *
+L22560
+1011111111101111
+1111111111111111111111111111011111111111
+1111111111111111111111111111111111111111*  NOTE PT 1 of MC 33(LAB C) *
+L22656
+1111111111111111
+1010111110111111011111111111101111011111
+1111111111011101111111111111111111111111*  NOTE PT 2 of MC 33(LAB C) *
+L22752
+1011111111111111
+1010111110111111111111111111011111111111
+1111111111111111111111111111111111111111*  NOTE PT 3 of MC 33(LAB C) *
+L22848
+1111111111111111
+1111111111111111111111111111111111111101
+1111110111111111111111111111111111111111*  NOTE PT 4 of MC 33(LAB C) *
+L22944
+1111111111101111
+1111111111111111011111111111101111011111
+1111111111011101111111111111111111111111*  NOTE PT 5 of MC 33(LAB C) *
+L28416
+1111111111111111
+1111111111110111111111111101111111111111
+1111111111111111111111111111111111111111*  NOTE PT 2 of MC 53(LAB D) *
+L28512
+1111111111111111
+1111111110111011111111111111111101111111
+1111111111111111111111111111111111111111*  NOTE PT 3 of MC 53(LAB D) *
+L28608
+1111111111111111
+1111111101111011111101111111111111111111
+1111111111111111111111111111111111111111*  NOTE PT 4 of MC 53(LAB D) *
+L28896
+1111111111111111
+1111111101111011111111111111111111111111
+1111111101111111111111111111111111111111*  NOTE PT 4 of MC 52(LAB D) *
+L28992
+1111111111111111
+1111111110111011111101111111111111111111
+1111111111111111111111111111111111111111*  NOTE PT 3 of MC 52(LAB D) *
+L29088
+1111111111111111
+1111111111110111111111111111111111111111
+1111111111111111111111011111111111111111*  NOTE PT 2 of MC 52(LAB D) *
+L29376
+1111111111111111
+1111111111110111111111011111111111111111
+1111111111111111111111111111111111111111*  NOTE PT 2 of MC 51(LAB D) *
+L29472
+1111111111111111
+1111111110111011111111111111111111110111
+1111111111111111111111111111111111111111*  NOTE PT 3 of MC 51(LAB D) *
+L29568
+1111111111111111
+1111111101111011111111111111111101111111
+1111111111111111111111111111111111111111*  NOTE PT 4 of MC 51(LAB D) *
+L29856
+1111111111111111
+1111111101111011111111111111111111110111
+1111111111111111111111111111111111111111*  NOTE PT 4 of MC 50(LAB D) *
+L29952
+1111111111111111
+1111111110111011011111111111111111111111
+1111111111111111111111111111111111111111*  NOTE PT 3 of MC 50(LAB D) *
+L30048
+1111111111111111
+1111111111110111111111111111111111111111
+1111111111111111111111110111111111111111*  NOTE PT 2 of MC 50(LAB D) *
 L30336
 1111111111111111
-1101111111101111111111111111111111111111
-1011111011111111111111111111111111111111*  NOTE PT 2 of MC 49(LAB D) *
+1111111111110111111111111111111111111111
+1111111111111111111101111111111111111111*  NOTE PT 2 of MC 49(LAB D) *
 L30432
 1111111111111111
-1111111111111111111111111111011111111111
-1111110111111111111111111111111111111111*  NOTE PT 3 of MC 49(LAB D) *
+1111111110111011111111111111111111111111
+1111111111111111111111111111111111111111*  NOTE PT 3 of MC 49(LAB D) *
 L30528
 1111111111111111
-1111111111111111111111111111011111111111
-0111111111111111111111111111111111111111*  NOTE PT 4 of MC 49(LAB D) *
-L30624
-1111111111111111
-1111111111011111111111111111011111111111
-1111111111111111111111111111111111111111*  NOTE PT 5 of MC 49(LAB D) *
+1111111111111011011111111111111111111111
+1111111111111111111111111111111111111111*  NOTE PT 4 of MC 49(LAB D) *
 L30720
-1111111111111111
-1111111111110111111111111110111110011111
-1111111111111011111111111111111111111111*  NOTE PT 5 of MC 128(LAB H) *
+1111011111111111
+1111111111111111101111111111111110111111
+1111111111111111111110111111111111111111*  NOTE PT 5 of MC 128(LAB H) *
 L30816
-1111111111111111
-1111111111110111111111111110111110011111
-1111111111101111111111111111111111111111*  NOTE PT 4 of MC 128(LAB H) *
+1111101111111111
+1111111111111111111111111111111101111111
+1111111111111111111101111111111111111111*  NOTE PT 4 of MC 128(LAB H) *
 L30912
 1111111111111111
-1111111111110111111111111101111110101111
-1111111111110111111111111111111111111111*  NOTE PT 3 of MC 128(LAB H) *
+1111111111111111111111111111111101011111
+1111111111011111111101111111111111111111*  NOTE PT 3 of MC 128(LAB H) *
 L31008
 1111111111111111
-1111111111110111111111111101111110101111
-1111111111011111111111111111111111111111*  NOTE PT 2 of MC 128(LAB H) *
+1111111111111111011111111111111111111111
+1111111111111111111101111111111111111111*  NOTE PT 2 of MC 128(LAB H) *
+L31104
+1111111111111111
+1111111111111111111111111111111111111111
+1111111111111111111111110111111111111111*  NOTE PT 1 of MC 128(LAB H) *
+L31680
+1111111111111111
+1011111101110111111011111101111111111111
+1101110110110111111111111111111111111111*  NOTE PT 5 of MC 126(LAB H) *
+L31776
+1111111111111111
+1010111101110111111111111101111111111111
+1101110110110111111111111111111111111111*  NOTE PT 4 of MC 126(LAB H) *
 L31872
 1111111111111111
-1111111111111111111111101111011011111111
-1101101101111111011110011110111111111111*  NOTE PT 3 of MC 126(LAB H) *
+1011111101110111110111111101111111111111
+1101110110111011111111111111111111111111*  NOTE PT 3 of MC 126(LAB H) *
 L31968
 1111111111111111
-1111111111111111111111101111011011111111
-1101101101111111101101011110111111111111*  NOTE PT 2 of MC 126(LAB H) *
+1001111101110111111111111101111111111111
+1101110110111011111111111111111111111111*  NOTE PT 2 of MC 126(LAB H) *
 L32256
 1111111111111111
-1111111111111110111111111111111111111111
-1111111111111111111111111111011111111111*  NOTE PT 2 of MC 125(LAB H) *
+1111111111111111111111101111111111111111
+1111111111111111111111101111111111111111*  NOTE PT 2 of MC 125(LAB H) *
 L33216
 1111111111111111
-1111111111111111101110111111111111111111
+1111110111111110111111111111111111111111
 1111111111111111111111111111111111111111*  NOTE PT 2 of MC 123(LAB H) *
-L33312
-1111111111111111
-1111111110101111111011111111111111111111
-1111111111111111111111111011011111111111*  NOTE PT 3 of MC 123(LAB H) *
 L34176
 1111111111111111
-1111111111111111101101111111111111111111
-1111111111111111111111111111111111111111*  NOTE PT 2 of MC 121(LAB H) *
+1111111111111110111111111111111111111111
+1111111111111111111011111111111111111111*  NOTE PT 2 of MC 121(LAB H) *
 L34272
 1111111111111111
-1111111101101111111011111111111111111111
-1111111111111111111111111011011111111111*  NOTE PT 3 of MC 121(LAB H) *
+1111111011111111111111111111111111111111
+1111111111111111111011111111111111111111*  NOTE PT 3 of MC 121(LAB H) *
+L34560
+1111111111111111
+1111111011111011111111111110111111110111
+1110111110111111111111111111111011111111*  NOTE PT 5 of MC 120(LAB H) *
+L34656
+1111111111111111
+1011111011111111111111111111111111110111
+1110111110111111111111111111111011111111*  NOTE PT 4 of MC 120(LAB H) *
+L34752
+1111111111111111
+1111111010111111111111111111111111110111
+1111111110111111111111111111111011111111*  NOTE PT 3 of MC 120(LAB H) *
 L34848
 1111111111111111
-1111111111101111111011111111111111111111
-1111111111111111111111111011011111111111*  NOTE PT 2 of MC 120(LAB H) *
-L35616
+1111111011111111111111111111111111110111
+1111111011111111111111111111111011111111*  NOTE PT 2 of MC 120(LAB H) *
+L34944
 1111111111111111
-1111111111111111111111111011111111111111
-1111111111111111111111111111111111111111*  NOTE PT 4 of MC 118(LAB H) *
-L35712
-1111111111111111
-1111111111101111111011111111111111111111
-1111111111111111111111111011111111111111*  NOTE PT 3 of MC 118(LAB H) *
+1111111011111011111111111111111111110111
+1110111110111011111111111111111011111111*  NOTE PT 1 of MC 120(LAB H) *
 L35808
 1111111111111111
-1111111011111111111111111111111111111110
+1111110111111111111111111111111111111110
 1111111111111111111111111111111111111111*  NOTE PT 2 of MC 118(LAB H) *
+L35904
+1111111111111111
+1111111111111111111111111011111111111111
+1111111111111111101111111110111111111111*  NOTE PT 1 of MC 118(LAB H) *
+L36000
+1111111111111111
+1111111111111111111111110111111111111111
+1111111111111111011111111101111111111111*  NOTE PT 1 of MC 117(LAB H) *
 L36096
 1111111111111111
-1111111111111111101111111111111111110111
+1111010111111111111111111111111111111111
 1111111111111111111111111111111111111111*  NOTE PT 2 of MC 117(LAB H) *
 L36192
 1111111111111111
-1111111111101111011011111111111111111111
-1111111111111111111111011011011111111111*  NOTE PT 3 of MC 117(LAB H) *
+1111111111111111111111111111111111111111
+1111110111111111110111111111111111111111*  NOTE PT 3 of MC 117(LAB H) *
+L36960
+1111111111111111
+1111111111111111111101111111011111111111
+1111111111111111111111111111011111111111*  NOTE PT 1 of MC 115(LAB H) *
 L37056
 1111111111111111
-1111011111111111101111111111111111111111
-1111111111111111111111111111111111111111*  NOTE PT 2 of MC 115(LAB H) *
+1111110111111111111101111111011111111111
+1111111111111110111111111111011111111111*  NOTE PT 2 of MC 115(LAB H) *
 L37152
 1111111111111111
-1111111111101111011011111111011111111111
-1111111111111111111111111011011111111111*  NOTE PT 3 of MC 115(LAB H) *
+1111111111111111111111111111111111111111
+1111111101111111110111111111111111111111*  NOTE PT 3 of MC 115(LAB H) *
+L37248
+1101111111111111
+1111110111111111111111111111111011111111
+1011111111111101111111111111111111111111*  NOTE PT 4 of MC 115(LAB H) *
+L37344
+0111111111111111
+1111110111111111111111111111111111111111
+1111111111111110111111111111111111111111*  NOTE PT 5 of MC 115(LAB H) *
+L37440
+1111111111111111
+1111111011111011111111111110111111110101
+1110111110111111111111111111111011111111*  NOTE PT 5 of MC 114(LAB H) *
+L37536
+1111111111111111
+1011111011111111111111111111111111110101
+1110111110111111111111111111111011111111*  NOTE PT 4 of MC 114(LAB H) *
+L37632
+1111111111111111
+1111111010111111111111111111111111110101
+1111111110111111111111111111111011111111*  NOTE PT 3 of MC 114(LAB H) *
+L37728
+1111111111111111
+1111111011111111111111111111111111110101
+1111111011111111111111111111111011111111*  NOTE PT 2 of MC 114(LAB H) *
+L37824
+1111111111111111
+1111111011111011111111111111111111110101
+1110111110111011111111111111111011111111*  NOTE PT 1 of MC 114(LAB H) *
+L37920
+1111111111111111
+1111111111111111111111111111111011111111
+1011111111111111111111111111111111111111*  NOTE PT 1 of MC 113(LAB H) *
 L38016
 1111111111111111
-0111111111111111101111111111111111111111
-1111111111111111111111111111111111111111*  NOTE PT 2 of MC 113(LAB H) *
+1111110111111111111111111111110111111111
+0111111111111111111111111111111111111111*  NOTE PT 2 of MC 113(LAB H) *
 L38112
 1111111111111111
-1111111111101111011011111111111111111111
-1111011111111111111111111011011111111111*  NOTE PT 3 of MC 113(LAB H) *
-L38400
+1111110111111111111101111111010111111111
+1111111111111111111111111111011111111111*  NOTE PT 3 of MC 113(LAB H) *
+L38208
 1111111111111111
-1110111111111111111111111111111111111111
-1011111111111111111111111101111111111111*  NOTE PT 5 of MC 112(LAB G) *
+1111111101111111111111111111111111111111
+1111111111111111110111111111111111111111*  NOTE PT 4 of MC 113(LAB H) *
+L38304
+1101111111111111
+1111110111111111111111111111111011111111
+1011111111111111111111111111111111111111*  NOTE PT 5 of MC 113(LAB H) *
+L38400
+1011111111111111
+1111111111111111110111111111111111111111
+1111111111111111111111111111111111111111*  NOTE PT 5 of MC 112(LAB G) *
 L38496
-0110001111111111
-1111111111111111111111111111111110111111
-1111111111111111011111111111111111111111*  NOTE PT 4 of MC 112(LAB G) *
+1111111111111111
+1111110111111111110111111111111111011111
+1111111111111111111111111111111111111111*  NOTE PT 4 of MC 112(LAB G) *
 L38592
 1111111111111111
-1110111111111111111111111111111111111111
-1111111111111111111110111101111111111111*  NOTE PT 3 of MC 112(LAB G) *
+1111011111111111111111111111111111111111
+1111110111111111111111111111111111111111*  NOTE PT 3 of MC 112(LAB G) *
 L38688
 1111111111111111
-1110111111111111111111111111111111111111
-0111111101111111111101111110111111111111*  NOTE PT 2 of MC 112(LAB G) *
+1101111111111111111111111111111111111111
+1111010111111111111111111111111111111111*  NOTE PT 2 of MC 112(LAB G) *
 L38784
-1111111111111111
-1110111111111111111111111111111111111111
-1111111110111111111111111101111111111111*  NOTE PT 1 of MC 112(LAB G) *
+0111111111111111
+1011111110111111101011111111111111111111
+1011111110111111111110111110101111111111*  NOTE PT 1 of MC 112(LAB G) *
 L38976
 1111111111111111
-1011111011111111111111101111111011111111
-0111101101111111111101111110111111111111*  NOTE PT 2 of MC 111(LAB G) *
+1111111111110111111111111111111111111111
+1111010111010111111111111111111111111111*  NOTE PT 2 of MC 111(LAB G) *
 L39072
 1111111111111111
-1011111011111111111111101111111011111111
-1111101110111111111111111101111111111111*  NOTE PT 3 of MC 111(LAB G) *
-L39168
+1111111111110111111111111111111111111111
+1111010111111111111111110111111111111111*  NOTE PT 3 of MC 111(LAB G) *
+L39360
 1111111111111111
-1011111011111111111111101111111011111111
-1011101111111111111110111101111111111111*  NOTE PT 4 of MC 111(LAB G) *
+1111111111111111111111110111011101111111
+1111111111111111011111011111111111111111*  NOTE PT 5 of MC 110(LAB G) *
+L39456
+1111111111111111
+1111111111111111111111111011111111111111
+1111111111111111101111011111111111111111*  NOTE PT 4 of MC 110(LAB G) *
 L39552
 1111111111111111
-1111110111111111011011111111011111111110
-1111111111111111111111111011111111111111*  NOTE PT 3 of MC 110(LAB G) *
+1111111111111111111111111011111110111111
+1111111111111111111111011111111111111111*  NOTE PT 3 of MC 110(LAB G) *
 L39648
 1111111111111111
-1111111111110111101111111111111111111111
-1111111111111111111111111111111111111111*  NOTE PT 2 of MC 110(LAB G) *
-L39936
-1111111111111111
-1111111111111111101101111111111111111111
-1111111111111111111111111111111111111111*  NOTE PT 2 of MC 109(LAB G) *
-L40032
-1111111111111111
-1111111111111111011011111111010111111110
-1111111111111111111111111011111111111111*  NOTE PT 3 of MC 109(LAB G) *
-L40416
-0110001111111111
-1111111111111111111111111111111110111111
-1111111111111111011111111111111111111111*  NOTE PT 4 of MC 108(LAB G) *
-L40512
+1111111111111111111111111011101111111111
+1111111111111111111111011111111111111111*  NOTE PT 2 of MC 110(LAB G) *
+L39744
 1111111111111111
 1101111111111111111111011111111111111111
-1111111111111111111111111111111111111111*  NOTE PT 3 of MC 108(LAB G) *
+1111111111111111111111111111111111111111*  NOTE PT 1 of MC 110(LAB G) *
+L39936
+1111111111111111
+1111111111111111111111111111011110111111
+1111111111111111111111011111111111111111*  NOTE PT 2 of MC 109(LAB G) *
+L40032
+1111111111111111
+1111111111111111111111111111011111111111
+1111111111111111101111011111111111111111*  NOTE PT 3 of MC 109(LAB G) *
+L40128
+1111111111111111
+1111111111111111111111111111101101111111
+1111111111111111011111011111111111111111*  NOTE PT 4 of MC 109(LAB G) *
+L40224
+1111111111111111
+1111111111110111111111011111111111111111
+1111111111111111111111111111111111111111*  NOTE PT 5 of MC 109(LAB G) *
+L40320
+1111111111111111
+1111111111111111110111111111111111111111
+0111111111111111111111111111111111111111*  NOTE PT 5 of MC 108(LAB G) *
+L40416
+1111111111111111
+1111111101111111010111111111111111111111
+1111111111111111111111111111111111111111*  NOTE PT 4 of MC 108(LAB G) *
+L40512
+1111111111111111
+1111111101111111110111111111111111111111
+1111111101111111111111111111111111111111*  NOTE PT 3 of MC 108(LAB G) *
 L40608
 1111111111111111
-0110110111111111111111111111110111111111
-0111011101111111111101111101111111111111*  NOTE PT 2 of MC 108(LAB G) *
+0111110101111111110111111111111111011111
+1111111111111111111101111101011111111111*  NOTE PT 2 of MC 108(LAB G) *
 L40896
 1111111111111111
-1111111111011111101111111111111111111111
-1111111111111111111111111111111111111111*  NOTE PT 2 of MC 107(LAB G) *
+1111111111111111111111111111111101111111
+1111111111111111101111011111111111111111*  NOTE PT 2 of MC 107(LAB G) *
 L40992
 1111111111111111
-1111111111111111011011111111011111111110
-1111111111111111111111111001111111111111*  NOTE PT 3 of MC 107(LAB G) *
+1111111111111111111111111111111110111111
+1111111111111111011111011111111111111111*  NOTE PT 3 of MC 107(LAB G) *
+L41088
+1111111111111111
+1111111111111111111111011111111111111111
+1111111111111111111111110111111111111111*  NOTE PT 4 of MC 107(LAB G) *
 L41280
 1111111111111111
-1001111011111111111111101111111011111111
-1011101111111111111110111111111111111111*  NOTE PT 5 of MC 106(LAB G) *
+1111111111111111111111111111111111111111
+0111111111111111111111111111111111111111*  NOTE PT 5 of MC 106(LAB G) *
 L41376
-0110001111111111
-1111111111111111111111111111111110111111
-1111111111111111011111111111111111111111*  NOTE PT 4 of MC 106(LAB G) *
+1111111111111111
+1111111101111111011111111111111111111111
+1111111111111111111111111111111111111111*  NOTE PT 4 of MC 106(LAB G) *
 L41472
 1111111111111111
-1001111011111111111111101111111011111111
-1111101110111111111111111111111111111111*  NOTE PT 3 of MC 106(LAB G) *
+1111111101111111111111111111111111111111
+1111111101111111111111111111111111111111*  NOTE PT 3 of MC 106(LAB G) *
 L41568
 1111111111111111
-1001111011111111111111101111111011111111
-1111101111111111111111111110111111111111*  NOTE PT 2 of MC 106(LAB G) *
-L41664
-1111111111111111
-0110110111111111111111011111110111111111
-0111011101111111111101111101111111111111*  NOTE PT 1 of MC 106(LAB G) *
+0111110101111111111111111111111111011111
+1111111111111111111101111101011111111111*  NOTE PT 2 of MC 106(LAB G) *
 L41856
 1111111111111111
-1111111111111111101111111111111111111111
-1111111111111111111111111111110111111111*  NOTE PT 2 of MC 105(LAB G) *
+1111111111111111111111111111111110111111
+1111111111111111111111011111111111111111*  NOTE PT 2 of MC 105(LAB G) *
 L41952
 1111111111111111
-1111111111111111011011111111011111111110
-1111111101111111111111111011111111111111*  NOTE PT 3 of MC 105(LAB G) *
+1111111111111111111111011111111111111111
+1111111111011111111111111111111111111111*  NOTE PT 3 of MC 105(LAB G) *
 L42432
 1111111111111111
-1111111111111111011011111111011111111110
-1111111111111111111101111011111111111111*  NOTE PT 3 of MC 104(LAB G) *
+1111111111111111111111011111111111111111
+1111111111110111111111111111111111111111*  NOTE PT 3 of MC 104(LAB G) *
 L42528
 1111111111111111
-1111111111111111101111111111111111111111
-1101111111111111111111111111111111111111*  NOTE PT 2 of MC 104(LAB G) *
-L42720
-1111111111111111
-1110111111111111111111111111111111111111
-1011111111111111111111111111111111111111*  NOTE PT 1 of MC 103(LAB G) *
+1111111111111111111111111111111111111111
+1111111111111111110111011111111111111111*  NOTE PT 2 of MC 104(LAB G) *
 L42816
 1111111111111111
-1011111011111111111111101111111011111111
-1011101111111111111111111110111111111111*  NOTE PT 2 of MC 103(LAB G) *
+0111110101111111011011111111111111011111
+1111111101111111111101111101011111111111*  NOTE PT 2 of MC 103(LAB G) *
 L42912
 1111111111111111
-1011111011111111111111101111111011111111
-1011101110111111111111111111111111111111*  NOTE PT 3 of MC 103(LAB G) *
-L43008
-0110001111111111
-1111111111111111111111111111111110111111
-1111111111111111011111111111111111111111*  NOTE PT 4 of MC 103(LAB G) *
-L43104
-1111111111111111
-1011111011111111111111101111111011111111
-1011101111111111111110111111111111111111*  NOTE PT 5 of MC 103(LAB G) *
+1111111111111111110111111111111111111111
+0111111111111111111111111111111111111111*  NOTE PT 3 of MC 103(LAB G) *
 L43392
 1111111111111111
-1111111111111111011011111111011111111110
-0111111111111111111111111011111111111111*  NOTE PT 3 of MC 102(LAB G) *
+1111111111111111111111011111111111111101
+1111111111111111111111111111111111111111*  NOTE PT 3 of MC 102(LAB G) *
 L43488
 1111111111111111
-1111111111111111101111111111111111111111
-1111111111011111111111111111111111111111*  NOTE PT 2 of MC 102(LAB G) *
-L43584
-1111111111111111
-1111111111111110111111111111111111111111
-1111111111111011111111101111111111111111*  NOTE PT 1 of MC 102(LAB G) *
-L43680
-1111111111111111
-1111111111111111111111111101111111111111
-1111111111111111111111011111111111111111*  NOTE PT 1 of MC 101(LAB G) *
+1111111111111111111111111111111111111111
+1111111111111111111111011111110111111111*  NOTE PT 2 of MC 102(LAB G) *
 L43776
 1111111111111111
-1111111111111111101111111111111111111111
-1111111111111111110111111111111111111111*  NOTE PT 2 of MC 101(LAB G) *
+1111111111111111111111111111111111111111
+1101111111111111111111011111111111111111*  NOTE PT 2 of MC 101(LAB G) *
 L43872
 1111111111111111
-1111111111111111011011111111011101111110
-1111111111111111111111111011111111111111*  NOTE PT 3 of MC 101(LAB G) *
+1111111111111111111111011111111111111111
+0111111111111111111111111111111111111111*  NOTE PT 3 of MC 101(LAB G) *
+L44160
+1111111111111111
+1111111111111111010111111111111111111111
+0111111111111111111111111111111111111111*  NOTE PT 5 of MC 100(LAB G) *
 L44256
-0110001111111111
-1111111111111111111111111111111110111111
-1111111111111111011111111111111111111111*  NOTE PT 4 of MC 100(LAB G) *
+1111111111111111
+1111111101111111010111111111111111111111
+1111111111111111111111111111111111111111*  NOTE PT 4 of MC 100(LAB G) *
 L44352
 1111111111111111
-1101111111111111111111111111111111111111
-1111011111111111111111111111111111111111*  NOTE PT 3 of MC 100(LAB G) *
+0111110110111111111111111111111111011111
+1011111111111111111101111101011111111111*  NOTE PT 3 of MC 100(LAB G) *
 L44448
 1111111111111111
-0110110111111111111111111111110111111111
-0111111101111111111101111101111111111111*  NOTE PT 2 of MC 100(LAB G) *
-L44544
-1111111111111111
-1111111111111101111111111111111111111111
-1111111111110111111111011111111111111111*  NOTE PT 1 of MC 100(LAB G) *
-L44640
-1111111111111111
-1111111111111111111111111111111111111111
-1111111101111111111111111101111111111111*  NOTE PT 1 of MC 99(LAB G) *
+0111110111111111111011111111111111011111
+1111111111111111111101111101011111111111*  NOTE PT 2 of MC 100(LAB G) *
 L44736
 1111111111111111
-1111111111111111101111111111111111111111
-1111111111111101111111111111111111111111*  NOTE PT 2 of MC 99(LAB G) *
+1111111111111111111111111111110111111111
+1111111111111111111111011111111111111111*  NOTE PT 2 of MC 99(LAB G) *
 L44832
 1111111111111111
-1111111111111111011011111111011111111110
-1111111111111111111111011011111111111111*  NOTE PT 3 of MC 99(LAB G) *
+1111111101111111111111011111111111111111
+1111111111111111111111111111111111111111*  NOTE PT 3 of MC 99(LAB G) *
 L45120
-1101111111111111
-1011111011111111111111101111111011111111
-1011101111111111111101111111111111111111*  NOTE PT 5 of MC 98(LAB G) *
+1111111111111111
+1111111111111111110111111111111111111111
+0111111101111111111111111111111111111111*  NOTE PT 5 of MC 98(LAB G) *
 L45216
-0110001111111111
-1111111111111111111111111111111110111111
-1111111111111111011111111111111111111111*  NOTE PT 4 of MC 98(LAB G) *
+1111111111111111
+1111111101111111110111111111111111111111
+1111111101111111111111111111111111111111*  NOTE PT 4 of MC 98(LAB G) *
 L45312
 1111111111111111
-1110111111111111111111111111111111111111
-0111111111111111111110111111111111111111*  NOTE PT 3 of MC 98(LAB G) *
+0111110110111111011111111111111111011111
+1011111111111111111101111101011111111111*  NOTE PT 3 of MC 98(LAB G) *
 L45408
 1111111111111111
-1110111111111111111111111111111111111111
-1011111111111111111101111111111111111111*  NOTE PT 2 of MC 98(LAB G) *
+0111110111111111011011111111111111011111
+1111111111111111111101111101011111111111*  NOTE PT 2 of MC 98(LAB G) *
 L45504
-1101111111111111
-1011111011111111111111101111111011111111
-0111101111111111111110111111111111111111*  NOTE PT 1 of MC 98(LAB G) *
+1111111111111111
+1011111110111111101111111111111111111111
+1011111110111111111110111110101111111111*  NOTE PT 1 of MC 98(LAB G) *
 L45600
 1111111111111111
-1111111111111111111111111110111111111111
-1111111111111111111111101111111111111111*  NOTE PT 1 of MC 97(LAB G) *
+1111110111111111111111111111111111011111
+1111111111111111111111111111111111111111*  NOTE PT 1 of MC 97(LAB G) *
 L45696
 1111111111111111
-1111111111111111101111110111111111111111
-1111111111111111111111111111111111111111*  NOTE PT 2 of MC 97(LAB G) *
+1111111111011111111111111111111111111111
+1111111111111111111111011111111111111111*  NOTE PT 2 of MC 97(LAB G) *
 L45792
 1111111111111111
-1111111111111111011011111101011111111110
-1111111111111111111111111011111111111111*  NOTE PT 3 of MC 97(LAB G) *
-L46368
-1111111111111111
-1111111111111111011111111111111111111111
-1111111111111111111111111111111111111111*  NOTE PT 2 of MC 96(LAB F) *
+1111111111111111111111011111111111111111
+1111111101111111111111111111111111111111*  NOTE PT 3 of MC 97(LAB G) *
 L47232
 1111111111111111
-1111111111101111011111111111111111111111
-1011111011011111111111111111011111111111*  NOTE PT 3 of MC 94(LAB F) *
+1111110111111111111111111111111111111111
+1111111111111111111111111111011111111111*  NOTE PT 3 of MC 94(LAB F) *
 L47328
 1111111111111111
-1111111111111111101111111111011111111111
-1111111111111111111111111111111111111111*  NOTE PT 2 of MC 94(LAB F) *
+1111111111111111111111111111111111111111
+1101111111111111111101111111111111111111*  NOTE PT 2 of MC 94(LAB F) *
 L47616
 1111111111111111
-0111111111111111101111111111111111111111
-1111111111111111111111111111111111111111*  NOTE PT 2 of MC 93(LAB F) *
+1111111111111111111111111111111111111111
+1101111111111111111111110111111111111111*  NOTE PT 2 of MC 93(LAB F) *
 L47712
 1111111111111111
-1111111111101111011111111111111111111111
-1011011011111111111111111111011111111111*  NOTE PT 3 of MC 93(LAB F) *
+1111110111111111111111111111111111111111
+0111111111111111111111111111111111111111*  NOTE PT 3 of MC 93(LAB F) *
 L48576
 1111111111111111
-1111111111111111101111111011111111111111
+1111110111111111111111110111111111111111
 1111111111111111111111111111111111111111*  NOTE PT 2 of MC 91(LAB F) *
 L48672
 1111111111111111
-1111111011111111101111111111111111111111
-1111111111111111111111111111111111111111*  NOTE PT 3 of MC 91(LAB F) *
-L48768
-1111111111111111
-1111111111101111011111011111111111111111
-1011111011111111111111111111011111111111*  NOTE PT 4 of MC 91(LAB F) *
+1111111111111111111101111111111111111111
+1101111111111111111111111111111111111111*  NOTE PT 3 of MC 91(LAB F) *
 L49536
 1111111111111111
-1111111011111111111111110111111101111101
-1111111111111111111111111111111111111111*  NOTE PT 2 of MC 89(LAB F) *
+1111111111111111111101111111111111111111
+1101111111111111111111011111111111111111*  NOTE PT 2 of MC 89(LAB F) *
 L49632
 1111111111111111
-1111110111111111111111110111111111111111
-1111111111111111111111011111111111111111*  NOTE PT 3 of MC 89(LAB F) *
-L50112
-1111111111111111
-1111110111111111111111110111111111111111
-1111111111111111111101111111111111111111*  NOTE PT 3 of MC 88(LAB F) *
-L50208
-1111111111111111
-1111111011111111111111110111111111111101
-1111111111110111111111111111111111111111*  NOTE PT 2 of MC 88(LAB F) *
-L51072
-1111111111111111
-1111110111111111111111110111111111111111
-1111111111111111011111111111111111111111*  NOTE PT 3 of MC 86(LAB F) *
-L51168
-1111111111111111
-1111111011111111111111110111111111111101
-1111111111111111111111111101111111111111*  NOTE PT 2 of MC 86(LAB F) *
-L51456
-1111111111111111
-1111111011111111111111110101111111111101
-1111111111111111111111111111111111111111*  NOTE PT 2 of MC 85(LAB F) *
-L51552
-1111111111111111
-1111110111111111111111110111111111011111
-1111111111111111111111111111111111111111*  NOTE PT 3 of MC 85(LAB F) *
-L51936
-1111111111111111
-1111011011111111111111111011111111111110
-1111111111111111110111111111111111111111*  NOTE PT 4 of MC 84(LAB F) *
-L52128
+1111111111111111111110111111111111111111
+1111111111110111111111111111111111111111*  NOTE PT 3 of MC 89(LAB F) *
+L49728
 1111111111111111
 1111111111111111111111111111111111111111
-1111111111111111111111110111111111111111*  NOTE PT 2 of MC 84(LAB F) *
+1110111111110111111111111111111111111111*  NOTE PT 4 of MC 89(LAB F) *
+L50016
+1111111111111111
+1111111111111111111111111111111101111111
+1110111111111111111111111111111111111111*  NOTE PT 4 of MC 88(LAB F) *
+L50112
+1111111111111111
+1111111111111111111110111111111101111111
+1111111111111111111111111111111111111111*  NOTE PT 3 of MC 88(LAB F) *
+L50208
+1111111111111111
+1111111111111111111101111111111111111111
+1101111111111111111111111101111111111111*  NOTE PT 2 of MC 88(LAB F) *
+L50976
+1111111111111111
+1111111111110111111111111111111111111111
+1110111111111111111111111111111111111111*  NOTE PT 4 of MC 86(LAB F) *
+L51072
+1111111111111111
+1111111111110111111110111111111111111111
+1111111111111111111111111111111111111111*  NOTE PT 3 of MC 86(LAB F) *
+L51168
+1111111111111111
+1111111111111111110101111111111111111111
+1101111111111111111111111111111111111111*  NOTE PT 2 of MC 86(LAB F) *
+L51456
+1111111111111111
+1111111111111111111101111101111111111111
+1101111111111111111111111111111111111111*  NOTE PT 2 of MC 85(LAB F) *
+L51552
+1111111111111111
+1111111111111111111110111111110111111111
+1111111111111111111111111111111111111111*  NOTE PT 3 of MC 85(LAB F) *
+L51648
+1111111111111111
+1111111111111111111111111111110111111111
+1110111111111111111111111111111111111111*  NOTE PT 4 of MC 85(LAB F) *
 L52416
 1111111111111111
-1111111011111111111111110111111111110101
-1111111111111111111111111111111111111111*  NOTE PT 2 of MC 83(LAB F) *
+1111111111111101111101111111111111111111
+1101111111111111111111111111111111111111*  NOTE PT 2 of MC 83(LAB F) *
 L52512
 1111111111111111
-1111110111111111111101110111111111111111
+1111111111111111111110011111111111111111
 1111111111111111111111111111111111111111*  NOTE PT 3 of MC 83(LAB F) *
+L52608
+1111111111111111
+1111111111111111111111011111111111111111
+1110111111111111111111111111111111111111*  NOTE PT 4 of MC 83(LAB F) *
 L53376
 1111111111111111
-1111111011111111111111110111111111111101
-1111111111111101111111111111111111111111*  NOTE PT 2 of MC 81(LAB F) *
+1111111111111111111101111111011111111111
+1101111111111111111111111111111111111111*  NOTE PT 2 of MC 81(LAB F) *
 L53472
 1111111111111111
-1111110101111111111111110111111111111111
+1111111111111111111110111111111111011111
 1111111111111111111111111111111111111111*  NOTE PT 3 of MC 81(LAB F) *
+L53568
+1111111111111111
+1111111111111111111111111111111111011111
+1110111111111111111111111111111111111111*  NOTE PT 4 of MC 81(LAB F) *
+L53856
+1111111111111111
+1111111111111111110111111111111111111111
+1110111111111111111111111111111111111111*  NOTE PT 4 of MC 80(LAB E) *
 L53952
 1111111111111111
-1111110111111111011111110111111111111111
+1011111111111111110111111111111111111111
 1111111111111111111111111111111111111111*  NOTE PT 3 of MC 80(LAB E) *
 L54048
 1111111111111111
-1111111011111111111111110111111111111101
-1111111111111111111111111111110111111111*  NOTE PT 2 of MC 80(LAB E) *
-L54240
-1111011111111111
-1111111111111111111111110111111111111110
-1011111111111111111111111111111111111111*  NOTE PT 1 of MC 79(LAB E) *
-L54336
+0111111111111111111101111111111111111111
+1101111111111111111111111111111111111111*  NOTE PT 2 of MC 80(LAB E) *
+L54144
 1111111111111111
-1111101111111111111111111011111111111101
-1111111111111111111111111111111111111111*  NOTE PT 2 of MC 79(LAB E) *
-L54432
+1111111111111111111111111111111110111111
+1111111111111101111111111111111111111111*  NOTE PT 1 of MC 80(LAB E) *
+L54816
 1111111111111111
-0101111010111001111110111001111101110110
-1111101111111111011111111101011111111111*  NOTE PT 3 of MC 79(LAB E) *
-L54528
-1111110111111111
-1111110111111111111111111111111111111111
-1111111111111111111111111111111111111111*  NOTE PT 4 of MC 79(LAB E) *
-L54624
-1111101111111111
-1111111111111111111111110111111111111101
-1111111111111111111111111111111111111111*  NOTE PT 5 of MC 79(LAB E) *
+1111111111111111111111111111110111111111
+1110111111111111111111111111111111111111*  NOTE PT 4 of MC 78(LAB E) *
 L54912
 1111111111111111
-1111110111111111111111110111110111111111
+1011111111111111111111111111110111111111
 1111111111111111111111111111111111111111*  NOTE PT 3 of MC 78(LAB E) *
 L55008
 1111111111111111
-1111111011111111111111110111111111111101
-1111111111111111111111110111111111111111*  NOTE PT 2 of MC 78(LAB E) *
-L55296
-1101111111111111
-1111111011111111111111010111111111111101
-1111111111111111111111111111111111111111*  NOTE PT 2 of MC 77(LAB E) *
-L55392
-1111111111111111
-1111111111111111111111010111111111101110
-1011111111111111111111111111111111111111*  NOTE PT 3 of MC 77(LAB E) *
-L55488
-1111111111111111
-1111110111111111111111111011111111111111
-1111111111111111111111111111111111111111*  NOTE PT 4 of MC 77(LAB E) *
-L55584
-1111111111111111
-1111110111101111111111111111111111111111
-1011111011111111111111111111111111111111*  NOTE PT 5 of MC 77(LAB E) *
-L55680
-1011111111111111
-1111110111111111111111010111111111111111
-1111111111111111111111111111111111111111*  NOTE PT 5 of MC 76(LAB E) *
-L55776
-1111111111111111
-1111111011110111111111011011111111111110
-1111111101111111110111111111111111111111*  NOTE PT 4 of MC 76(LAB E) *
-L55872
-1111111111111111
-1111110111110111111111010111111111111111
-1111111111111111111111111111111111111111*  NOTE PT 3 of MC 76(LAB E) *
-L55968
-1111111111111111
-1111111011111011111111101011111111111110
-1111111101111111110111111111111111111111*  NOTE PT 2 of MC 76(LAB E) *
-L56064
-1011111111111111
-1111111011111111111111011011111111111110
-1111111101111111110111111111111111111111*  NOTE PT 1 of MC 76(LAB E) *
-L56640
-1011111111111111
-1111111011111111111111111011111111011110
-1111111101111111110111111111111111111111*  NOTE PT 5 of MC 74(LAB E) *
-L56736
-1111111111111111
-1111111011111111111111110111111111011101
-1111111111110111111111111111111111111111*  NOTE PT 4 of MC 74(LAB E) *
-L56832
-1111111111111111
-1111111011111111111111111011111111011110
-1111111101110111110111111111111111111111*  NOTE PT 3 of MC 74(LAB E) *
-L56928
-1111111111111111
-1111111011111111111111111011111111101110
-1111111101111011110111111111111111111111*  NOTE PT 2 of MC 74(LAB E) *
-L57024
-1011111111111111
-1111111011111111111111110111111111011101
-1111111111111111111111111111111111111111*  NOTE PT 1 of MC 74(LAB E) *
-L57216
+0111111111111111111111111111111111110111
+1101111111111111111111111111111111111111*  NOTE PT 2 of MC 78(LAB E) *
+L55104
 1111111111111111
 1111111111111111111111111111111101111111
+1111111111111110111111111111111111111111*  NOTE PT 1 of MC 78(LAB E) *
+L56064
+1111111111111111
+1111111111111111111111111111011111111111
+0111111111111111011111111111111111111111*  NOTE PT 1 of MC 76(LAB E) *
+L56160
+0000010100111010
+1011011111101111111111111110111111111110
+1111110110111011111101101011111111111111*  NOTE PT 1 of MC 75(LAB E) *
+L56256
+0000010101111010
+1011011010111011111111111110111111111110
+1111110110111111111101101011111011111111*  NOTE PT 2 of MC 75(LAB E) *
+L56352
+0000010101111010
+1011011011101111111111111110111111111110
+1111110110111011111101101011111011111111*  NOTE PT 3 of MC 75(LAB E) *
+L56448
+1111111111111111
+1111111111111111111111111111111111111110
+1101111111111111111111111111111111111111*  NOTE PT 4 of MC 75(LAB E) *
+L56544
+0000010100111010
+1011011110111011111111111110111111111110
+1111110110111111111101101011111111111111*  NOTE PT 5 of MC 75(LAB E) *
+L57024
+1111111111111111
+1111111111111101111111111111111111111111
+1111111111111111111111111111011111111111*  NOTE PT 1 of MC 74(LAB E) *
+L57120
+1111101111111111
+1111111111111111111111110111011111011111
+1111111111111111110111111101111111111111*  NOTE PT 1 of MC 73(LAB E) *
+L57216
+1111111111111111
+1111111111111111111111111111111111111111
 1111111111111111111111111111111111111111*  NOTE PT 2 of MC 73(LAB E) *
 L57312
 1111111111111111
 1111111111111111111111111111111111111111
-1111111111111111011111111111111111111111*  NOTE PT 3 of MC 73(LAB E) *
+1111111111111111111111110111111111111111*  NOTE PT 3 of MC 73(LAB E) *
 L57408
-1111111111111111
-1111111011111111111111111011111111111110
-1111111101111111110111111111111111111111*  NOTE PT 4 of MC 73(LAB E) *
-L57600
-1011111111111111
-1111111111111111111111111011111111111111
-0111111111111111111111111111111111111111*  NOTE PT 5 of MC 72(LAB E) *
-L57696
-1001111111111111
-1111111111111111111111110111111111111101
-1111111111111111111111111111111111111111*  NOTE PT 4 of MC 72(LAB E) *
-L57792
-1011111111111111
-1111111011111111111111101111111111101110
-1111111111111111111111111111111111111111*  NOTE PT 3 of MC 72(LAB E) *
-L57888
-1001111111111111
-1111111111111111111111100111111111101111
-1111111111111111111111111111111111111111*  NOTE PT 2 of MC 72(LAB E) *
+0000010101111010
+0111011111111111111111111110111111111110
+1101110110111011111101101011111111111111*  NOTE PT 4 of MC 73(LAB E) *
 L57984
-1011111111111111
-1111111011111111111111111011111111111111
+1111111111111111
+1111111110111011111111111111111111111111
 1111111111111111111111111111111111111111*  NOTE PT 1 of MC 72(LAB E) *
 L58080
 1111111111111111
-1111111111111111111111111011111111111111
-0111111111111111111111111111111111111111*  NOTE PT 1 of MC 71(LAB E) *
+1110111111111111011111111111111111111111
+1111111111111111111111111111111111111111*  NOTE PT 1 of MC 71(LAB E) *
 L58176
 1111111111111111
-1111111111111111111111111111111101111111
-1111111111111111011111111111111111111111*  NOTE PT 2 of MC 71(LAB E) *
+1111110111111101111111111111111111111110
+1110111111111111111111111111010111111111*  NOTE PT 2 of MC 71(LAB E) *
 L58272
 1111111111111111
-1111111111111111111111111111111111110111
+0111111111111111111111111111111111111110
 1111111111111111111111111111111111111111*  NOTE PT 3 of MC 71(LAB E) *
 L58368
-1111111111111111
-1111111011111111111111111011111111111110
-1111111101111111110111111111111111111111*  NOTE PT 4 of MC 71(LAB E) *
-L58656
-1111111111111111
-1111011111111111111111110111111111111110
-1111111111111111111111111111111111111111*  NOTE PT 4 of MC 70(LAB E) *
-L58752
-1111111111111111
-1111101111110111111111111111111111111101
-1111111111110111111111111111111111111111*  NOTE PT 3 of MC 70(LAB E) *
-L58848
-1111111111111111
-1111100111110111111111111011111111111111
-1111111111110111111111111111111111111111*  NOTE PT 2 of MC 70(LAB E) *
+0000010001111010
+1111011011101111111111111110111111111110
+1110110110111011111101101011111011111111*  NOTE PT 4 of MC 71(LAB E) *
+L58464
+0000010000111010
+1111011111101111111111111110111111111110
+1110110110111011111101101011111111111111*  NOTE PT 5 of MC 71(LAB E) *
 L58944
-1101111111111111
-1111111111111111111111011111111111111111
-1111111111111111111111111111111111111111*  NOTE PT 1 of MC 70(LAB E) *
+1111111111111111
+1111111111111111111111101111111111111111
+1011111111111111101111111111111111111111*  NOTE PT 1 of MC 70(LAB E) *
 L59040
 1111111111111111
-1111111111111111111111101111111111101111
+1101111111111111101111111111111111111111
 1111111111111111111111111111111111111111*  NOTE PT 1 of MC 69(LAB E) *
-L59136
-1111111111111111
-1111111111111111111111111111111101110111
-1111111111111111011111111111111111111111*  NOTE PT 2 of MC 69(LAB E) *
-L59232
-1111111111111111
-1011111111111111111111111111111111111111
-1111111111111111111111111111111111111111*  NOTE PT 3 of MC 69(LAB E) *
-L59328
-1111111111111111
-1111111011111111111111111011111111111110
-1111111101111111110111111111111111111111*  NOTE PT 4 of MC 69(LAB E) *
-L59520
-1111111111111111
-1111111111111111111111111111111111111111
-1111111111111111111111111101111111111111*  NOTE PT 5 of MC 68(LAB E) *
-L59616
-1111111111111111
-1111111011111111111111111011111111111110
-1111111101111111110111111111111111111111*  NOTE PT 4 of MC 68(LAB E) *
-L59712
-1111111111111111
-1111111111111111111111111111111101110111
-1111111111111111011111111111111111111111*  NOTE PT 3 of MC 68(LAB E) *
-L59808
-1111111111111111
-1111111111111111111111111111111111111111
-1111111111111101111111111111111111111111*  NOTE PT 2 of MC 68(LAB E) *
 L59904
-1111111111111111
-0111111111111111111111111111111111111111
-1111111111111111111111111111111111111111*  NOTE PT 1 of MC 68(LAB E) *
+1111111111101111
+1111111111111111111111111011111111101111
+1111111111111111111111111110111111111111*  NOTE PT 1 of MC 68(LAB E) *
 L60000
 1111111111111111
-1111111111101111111111111111111111111111
-1011111011111111111111111111111111111111*  NOTE PT 1 of MC 67(LAB E) *
-L60096
+1111111111111111111111111111111111111111
+1111101111011111111111111111111111111111*  NOTE PT 1 of MC 67(LAB E) *
+L60576
+0000010101111010
+1011011111111011111111111110111111111110
+1101110110111111111101101011111111111111*  NOTE PT 4 of MC 66(LAB E) *
+L60672
 1111111111111111
 1111111111111111111111111111111111111111
-1111111111111111111111111110111111111111*  NOTE PT 2 of MC 67(LAB E) *
-L60192
-1111111111111111
-1111111111111111111111111111111101110111
-1111111111111111011111111111111111111111*  NOTE PT 3 of MC 67(LAB E) *
-L60288
-1111111111111111
-1111111011111111111111111011111111111110
-1111111101111111110111111111111111111111*  NOTE PT 4 of MC 67(LAB E) *
-L60384
-1111111111111111
-0111111111111111111111111111111111111111
-1111111111111111111111111111111111111111*  NOTE PT 5 of MC 67(LAB E) *
-L60576
-1111111111111111
-0101111010111001111110111001011101110110
-1111101111111111011111111101011111111111*  NOTE PT 4 of MC 66(LAB E) *
+1111111111111111111111110111111111111111*  NOTE PT 3 of MC 66(LAB E) *
 L60768
 1111111111111111
 1111111111111111111111111111111111111111
-1111111111111111111110111111111111111111*  NOTE PT 2 of MC 66(LAB E) *
+1111111111111111111111111111111111111111*  NOTE PT 2 of MC 66(LAB E) *
 L60864
 1111111111111111
-1111111011111111111111111011111111111110
-1111111101111111110111111111111111111111*  NOTE PT 1 of MC 66(LAB E) *
+1111111111111111111111111111111111101111
+1111111111111111111011111111111111111111*  NOTE PT 1 of MC 66(LAB E) *
+L60960
+1111111111111111
+1111111111111111111111111111111111111111
+1111011111101111111111111111111111111111*  NOTE PT 1 of MC 65(LAB E) *
 
 NOTE macrocell configurations
         0         0         0         0 *
 L61440 1111111111111111*
-L61456 00000100000001000000000001000010*  NOTE S16,S12 of block A * 
-L61488 00000000010000000000000000000000*  NOTE S14,S11 of block A * 
+L61456 11111100111111111111111111111100*  NOTE S16,S12 of block A * 
+L61488 00000000000000000000000001000000*  NOTE S14,S11 of block A * 
 L61520 1111111111111111*
-L61536 11110000111111111111111111111111*  NOTE S16,S12 of block B * 
-L61568 00000000000000000000000001000000*  NOTE S14,S11 of block B * 
+L61536 11000000000000000000110000111000*  NOTE S16,S12 of block B * 
+L61568 00000000001000100000000000000010*  NOTE S14,S11 of block B * 
 L61600 1111111111111111*
-L61616 00111111111111110011110111111011*  NOTE S16,S12 of block C * 
-L61648 00000000000000000000000000000000*  NOTE S14,S11 of block C * 
+L61616 01100010111000100100110001100011*  NOTE S16,S12 of block C * 
+L61648 00000010000000000000000001000000*  NOTE S14,S11 of block C * 
 L61680 1111111111111111*
-L61696 00100011000000111111111111111100*  NOTE S16,S12 of block D * 
-L61728 01000000000000000000000000000100*  NOTE S14,S11 of block D * 
+L61696 00000000001111111111111111111111*  NOTE S16,S12 of block D * 
+L61728 00000000000000000000000000000000*  NOTE S14,S11 of block D * 
 L61760 1111111111111111*
-L61776 10110001100010011001100010011001*  NOTE S9 ,S6  of block A * 
-L61808 01100010000001100110000000000000*  NOTE S13,S10 of block A * 
+L61776 10011001100110011001100110011000*  NOTE S9 ,S6  of block A * 
+L61808 00011001100110011001100110011000*  NOTE S13,S10 of block A * 
 L61840 1111111111111111*
-L61856 10010100100110011001100110011001*  NOTE S9 ,S6  of block B * 
-L61888 00000000000010000000000010001000*  NOTE S13,S10 of block B * 
+L61856 10011001101101000000100010011001*  NOTE S9 ,S6  of block B * 
+L61888 01001010000000000000001001100100*  NOTE S13,S10 of block B * 
 L61920 1111111111111111*
-L61936 10011001100110011001100110011001*  NOTE S9 ,S6  of block C * 
-L61968 00000000000000000000000000000000*  NOTE S13,S10 of block C * 
+L61936 00010100110001001001100100001001*  NOTE S9 ,S6  of block C * 
+L61968 00000000000000100100000000000100*  NOTE S13,S10 of block C * 
 L62000 1111111111111111*
-L62016 10001001100110011001100110011000*  NOTE S9 ,S6  of block D * 
-L62048 10011001100110011000000010001000*  NOTE S13,S10 of block D * 
+L62016 10011001100110011001100110011001*  NOTE S9 ,S6  of block D * 
+L62048 10011001100110011001100000000000*  NOTE S13,S10 of block D * 
 L62080 1111111111111111*
-L62096 00000000001000000000000000000000*  NOTE S20,S18 of block A * 
-L62128 00000000000000000000000000000000*  NOTE S8 ,S21 of block A * 
+L62096 00000010000000000000000000000000*  NOTE S20,S18 of block A * 
+L62128 00111111111111111111111100111100*  NOTE S8 ,S21 of block A * 
 L62160 1111111111111111*
-L62176 00000010000000000000000000000000*  NOTE S20,S18 of block B * 
-L62208 00000000000011000000000000001100*  NOTE S8 ,S21 of block B * 
+L62176 01000000000000100010001000000000*  NOTE S20,S18 of block B * 
+L62208 00001100000000000000000000000000*  NOTE S8 ,S21 of block B * 
 L62240 1111111111111111*
 L62256 00000000000000000000000000000000*  NOTE S20,S18 of block C * 
 L62288 00000000000000000000000000000000*  NOTE S8 ,S21 of block C * 
 L62320 1111111111111111*
-L62336 00000000000000000000000000000010*  NOTE S20,S18 of block D * 
-L62368 00111111111111111100000011000000*  NOTE S8 ,S21 of block D * 
+L62336 00000000000000000000000000000000*  NOTE S20,S18 of block D * 
+L62368 11111111111111111111110000000000*  NOTE S8 ,S21 of block D * 
 L62400 1111111111111111*
-L62416 00110000001100000000000000000000*  NOTE S7 ,S19 of block A * 
-L62448 01010010100010000011010010101100*  NOTE S22,S5  of block A * 
+L62416 11111111111111111111111111111100*  NOTE S7 ,S19 of block A * 
+L62448 00110110111011100111011011101100*  NOTE S22,S5  of block A * 
 L62480 1111111111111111*
-L62496 00111111000000000011000000000000*  NOTE S7 ,S19 of block B * 
-L62528 00010000100011000001000011101100*  NOTE S22,S5  of block B * 
+L62496 11000000001111110011001100110000*  NOTE S7 ,S19 of block B * 
+L62528 00010100110011000111010010001010*  NOTE S22,S5  of block B * 
 L62560 1111111111111111*
-L62576 00000000000000000000000000000000*  NOTE S7 ,S19 of block C * 
-L62608 00010000100010000001000010001000*  NOTE S22,S5  of block C * 
+L62576 00001100110011000011111100001100*  NOTE S7 ,S19 of block C * 
+L62608 00010000100010000011001010101000*  NOTE S22,S5  of block C * 
 L62640 1111111111111111*
-L62656 00000011000000111111111111111111*  NOTE S7 ,S19 of block D * 
-L62688 01110110111011100101000011001000*  NOTE S22,S5  of block D * 
+L62656 11111111111111111111111111111111*  NOTE S7 ,S19 of block D * 
+L62688 01110110111011100111010010001000*  NOTE S22,S5  of block D * 
 L62720 1111111111111111*
 L62736 11111111111111111111111111111111*  NOTE S23,S4  of block A * 
-L62768 00000000000000000000110000000100*  NOTE S3 ,S15 of block A * 
+L62768 00100110011001100110011011100110*  NOTE S3 ,S15 of block A * 
 L62800 1111111111111111*
 L62816 11111111111111111111111111111111*  NOTE S23,S4  of block B * 
-L62848 00000000000001000000000011100100*  NOTE S3 ,S15 of block B * 
+L62848 01100110111011101110011001100111*  NOTE S3 ,S15 of block B * 
 L62880 1111111111111111*
 L62896 11111111111111111111111111111111*  NOTE S23,S4  of block C * 
-L62928 00000000000000000010000000000000*  NOTE S3 ,S15 of block C * 
+L62928 01100110011001100110011001100110*  NOTE S3 ,S15 of block C * 
 L62960 1111111111111111*
 L62976 11111111111111111111111111111111*  NOTE S23,S4  of block D * 
-L63008 11100110011001100100000001000000*  NOTE S3 ,S15 of block D * 
+L63008 01100110011001100110011001100110*  NOTE S3 ,S15 of block D * 
 L63040 1111111111111111*
-L63056 00110011000011000011001100001100*  NOTE S0 ,S1  of block A * 
-L63088 10111001110111011011100111011101*  NOTE S17,S2  of block A * 
+L63056 00000011000000000000000000000000*  NOTE S0 ,S1  of block A * 
+L63088 10011001100110011001100111011001*  NOTE S17,S2  of block A * 
 L63120 1111111111111111*
-L63136 00000011000011000000001100001100*  NOTE S0 ,S1  of block B * 
-L63168 10111001110110011011100111011001*  NOTE S17,S2  of block B * 
+L63136 00110011000011000011001100001100*  NOTE S0 ,S1  of block B * 
+L63168 10111001110111011011100111011101*  NOTE S17,S2  of block B * 
 L63200 1111111111111111*
 L63216 00110011000011000011001100001100*  NOTE S0 ,S1  of block C * 
 L63248 10111001110111011011100111011101*  NOTE S17,S2  of block C * 
 L63280 1111111111111111*
-L63296 00110000000011000000000000000000*  NOTE S0 ,S1  of block D * 
-L63328 10011001100110011011100110011101*  NOTE S17,S2  of block D * 
+L63296 00110011000000000000000000000000*  NOTE S0 ,S1  of block D * 
+L63328 10011001100110011001100111011101*  NOTE S17,S2  of block D * 
 L63360 1111111111111111*
-L63376 01110111010011110111011111101100*  NOTE S16,S12 of block H * 
-L63408 01000100001000100100000000000000*  NOTE S14,S11 of block H * 
+L63376 00000011011111000111111111001100*  NOTE S16,S12 of block H * 
+L63408 00000100001000000100010000000000*  NOTE S14,S11 of block H * 
 L63440 1111111111111111*
-L63456 01100110011001100110011001100010*  NOTE S16,S12 of block G * 
+L63456 01000100011000100100000000000100*  NOTE S16,S12 of block G * 
 L63488 00000000000000000000000000000000*  NOTE S14,S11 of block G * 
 L63520 1111111111111111*
-L63536 01110111011011100111001101101111*  NOTE S16,S12 of block F * 
+L63536 00110011000011000011011101101111*  NOTE S16,S12 of block F * 
 L63568 00000000000000000000000000000000*  NOTE S14,S11 of block F * 
 L63600 1111111111111111*
-L63616 11110110010001000100110000100010*  NOTE S16,S12 of block E * 
-L63648 00000000000000100110001001100000*  NOTE S14,S11 of block E * 
+L63616 11111111111100111111001111001100*  NOTE S16,S12 of block E * 
+L63648 00000000000000000000000000000000*  NOTE S14,S11 of block E * 
 L63680 1111111111111111*
-L63696 10011001100110011001100110011001*  NOTE S9 ,S6  of block H * 
-L63728 00010000100010000001000010001000*  NOTE S13,S10 of block H * 
+L63696 10001001100110001001100110011000*  NOTE S9 ,S6  of block H * 
+L63728 00010000100010000001000010000000*  NOTE S13,S10 of block H * 
 L63760 1111111111111111*
-L63776 10001001100100011000100110011100*  NOTE S9 ,S6  of block G * 
-L63808 00000000010000000000000001000000*  NOTE S13,S10 of block G * 
+L63776 10011001100110011001100110001100*  NOTE S9 ,S6  of block G * 
+L63808 00000000000000000010000001000100*  NOTE S13,S10 of block G * 
 L63840 1111111111111111*
 L63856 10011001100110011001100110011001*  NOTE S9 ,S6  of block F * 
-L63888 00010000100010000001000000001000*  NOTE S13,S10 of block F * 
+L63888 10010000100010000001000010001000*  NOTE S13,S10 of block F * 
 L63920 1111111111111111*
-L63936 10011000100110001000100010010001*  NOTE S9 ,S6  of block E * 
-L63968 00000000010101010001010110010001*  NOTE S13,S10 of block E * 
+L63936 10011001100110011001000110011001*  NOTE S9 ,S6  of block E * 
+L63968 00010001100010001000100110010001*  NOTE S13,S10 of block E * 
 L64000 1111111111111111*
-L64016 01000100011000100100010001100010*  NOTE S20,S18 of block H * 
-L64048 00110000110011000011000011001100*  NOTE S8 ,S21 of block H * 
+L64016 01100100011000100100010001100010*  NOTE S20,S18 of block H * 
+L64048 00110000110011000011000011000000*  NOTE S8 ,S21 of block H * 
 L64080 1111111111111111*
-L64096 01000100011000100100010001100000*  NOTE S20,S18 of block G * 
+L64096 01000100011000100110011001100010*  NOTE S20,S18 of block G * 
 L64128 00000000000000000000000000000000*  NOTE S8 ,S21 of block G * 
 L64160 1111111111111111*
-L64176 01000100011000100100010001100010*  NOTE S20,S18 of block F * 
-L64208 00110000110011000011000000001100*  NOTE S8 ,S21 of block F * 
+L64176 01000100011000100100010001100000*  NOTE S20,S18 of block F * 
+L64208 11110000110011000011000011001100*  NOTE S8 ,S21 of block F * 
 L64240 1111111111111111*
 L64256 00000000000000000000000000100010*  NOTE S20,S18 of block E * 
-L64288 00000000001100000000000000000011*  NOTE S8 ,S21 of block E * 
+L64288 00110011000000000000000000000000*  NOTE S8 ,S21 of block E * 
 L64320 1111111111111111*
 L64336 11111111111111111111111111111111*  NOTE S7 ,S19 of block H * 
 L64368 01110110111011100111011011101110*  NOTE S22,S5  of block H * 
 L64400 1111111111111111*
-L64416 11001100111100111100110011111100*  NOTE S7 ,S19 of block G * 
-L64448 01110110111011100111011011101110*  NOTE S22,S5  of block G * 
+L64416 11001100111100111111111111111111*  NOTE S7 ,S19 of block G * 
+L64448 01110110111011100101011010101010*  NOTE S22,S5  of block G * 
 L64480 1111111111111111*
-L64496 11111100111111111111111111111111*  NOTE S7 ,S19 of block F * 
-L64528 01110110111011100111011010101110*  NOTE S22,S5  of block F * 
+L64496 11111111111111111111111111111111*  NOTE S7 ,S19 of block F * 
+L64528 01110110111011100111011011101110*  NOTE S22,S5  of block F * 
 L64560 1111111111111111*
-L64576 11000000000000000000110000110011*  NOTE S7 ,S19 of block E * 
-L64608 01010100101010000001000010001010*  NOTE S22,S5  of block E * 
+L64576 11111111111100111111001111111111*  NOTE S7 ,S19 of block E * 
+L64608 01110110110011000101011011101010*  NOTE S22,S5  of block E * 
 L64640 1111111111111111*
 L64656 11111111111111111111111111111111*  NOTE S23,S4  of block H * 
-L64688 11101111011101111110111101110111*  NOTE S3 ,S15 of block H * 
+L64688 11101111011101111110111101111111*  NOTE S3 ,S15 of block H * 
 L64720 1111111111111111*
 L64736 11111111111111111111111111111111*  NOTE S23,S4  of block G * 
-L64768 00101111001100111100111100110011*  NOTE S3 ,S15 of block G * 
+L64768 11101111111111111110111101110111*  NOTE S3 ,S15 of block G * 
 L64800 1111111111111111*
 L64816 11111111111111111111111111111111*  NOTE S23,S4  of block F * 
-L64848 11101111011101111110111100110111*  NOTE S3 ,S15 of block F * 
+L64848 01101111011101111110111101110111*  NOTE S3 ,S15 of block F * 
 L64880 1111111111111111*
 L64896 11111111111111111111111111111111*  NOTE S23,S4  of block E * 
-L64928 11001100001000000000000000000110*  NOTE S3 ,S15 of block E * 
+L64928 11101110010001100100011001100110*  NOTE S3 ,S15 of block E * 
 L64960 1111111111111111*
-L64976 11001100111100111100110011110011*  NOTE S0 ,S1  of block H * 
-L65008 11011111101110111101111110111011*  NOTE S17,S2  of block H * 
+L64976 11111100111100111100110011110011*  NOTE S0 ,S1  of block H * 
+L65008 11011111101110111101111110111111*  NOTE S17,S2  of block H * 
 L65040 1111111111111111*
 L65056 11111111111111111111111111111111*  NOTE S0 ,S1  of block G * 
 L65088 11111111111111111111111111111111*  NOTE S17,S2  of block G * 
 L65120 1111111111111111*
-L65136 11001111111100111100110011110000*  NOTE S0 ,S1  of block F * 
-L65168 10011111101110011001100111011001*  NOTE S17,S2  of block F * 
+L65136 11001100111100111100110011110000*  NOTE S0 ,S1  of block F * 
+L65168 10011111101110011001100110011001*  NOTE S17,S2  of block F * 
 L65200 1111111111111111*
-L65216 00110011000011000011001100111111*  NOTE S0 ,S1  of block E * 
-L65248 10111001110111011011100111011101*  NOTE S17,S2  of block E * 
+L65216 00110011000011000011001100110011*  NOTE S0 ,S1  of block E * 
+L65248 10011001110111011011100111011101*  NOTE S17,S2  of block E * 
 
 NOTE   UIM for block A and H*
 NOTE         0         0         0*
 L65280 111111111111111111111111110*  NOTE Mux-0 of block A*
-L65307 111111111111111111111111111*  NOTE Mux-1 of block H*
-L65334 111111110111111111111111111*  NOTE Mux-0 of block H*
-L65361 111111111111111111111111111*  NOTE Mux-1 of block A*
-L65388 111011111111111111111111111*  NOTE Mux-2 of block A*
-L65415 111111111101111111111111111*  NOTE Mux-3 of block H*
-L65442 111111110111111111111111111*  NOTE Mux-2 of block H*
-L65469 111011111111111111111111111*  NOTE Mux-3 of block A*
-L65496 111111111111111111111111110*  NOTE Mux-4 of block A*
-L65523 111011111111111111111111111*  NOTE Mux-5 of block H*
-L65550 011111111111111111111111111*  NOTE Mux-4 of block H*
-L65577 111011111111111111111111111*  NOTE Mux-5 of block A*
-L65604 011111111111111111111111111*  NOTE Mux-6 of block A*
-L65631 111111110111111111111111111*  NOTE Mux-7 of block H*
-L65658 011111111111111111111111111*  NOTE Mux-6 of block H*
-L65685 111111111111111111111111110*  NOTE Mux-7 of block A*
-L65712 111111111111111111111111110*  NOTE Mux-8 of block A*
-L65739 111011111111111111111111111*  NOTE Mux-9 of block H*
-L65766 111011111111111111111111111*  NOTE Mux-8 of block H*
-L65793 111011111111111111111111111*  NOTE Mux-9 of block A*
+L65307 111111111111111111011111111*  NOTE Mux-1 of block H*
+L65334 111111111110111111111111111*  NOTE Mux-0 of block H*
+L65361 111011111111111111111111111*  NOTE Mux-1 of block A*
+L65388 111111111111110111111111111*  NOTE Mux-2 of block A*
+L65415 111111111111111111111110111*  NOTE Mux-3 of block H*
+L65442 101111111111111111111111111*  NOTE Mux-2 of block H*
+L65469 111111111111111111111110111*  NOTE Mux-3 of block A*
+L65496 111110111111111111111111111*  NOTE Mux-4 of block A*
+L65523 111111111111111111111111111*  NOTE Mux-5 of block H*
+L65550 111111111111111111111111011*  NOTE Mux-4 of block H*
+L65577 111111110111111111111111111*  NOTE Mux-5 of block A*
+L65604 111110111111111111111111111*  NOTE Mux-6 of block A*
+L65631 111111101111111111111111111*  NOTE Mux-7 of block H*
+L65658 111111111111111111111111101*  NOTE Mux-6 of block H*
+L65685 111111101111111111111111111*  NOTE Mux-7 of block A*
+L65712 110111111111111111111111111*  NOTE Mux-8 of block A*
+L65739 111111111111111111110111111*  NOTE Mux-9 of block H*
+L65766 111110111111111111111111111*  NOTE Mux-8 of block H*
+L65793 111111110111111111111111111*  NOTE Mux-9 of block A*
 L65820 111111111111111111111111110*  NOTE Mux-10 of block A*
 L65847 011111111111111111111111111*  NOTE Mux-11 of block H*
-L65874 111111111111101111111111111*  NOTE Mux-10 of block H*
-L65901 011111111111111111111111111*  NOTE Mux-11 of block A*
-L65928 111111111111111111111111111*  NOTE Mux-12 of block A*
-L65955 111011111111111111111111111*  NOTE Mux-13 of block H*
-L65982 111111111111111111111011111*  NOTE Mux-12 of block H*
-L66009 111011111111111111111111111*  NOTE Mux-13 of block A*
-L66036 111110111111111111111111111*  NOTE Mux-14 of block A*
-L66063 111111111111111011111111111*  NOTE Mux-15 of block H*
-L66090 111110111111111111111111111*  NOTE Mux-14 of block H*
-L66117 111111111111111011111111111*  NOTE Mux-15 of block A*
-L66144 101111111111111111111111111*  NOTE Mux-16 of block A*
-L66171 111011111111111111111111111*  NOTE Mux-17 of block H*
-L66198 101111111111111111111111111*  NOTE Mux-16 of block H*
-L66225 111011111111111111111111111*  NOTE Mux-17 of block A*
-L66252 111111111111111111111111111*  NOTE Mux-18 of block A*
-L66279 111111111110111111111111111*  NOTE Mux-19 of block H*
-L66306 111111111110111111111111111*  NOTE Mux-18 of block H*
-L66333 111111111111111111111111111*  NOTE Mux-19 of block A*
-L66360 111111111111111111111111111*  NOTE Mux-20 of block A*
-L66387 111111111111111011111111111*  NOTE Mux-21 of block H*
-L66414 111111111111111111111111111*  NOTE Mux-20 of block H*
-L66441 111111111111111011111111111*  NOTE Mux-21 of block A*
-L66468 101111111111111111111111111*  NOTE Mux-22 of block A*
-L66495 111111111111111111111111111*  NOTE Mux-23 of block H*
-L66522 101111111111111111111111111*  NOTE Mux-22 of block H*
-L66549 111111111111111111111111111*  NOTE Mux-23 of block A*
-L66576 110111111111111111111111111*  NOTE Mux-24 of block A*
-L66603 111111111111111011111111111*  NOTE Mux-25 of block H*
-L66630 110111111111111111111111111*  NOTE Mux-24 of block H*
-L66657 111111111111111011111111111*  NOTE Mux-25 of block A*
-L66684 110111111111111111111111111*  NOTE Mux-26 of block A*
-L66711 111111111111111111111111111*  NOTE Mux-27 of block H*
-L66738 110111111111111111111111111*  NOTE Mux-26 of block H*
-L66765 111111111111111111111111111*  NOTE Mux-27 of block A*
-L66792 111111111111111110111111111*  NOTE Mux-28 of block A*
-L66819 111111111111111111111111111*  NOTE Mux-29 of block H*
-L66846 111111111111111110111111111*  NOTE Mux-28 of block H*
-L66873 111111111111111011111111111*  NOTE Mux-29 of block A*
-L66900 111110111111111111111111111*  NOTE Mux-30 of block A*
-L66927 110111111111111111111111111*  NOTE Mux-31 of block H*
+L65874 111111111111111111111111110*  NOTE Mux-10 of block H*
+L65901 111111111111111111111101111*  NOTE Mux-11 of block A*
+L65928 111111111111110111111111111*  NOTE Mux-12 of block A*
+L65955 111111111111111111110111111*  NOTE Mux-13 of block H*
+L65982 110111111111111111111111111*  NOTE Mux-12 of block H*
+L66009 111111111111111111111111111*  NOTE Mux-13 of block A*
+L66036 111111111111011111111111111*  NOTE Mux-14 of block A*
+L66063 111111111111111111101111111*  NOTE Mux-15 of block H*
+L66090 111111111111011111111111111*  NOTE Mux-14 of block H*
+L66117 111111111111111111101111111*  NOTE Mux-15 of block A*
+L66144 111111111111111111111101111*  NOTE Mux-16 of block A*
+L66171 111111111111111101111111111*  NOTE Mux-17 of block H*
+L66198 011111111111111111111111111*  NOTE Mux-16 of block H*
+L66225 111111101111111111111111111*  NOTE Mux-17 of block A*
+L66252 111111111111111111110111111*  NOTE Mux-18 of block A*
+L66279 111111111111111101111111111*  NOTE Mux-19 of block H*
+L66306 111111111111111111110111111*  NOTE Mux-18 of block H*
+L66333 111111111111111101111111111*  NOTE Mux-19 of block A*
+L66360 111111111111111111111111101*  NOTE Mux-20 of block A*
+L66387 111111011111111111111111111*  NOTE Mux-21 of block H*
+L66414 111111111111011111111111111*  NOTE Mux-20 of block H*
+L66441 111111111111111111101111111*  NOTE Mux-21 of block A*
+L66468 111111111111111111111111110*  NOTE Mux-22 of block A*
+L66495 111111111111111111011111111*  NOTE Mux-23 of block H*
+L66522 111111111111111111111111111*  NOTE Mux-22 of block H*
+L66549 111111111011111111111111111*  NOTE Mux-23 of block A*
+L66576 111111111111111111011111111*  NOTE Mux-24 of block A*
+L66603 111110111111111111111111111*  NOTE Mux-25 of block H*
+L66630 111111111111011111111111111*  NOTE Mux-24 of block H*
+L66657 111111111111111110111111111*  NOTE Mux-25 of block A*
+L66684 111111111111111111111111110*  NOTE Mux-26 of block A*
+L66711 111111111111111111101111111*  NOTE Mux-27 of block H*
+L66738 111111111111111111111110111*  NOTE Mux-26 of block H*
+L66765 111111111111111111101111111*  NOTE Mux-27 of block A*
+L66792 111111111111110111111111111*  NOTE Mux-28 of block A*
+L66819 111111111111111110111111111*  NOTE Mux-29 of block H*
+L66846 111111111111110111111111111*  NOTE Mux-28 of block H*
+L66873 111101111111111111111111111*  NOTE Mux-29 of block A*
+L66900 111111111111111111111111011*  NOTE Mux-30 of block A*
+L66927 111111110111111111111111111*  NOTE Mux-31 of block H*
 L66954 111110111111111111111111111*  NOTE Mux-30 of block H*
-L66981 110111111111111111111111111*  NOTE Mux-31 of block A*
-L67008 110111111111111111111111111*  NOTE Mux-32 of block A*
-L67035 111111111111111111111111110*  NOTE Mux-33 of block H*
-L67062 110111111111111111111111111*  NOTE Mux-32 of block H*
-L67089 111111111111111111111111110*  NOTE Mux-33 of block A*
-L67116 111111111111111111111111111*  NOTE Mux-34 of block A*
-L67143 111111111111111111111111111*  NOTE Mux-35 of block H*
-L67170 101111111111111111111111111*  NOTE Mux-34 of block H*
-L67197 111111111111111111111111111*  NOTE Mux-35 of block A*
+L66981 111111111111111101111111111*  NOTE Mux-31 of block A*
+L67008 111111111111111111111111011*  NOTE Mux-32 of block A*
+L67035 111111011111111111111111111*  NOTE Mux-33 of block H*
+L67062 011111111111111111111111111*  NOTE Mux-32 of block H*
+L67089 111111011111111111111111111*  NOTE Mux-33 of block A*
+L67116 111111111111110111111111111*  NOTE Mux-34 of block A*
+L67143 111101111111111111111111111*  NOTE Mux-35 of block H*
+L67170 111111111111111111111111011*  NOTE Mux-34 of block H*
+L67197 111111111111111111101111111*  NOTE Mux-35 of block A*
 L67224 111111111111110111111111111*  NOTE Mux-36 of block A*
 L67251 111111111111110111111111111*  NOTE Mux-37 of block H*
 L67278 111111111111110111111111111*  NOTE Mux-36 of block H*
@@ -1507,78 +1407,78 @@ L67413 111111111111111111111111011*  NOTE Mux-39 of block A*
 
 NOTE   UIM for block B and G*
 NOTE         0         0         0*
-L67440 111111111111111111111111110*  NOTE Mux-0 of block B*
-L67467 111111111111111111111111101*  NOTE Mux-1 of block G*
-L67494 101111111111111111111111111*  NOTE Mux-0 of block G*
-L67521 111111111011111111111111111*  NOTE Mux-1 of block B*
-L67548 111111111111101111111111111*  NOTE Mux-2 of block B*
-L67575 111111111111111011111111111*  NOTE Mux-3 of block G*
-L67602 111111111111111111111111111*  NOTE Mux-2 of block G*
-L67629 111111111011111111111111111*  NOTE Mux-3 of block B*
-L67656 111111111111111111110111111*  NOTE Mux-4 of block B*
-L67683 111111111111111111111101111*  NOTE Mux-5 of block G*
-L67710 111111111111111111111111110*  NOTE Mux-4 of block G*
-L67737 111111110111111111111111111*  NOTE Mux-5 of block B*
-L67764 111110111111111111111111111*  NOTE Mux-6 of block B*
-L67791 111111111111111011111111111*  NOTE Mux-7 of block G*
-L67818 111111111111111111111101111*  NOTE Mux-6 of block G*
-L67845 111111111011111111111111111*  NOTE Mux-7 of block B*
-L67872 111111111111111110111111111*  NOTE Mux-8 of block B*
-L67899 111011111111111111111111111*  NOTE Mux-9 of block G*
-L67926 111011111111111111111111111*  NOTE Mux-8 of block G*
-L67953 111111111111111101111111111*  NOTE Mux-9 of block B*
-L67980 111111111101111111111111111*  NOTE Mux-10 of block B*
-L68007 110111111111111111111111111*  NOTE Mux-11 of block G*
-L68034 111111111111111111111011111*  NOTE Mux-10 of block G*
-L68061 111111111110111111111111111*  NOTE Mux-11 of block B*
-L68088 111111111111110111111111111*  NOTE Mux-12 of block B*
-L68115 111011111111111111111111111*  NOTE Mux-13 of block G*
-L68142 110111111111111111111111111*  NOTE Mux-12 of block G*
-L68169 111111111111111111111101111*  NOTE Mux-13 of block B*
-L68196 111111111111111111111101111*  NOTE Mux-14 of block B*
-L68223 111111111111111011111111111*  NOTE Mux-15 of block G*
-L68250 101111111111111111111111111*  NOTE Mux-14 of block G*
-L68277 111111110111111111111111111*  NOTE Mux-15 of block B*
-L68304 111111111111111111111111101*  NOTE Mux-16 of block B*
-L68331 111111111111111111111111111*  NOTE Mux-17 of block G*
-L68358 101111111111111111111111111*  NOTE Mux-16 of block G*
-L68385 111111101111111111111111111*  NOTE Mux-17 of block B*
-L68412 111111111111111111111101111*  NOTE Mux-18 of block B*
-L68439 111011111111111111111111111*  NOTE Mux-19 of block G*
+L67440 011111111111111111111111111*  NOTE Mux-0 of block B*
+L67467 111111011111111111111111111*  NOTE Mux-1 of block G*
+L67494 011111111111111111111111111*  NOTE Mux-0 of block G*
+L67521 111111111111111111011111111*  NOTE Mux-1 of block B*
+L67548 111111111111011111111111111*  NOTE Mux-2 of block B*
+L67575 111110111111111111111111111*  NOTE Mux-3 of block G*
+L67602 111111111111011111111111111*  NOTE Mux-2 of block G*
+L67629 111110111111111111111111111*  NOTE Mux-3 of block B*
+L67656 111111111111110111111111111*  NOTE Mux-4 of block B*
+L67683 111111110111111111111111111*  NOTE Mux-5 of block G*
+L67710 111111111111110111111111111*  NOTE Mux-4 of block G*
+L67737 111111111111111111111111110*  NOTE Mux-5 of block B*
+L67764 111111111110111111111111111*  NOTE Mux-6 of block B*
+L67791 111111111111111111111111111*  NOTE Mux-7 of block G*
+L67818 111111111110111111111111111*  NOTE Mux-6 of block G*
+L67845 111111111111111111111111111*  NOTE Mux-7 of block B*
+L67872 111110111111111111111111111*  NOTE Mux-8 of block B*
+L67899 111110111111111111111111111*  NOTE Mux-9 of block G*
+L67926 111110111111111111111111111*  NOTE Mux-8 of block G*
+L67953 111110111111111111111111111*  NOTE Mux-9 of block B*
+L67980 111111111111111111111011111*  NOTE Mux-10 of block B*
+L68007 111111111111111110111111111*  NOTE Mux-11 of block G*
+L68034 111111111111111111111111110*  NOTE Mux-10 of block G*
+L68061 111111111111111111111111111*  NOTE Mux-11 of block B*
+L68088 111111111111111111111111110*  NOTE Mux-12 of block B*
+L68115 111111111111111111111111110*  NOTE Mux-13 of block G*
+L68142 111111111111110111111111111*  NOTE Mux-12 of block G*
+L68169 110111111111111111111111111*  NOTE Mux-13 of block B*
+L68196 111101111111111111111111111*  NOTE Mux-14 of block B*
+L68223 111111110111111111111111111*  NOTE Mux-15 of block G*
+L68250 111111111111011111111111111*  NOTE Mux-14 of block G*
+L68277 111111111111111111111111101*  NOTE Mux-15 of block B*
+L68304 111111111111111111111111111*  NOTE Mux-16 of block B*
+L68331 111111111111111101111111111*  NOTE Mux-17 of block G*
+L68358 111111111111111111111111101*  NOTE Mux-16 of block G*
+L68385 111111111111111101111111111*  NOTE Mux-17 of block B*
+L68412 111111111111111111111111111*  NOTE Mux-18 of block B*
+L68439 111111111111111111011111111*  NOTE Mux-19 of block G*
 L68466 111111111111111111111111111*  NOTE Mux-18 of block G*
-L68493 111111111111111111101111111*  NOTE Mux-19 of block B*
-L68520 111111111101111111111111111*  NOTE Mux-20 of block B*
-L68547 111111111111111111110111111*  NOTE Mux-21 of block G*
+L68493 111111111111111111111111110*  NOTE Mux-19 of block B*
+L68520 111111111111111111011111111*  NOTE Mux-20 of block B*
+L68547 111111111111111111101111111*  NOTE Mux-21 of block G*
 L68574 111111111111111111011111111*  NOTE Mux-20 of block G*
-L68601 111011111111111111111111111*  NOTE Mux-21 of block B*
-L68628 111111111111111111111111110*  NOTE Mux-22 of block B*
-L68655 111111111111111111111111111*  NOTE Mux-23 of block G*
-L68682 111110111111111111111111111*  NOTE Mux-22 of block G*
-L68709 111111111111111111111011111*  NOTE Mux-23 of block B*
-L68736 111011111111111111111111111*  NOTE Mux-24 of block B*
-L68763 111110111111111111111111111*  NOTE Mux-25 of block G*
-L68790 110111111111111111111111111*  NOTE Mux-24 of block G*
-L68817 111111111111111101111111111*  NOTE Mux-25 of block B*
-L68844 111111011111111111111111111*  NOTE Mux-26 of block B*
-L68871 111111111111111111011111111*  NOTE Mux-27 of block G*
-L68898 110111111111111111111111111*  NOTE Mux-26 of block G*
-L68925 111111111111111111111111110*  NOTE Mux-27 of block B*
-L68952 111111111111111111111111110*  NOTE Mux-28 of block B*
-L68979 111111011111111111111111111*  NOTE Mux-29 of block G*
-L69006 011111111111111111111111111*  NOTE Mux-28 of block G*
-L69033 111111111111111111101111111*  NOTE Mux-29 of block B*
-L69060 111111111111111111111111011*  NOTE Mux-30 of block B*
-L69087 111011111111111111111111111*  NOTE Mux-31 of block G*
-L69114 111110111111111111111111111*  NOTE Mux-30 of block G*
-L69141 111111111111111101111111111*  NOTE Mux-31 of block B*
-L69168 111111111111111111111110111*  NOTE Mux-32 of block B*
-L69195 011111111111111111111111111*  NOTE Mux-33 of block G*
-L69222 110111111111111111111111111*  NOTE Mux-32 of block G*
-L69249 111111111111111111101111111*  NOTE Mux-33 of block B*
-L69276 111111111111110111111111111*  NOTE Mux-34 of block B*
-L69303 111101111111111111111111111*  NOTE Mux-35 of block G*
-L69330 111011111111111111111111111*  NOTE Mux-34 of block G*
-L69357 111111111111111111101111111*  NOTE Mux-35 of block B*
+L68601 111111111111111111111111110*  NOTE Mux-21 of block B*
+L68628 111111111111111111111111011*  NOTE Mux-22 of block B*
+L68655 111111111111111111011111111*  NOTE Mux-23 of block G*
+L68682 111111111111111111111111011*  NOTE Mux-22 of block G*
+L68709 111111111111111111011111111*  NOTE Mux-23 of block B*
+L68736 111110111111111111111111111*  NOTE Mux-24 of block B*
+L68763 111111111111111111101111111*  NOTE Mux-25 of block G*
+L68790 111110111111111111111111111*  NOTE Mux-24 of block G*
+L68817 111111111111111111101111111*  NOTE Mux-25 of block B*
+L68844 111111111111111111111110111*  NOTE Mux-26 of block B*
+L68871 111111111111111111111111111*  NOTE Mux-27 of block G*
+L68898 111111111111111111111110111*  NOTE Mux-26 of block G*
+L68925 111111111111111111110111111*  NOTE Mux-27 of block B*
+L68952 111111111111111101111111111*  NOTE Mux-28 of block B*
+L68979 111111111111111111111101111*  NOTE Mux-29 of block G*
+L69006 111111111111111111111111110*  NOTE Mux-28 of block G*
+L69033 111111111111111101111111111*  NOTE Mux-29 of block B*
+L69060 110111111111111111111111111*  NOTE Mux-30 of block B*
+L69087 111111111111111111111110111*  NOTE Mux-31 of block G*
+L69114 110111111111111111111111111*  NOTE Mux-30 of block G*
+L69141 111111111111111111111110111*  NOTE Mux-31 of block B*
+L69168 111111111111111111111111101*  NOTE Mux-32 of block B*
+L69195 111111011111111111111111111*  NOTE Mux-33 of block G*
+L69222 111111111111111111111111101*  NOTE Mux-32 of block G*
+L69249 111111011111111111111111111*  NOTE Mux-33 of block B*
+L69276 111111111111101111111111111*  NOTE Mux-34 of block B*
+L69303 111111111111111111101111111*  NOTE Mux-35 of block G*
+L69330 111111111111101111111111111*  NOTE Mux-34 of block G*
+L69357 111110111111111111111111111*  NOTE Mux-35 of block B*
 L69384 111111111111110111111111111*  NOTE Mux-36 of block B*
 L69411 111111111111110111111111111*  NOTE Mux-37 of block G*
 L69438 111111111111110111111111111*  NOTE Mux-36 of block G*
@@ -1590,77 +1490,77 @@ L69573 111111111111111111111111011*  NOTE Mux-39 of block B*
 
 NOTE   UIM for block C and F*
 NOTE         0         0         0*
-L69600 111111111111111111111111111*  NOTE Mux-0 of block C*
+L69600 111111111110111111111111111*  NOTE Mux-0 of block C*
 L69627 111111111111111111111111111*  NOTE Mux-1 of block F*
-L69654 111111111111111111011111111*  NOTE Mux-0 of block F*
+L69654 111111111111111111111111111*  NOTE Mux-0 of block F*
 L69681 111111011111111111111111111*  NOTE Mux-1 of block C*
-L69708 111111111111101111111111111*  NOTE Mux-2 of block C*
-L69735 111111111101111111111111111*  NOTE Mux-3 of block F*
-L69762 111111111111101111111111111*  NOTE Mux-2 of block F*
-L69789 111111111101111111111111111*  NOTE Mux-3 of block C*
-L69816 111111111111111111111111111*  NOTE Mux-4 of block C*
-L69843 111011111111111111111111111*  NOTE Mux-5 of block F*
-L69870 111111111111111111111111101*  NOTE Mux-4 of block F*
-L69897 111011111111111111111111111*  NOTE Mux-5 of block C*
-L69924 111111111111011111111111111*  NOTE Mux-6 of block C*
-L69951 111111111111111111111111111*  NOTE Mux-7 of block F*
-L69978 111111111111111111111111111*  NOTE Mux-6 of block F*
-L70005 111111111111011111111111111*  NOTE Mux-7 of block C*
-L70032 111111111111111111111111110*  NOTE Mux-8 of block C*
-L70059 111111111111111111111111111*  NOTE Mux-9 of block F*
-L70086 111011111111111111111111111*  NOTE Mux-8 of block F*
-L70113 111111111110111111111111111*  NOTE Mux-9 of block C*
+L69708 111111111101111111111111111*  NOTE Mux-2 of block C*
+L69735 111111111111111111011111111*  NOTE Mux-3 of block F*
+L69762 111111111111111111111111111*  NOTE Mux-2 of block F*
+L69789 111111111111111111111111111*  NOTE Mux-3 of block C*
+L69816 111111111111111111111111011*  NOTE Mux-4 of block C*
+L69843 111111111111111111111111111*  NOTE Mux-5 of block F*
+L69870 111111111111111111111111110*  NOTE Mux-4 of block F*
+L69897 111111101111111111111111111*  NOTE Mux-5 of block C*
+L69924 111111111111111111111111110*  NOTE Mux-6 of block C*
+L69951 111111111111011111111111111*  NOTE Mux-7 of block F*
+L69978 111111111111011111111111111*  NOTE Mux-6 of block F*
+L70005 111111111111111111111111110*  NOTE Mux-7 of block C*
+L70032 111111111111111111111110111*  NOTE Mux-8 of block C*
+L70059 111111111110111111111111111*  NOTE Mux-9 of block F*
+L70086 111111111111111111111111110*  NOTE Mux-8 of block F*
+L70113 111111111111111111111111110*  NOTE Mux-9 of block C*
 L70140 111111111111111111111111111*  NOTE Mux-10 of block C*
-L70167 111111111111111011111111111*  NOTE Mux-11 of block F*
-L70194 111111111111111111111111101*  NOTE Mux-10 of block F*
-L70221 111111111101111111111111111*  NOTE Mux-11 of block C*
-L70248 111111111111111111111011111*  NOTE Mux-12 of block C*
-L70275 111111111111111111110111111*  NOTE Mux-13 of block F*
-L70302 111111111111111111111011111*  NOTE Mux-12 of block F*
-L70329 111111110111111111111111111*  NOTE Mux-13 of block C*
-L70356 111111111111111111111111110*  NOTE Mux-14 of block C*
-L70383 111111111111111111111111111*  NOTE Mux-15 of block F*
-L70410 111111111111111111111111101*  NOTE Mux-14 of block F*
-L70437 111111111101111111111111111*  NOTE Mux-15 of block C*
-L70464 111111111111011111111111111*  NOTE Mux-16 of block C*
-L70491 111111111111111110111111111*  NOTE Mux-17 of block F*
-L70518 111111011111111111111111111*  NOTE Mux-16 of block F*
-L70545 111111111111011111111111111*  NOTE Mux-17 of block C*
-L70572 111111111111111111111111110*  NOTE Mux-18 of block C*
-L70599 111111111110111111111111111*  NOTE Mux-19 of block F*
-L70626 111111111111111111111110111*  NOTE Mux-18 of block F*
-L70653 111111111110111111111111111*  NOTE Mux-19 of block C*
-L70680 110111111111111111111111111*  NOTE Mux-20 of block C*
-L70707 111111111111111111111111111*  NOTE Mux-21 of block F*
-L70734 110111111111111111111111111*  NOTE Mux-20 of block F*
-L70761 111111111111111111111011111*  NOTE Mux-21 of block C*
-L70788 111111111111011111111111111*  NOTE Mux-22 of block C*
-L70815 111011111111111111111111111*  NOTE Mux-23 of block F*
-L70842 110111111111111111111111111*  NOTE Mux-22 of block F*
-L70869 111011111111111111111111111*  NOTE Mux-23 of block C*
-L70896 111111111111111111111111011*  NOTE Mux-24 of block C*
-L70923 111111111111111011111111111*  NOTE Mux-25 of block F*
+L70167 111111111101111111111111111*  NOTE Mux-11 of block F*
+L70194 111111111111111111111011111*  NOTE Mux-10 of block F*
+L70221 111111111111111111110111111*  NOTE Mux-11 of block C*
+L70248 111111111111101111111111111*  NOTE Mux-12 of block C*
+L70275 111111111111011111111111111*  NOTE Mux-13 of block F*
+L70302 110111111111111111111111111*  NOTE Mux-12 of block F*
+L70329 111111111111111111011111111*  NOTE Mux-13 of block C*
+L70356 111111111111111111111111011*  NOTE Mux-14 of block C*
+L70383 111111111101111111111111111*  NOTE Mux-15 of block F*
+L70410 111111111101111111111111111*  NOTE Mux-14 of block F*
+L70437 111111111111111110111111111*  NOTE Mux-15 of block C*
+L70464 111111111111111111111111011*  NOTE Mux-16 of block C*
+L70491 111111111011111111111111111*  NOTE Mux-17 of block F*
+L70518 111111111111011111111111111*  NOTE Mux-16 of block F*
+L70545 111111111111111110111111111*  NOTE Mux-17 of block C*
+L70572 111111111111111111111111111*  NOTE Mux-18 of block C*
+L70599 111111111111111111111111111*  NOTE Mux-19 of block F*
+L70626 111111111111111111111111111*  NOTE Mux-18 of block F*
+L70653 111111111111111111111111101*  NOTE Mux-19 of block C*
+L70680 111111111111111111111111111*  NOTE Mux-20 of block C*
+L70707 111111111111111111111110111*  NOTE Mux-21 of block F*
+L70734 011111111111111111111111111*  NOTE Mux-20 of block F*
+L70761 111111111111111111111111110*  NOTE Mux-21 of block C*
+L70788 111111111111111111111111101*  NOTE Mux-22 of block C*
+L70815 111111111111111111111111110*  NOTE Mux-23 of block F*
+L70842 111111111111111111111111111*  NOTE Mux-22 of block F*
+L70869 111110111111111111111111111*  NOTE Mux-23 of block C*
+L70896 111111111111111011111111111*  NOTE Mux-24 of block C*
+L70923 111111111111111111111111111*  NOTE Mux-25 of block F*
 L70950 111111111111111111111111111*  NOTE Mux-24 of block F*
-L70977 111011111111111111111111111*  NOTE Mux-25 of block C*
-L71004 111111111111111111111111011*  NOTE Mux-26 of block C*
-L71031 111110111111111111111111111*  NOTE Mux-27 of block F*
-L71058 111111111111101111111111111*  NOTE Mux-26 of block F*
-L71085 111111111111111111111111111*  NOTE Mux-27 of block C*
+L70977 111111111111111111101111111*  NOTE Mux-25 of block C*
+L71004 111111111111111111111111110*  NOTE Mux-26 of block C*
+L71031 111111111111111111111111111*  NOTE Mux-27 of block F*
+L71058 111111111111111111111111011*  NOTE Mux-26 of block F*
+L71085 111111111111111111110111111*  NOTE Mux-27 of block C*
 L71112 111111111111111111111101111*  NOTE Mux-28 of block C*
-L71139 111111111011111111111111111*  NOTE Mux-29 of block F*
-L71166 111111111110111111111111111*  NOTE Mux-28 of block F*
-L71193 111111111011111111111111111*  NOTE Mux-29 of block C*
-L71220 111111111111111111111101111*  NOTE Mux-30 of block C*
-L71247 111111110111111111111111111*  NOTE Mux-31 of block F*
-L71274 111111111111101111111111111*  NOTE Mux-30 of block F*
-L71301 111111111111111111111111011*  NOTE Mux-31 of block C*
+L71139 111111111111111111111111111*  NOTE Mux-29 of block F*
+L71166 111111111111111111111111111*  NOTE Mux-28 of block F*
+L71193 111111111111111111111111110*  NOTE Mux-29 of block C*
+L71220 111111111111111111111111110*  NOTE Mux-30 of block C*
+L71247 111111111111111111111111011*  NOTE Mux-31 of block F*
+L71274 111111111111111111111111011*  NOTE Mux-30 of block F*
+L71301 111111111111111111111111110*  NOTE Mux-31 of block C*
 L71328 111111111111111111111110111*  NOTE Mux-32 of block C*
-L71355 111111101111111111111111111*  NOTE Mux-33 of block F*
+L71355 111111111111111111111111011*  NOTE Mux-33 of block F*
 L71382 111111111111111111111111011*  NOTE Mux-32 of block F*
-L71409 111111111111111111111111011*  NOTE Mux-33 of block C*
+L71409 111111101111111111111111111*  NOTE Mux-33 of block C*
 L71436 111111111111111111111111111*  NOTE Mux-34 of block C*
 L71463 111111111111111111111111111*  NOTE Mux-35 of block F*
-L71490 101111111111111111111111111*  NOTE Mux-34 of block F*
+L71490 111101111111111111111111111*  NOTE Mux-34 of block F*
 L71517 111111111111111111111111011*  NOTE Mux-35 of block C*
 L71544 111111111111110111111111111*  NOTE Mux-36 of block C*
 L71571 111111111111110111111111111*  NOTE Mux-37 of block F*
@@ -1673,77 +1573,77 @@ L71733 111111111111111111111111011*  NOTE Mux-39 of block C*
 
 NOTE   UIM for block D and E*
 NOTE         0         0         0*
-L71760 111111111111011111111111111*  NOTE Mux-0 of block D*
+L71760 111111111111111111111111111*  NOTE Mux-0 of block D*
 L71787 111011111111111111111111111*  NOTE Mux-1 of block E*
-L71814 111111111111011111111111111*  NOTE Mux-0 of block E*
-L71841 111111111111111111111111011*  NOTE Mux-1 of block D*
-L71868 111111111111110111111111111*  NOTE Mux-2 of block D*
-L71895 111111111101111111111111111*  NOTE Mux-3 of block E*
-L71922 111111111111111111111101111*  NOTE Mux-2 of block E*
-L71949 111111111101111111111111111*  NOTE Mux-3 of block D*
-L71976 111110111111111111111111111*  NOTE Mux-4 of block D*
-L72003 111011111111111111111111111*  NOTE Mux-5 of block E*
-L72030 111110111111111111111111111*  NOTE Mux-4 of block E*
-L72057 111011111111111111111111111*  NOTE Mux-5 of block D*
-L72084 111111111111111111111111011*  NOTE Mux-6 of block D*
-L72111 111101111111111111111111111*  NOTE Mux-7 of block E*
+L71814 111111111111111111110111111*  NOTE Mux-0 of block E*
+L71841 111111111111111111111111110*  NOTE Mux-1 of block D*
+L71868 111011111111111111111111111*  NOTE Mux-2 of block D*
+L71895 111110111111111111111111111*  NOTE Mux-3 of block E*
+L71922 111111111111110111111111111*  NOTE Mux-2 of block E*
+L71949 111011111111111111111111111*  NOTE Mux-3 of block D*
+L71976 111111111111111111111111101*  NOTE Mux-4 of block D*
+L72003 111111111111111111111101111*  NOTE Mux-5 of block E*
+L72030 011111111111111111111111111*  NOTE Mux-4 of block E*
+L72057 111111111111111111111111111*  NOTE Mux-5 of block D*
+L72084 111111111111111011111111111*  NOTE Mux-6 of block D*
+L72111 111111011111111111111111111*  NOTE Mux-7 of block E*
 L72138 111110111111111111111111111*  NOTE Mux-6 of block E*
-L72165 111101111111111111111111111*  NOTE Mux-7 of block D*
-L72192 111111111111111111111111111*  NOTE Mux-8 of block D*
-L72219 111111111111111111111111111*  NOTE Mux-9 of block E*
-L72246 111111111111111111111111110*  NOTE Mux-8 of block E*
-L72273 111111111101111111111111111*  NOTE Mux-9 of block D*
-L72300 111111111111111111011111111*  NOTE Mux-10 of block D*
-L72327 111111111111111111111110111*  NOTE Mux-11 of block E*
-L72354 111111111111111111011111111*  NOTE Mux-10 of block E*
+L72165 111111111111111111111111110*  NOTE Mux-7 of block D*
+L72192 111111111111011111111111111*  NOTE Mux-8 of block D*
+L72219 111111111111111111111101111*  NOTE Mux-9 of block E*
+L72246 111111111111111110111111111*  NOTE Mux-8 of block E*
+L72273 111111111111111111111111111*  NOTE Mux-9 of block D*
+L72300 111111111111111111111110111*  NOTE Mux-10 of block D*
+L72327 111111111111111111111101111*  NOTE Mux-11 of block E*
+L72354 111111111101111111111111111*  NOTE Mux-10 of block E*
 L72381 111111111111110111111111111*  NOTE Mux-11 of block D*
-L72408 111111111111111111111011111*  NOTE Mux-12 of block D*
+L72408 111111111111111111111111110*  NOTE Mux-12 of block D*
 L72435 111111111111111101111111111*  NOTE Mux-13 of block E*
-L72462 111111111111111111111011111*  NOTE Mux-12 of block E*
+L72462 111111111111110111111111111*  NOTE Mux-12 of block E*
 L72489 111111111111110111111111111*  NOTE Mux-13 of block D*
-L72516 111111111111111111011111111*  NOTE Mux-14 of block D*
-L72543 111111111111111110111111111*  NOTE Mux-15 of block E*
-L72570 111111111111111111111111110*  NOTE Mux-14 of block E*
+L72516 111101111111111111111111111*  NOTE Mux-14 of block D*
+L72543 111111111111111111111011111*  NOTE Mux-15 of block E*
+L72570 111111111111011111111111111*  NOTE Mux-14 of block E*
 L72597 111111111111111111111111111*  NOTE Mux-15 of block D*
-L72624 111111111111111111111111101*  NOTE Mux-16 of block D*
-L72651 111111111111111111011111111*  NOTE Mux-17 of block E*
-L72678 111111111111111111111111101*  NOTE Mux-16 of block E*
-L72705 111111101111111111111111111*  NOTE Mux-17 of block D*
-L72732 111111111111101111111111111*  NOTE Mux-18 of block D*
-L72759 111111111110111111111111111*  NOTE Mux-19 of block E*
-L72786 111111111111101111111111111*  NOTE Mux-18 of block E*
-L72813 111111111110111111111111111*  NOTE Mux-19 of block D*
-L72840 110111111111111111111111111*  NOTE Mux-20 of block D*
-L72867 111111111111111111111111111*  NOTE Mux-21 of block E*
-L72894 110111111111111111111111111*  NOTE Mux-20 of block E*
-L72921 111111111111111111111011111*  NOTE Mux-21 of block D*
+L72624 111111111101111111111111111*  NOTE Mux-16 of block D*
+L72651 111111101111111111111111111*  NOTE Mux-17 of block E*
+L72678 111111111111111111111101111*  NOTE Mux-16 of block E*
+L72705 111111111111111111111111011*  NOTE Mux-17 of block D*
+L72732 111111111110111111111111111*  NOTE Mux-18 of block D*
+L72759 111111111111111101111111111*  NOTE Mux-19 of block E*
+L72786 111111111111111111111101111*  NOTE Mux-18 of block E*
+L72813 111111111111111111111111110*  NOTE Mux-19 of block D*
+L72840 111111111111111111111111110*  NOTE Mux-20 of block D*
+L72867 111111111111111111111110111*  NOTE Mux-21 of block E*
+L72894 111111111111111111111111101*  NOTE Mux-20 of block E*
+L72921 111111111111111111111111110*  NOTE Mux-21 of block D*
 L72948 111111111111111111111111110*  NOTE Mux-22 of block D*
-L72975 111011111111111111111111111*  NOTE Mux-23 of block E*
+L72975 111111110111111111111111111*  NOTE Mux-23 of block E*
 L73002 111111111111111111111111110*  NOTE Mux-22 of block E*
-L73029 111011111111111111111111111*  NOTE Mux-23 of block D*
-L73056 111111111111101111111111111*  NOTE Mux-24 of block D*
-L73083 111011111111111111111111111*  NOTE Mux-25 of block E*
-L73110 111111111111101111111111111*  NOTE Mux-24 of block E*
-L73137 111111101111111111111111111*  NOTE Mux-25 of block D*
+L73029 111111111111111111111111111*  NOTE Mux-23 of block D*
+L73056 111111111101111111111111111*  NOTE Mux-24 of block D*
+L73083 111111111111111101111111111*  NOTE Mux-25 of block E*
+L73110 111111111111111111011111111*  NOTE Mux-24 of block E*
+L73137 111011111111111111111111111*  NOTE Mux-25 of block D*
 L73164 111111111111111111111111111*  NOTE Mux-26 of block D*
-L73191 111111111111111111101111111*  NOTE Mux-27 of block E*
+L73191 111111111111111101111111111*  NOTE Mux-27 of block E*
 L73218 111111011111111111111111111*  NOTE Mux-26 of block E*
-L73245 111111111111111111101111111*  NOTE Mux-27 of block D*
-L73272 111111111111111111111111110*  NOTE Mux-28 of block D*
-L73299 111111111011111111111111111*  NOTE Mux-29 of block E*
+L73245 111111111111111111111111110*  NOTE Mux-27 of block D*
+L73272 111111111111111101111111111*  NOTE Mux-28 of block D*
+L73299 111111111111111111101111111*  NOTE Mux-29 of block E*
 L73326 111111111111111111111111110*  NOTE Mux-28 of block E*
-L73353 111111111111111111110111111*  NOTE Mux-29 of block D*
-L73380 111111111111111111111110111*  NOTE Mux-30 of block D*
-L73407 111111111111111111111111111*  NOTE Mux-31 of block E*
-L73434 111111111111011111111111111*  NOTE Mux-30 of block E*
+L73353 111111111111111101111111111*  NOTE Mux-29 of block D*
+L73380 111111111111111111111101111*  NOTE Mux-30 of block D*
+L73407 111101111111111111111111111*  NOTE Mux-31 of block E*
+L73434 111111111111110111111111111*  NOTE Mux-30 of block E*
 L73461 111111111111111111111111101*  NOTE Mux-31 of block D*
 L73488 111111111111111111111011111*  NOTE Mux-32 of block D*
 L73515 111111111111111111101111111*  NOTE Mux-33 of block E*
-L73542 011111111111111111111111111*  NOTE Mux-32 of block E*
-L73569 111111111111111111101111111*  NOTE Mux-33 of block D*
-L73596 111111111011111111111111111*  NOTE Mux-34 of block D*
+L73542 111110111111111111111111111*  NOTE Mux-32 of block E*
+L73569 111111111111111111111110111*  NOTE Mux-33 of block D*
+L73596 111111111111111111111111111*  NOTE Mux-34 of block D*
 L73623 111111111111111101111111111*  NOTE Mux-35 of block E*
-L73650 111111111111111111111101111*  NOTE Mux-34 of block E*
+L73650 111111111111101111111111111*  NOTE Mux-34 of block E*
 L73677 111011111111111111111111111*  NOTE Mux-35 of block D*
 L73704 111111111111110111111111111*  NOTE Mux-36 of block D*
 L73731 111111111111110111111111111*  NOTE Mux-37 of block E*
@@ -1762,12 +1662,12 @@ L73920
 101111111111111111111111111
 111111111111111110111111111
 110111111111111111111111111
-111111111111111111111111011
+111111111111111111111101111
 *
 
 NOTE  device configuration bits*
 NOTE    0         0         0         0*
-L74082 01110000000011111111000111111111*
+L74082 01110000010011111111000111111111*
 
 NOTE  Special Purpose Bits (JTAG) *
 L74114 1111*
@@ -1778,5 +1678,5 @@ L74118 1111111111111111*
 NOTE  Reserved bits *
 L74134 00*
 
-C5147*
+C4B50*
 0000
diff --git a/Compiled/sevga.pof b/Compiled/sevga.pof
index b87ec1ef5d8794c91dc3bfb105912a8d8c1cedac..18ec5c664f172e4258c53507631c8c006f7b7b5a 100644
GIT binary patch
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diff --git a/old/se-xga.sv b/old/se-xga.sv
deleted file mode 100644
index 12c0e64..0000000
--- a/old/se-xga.sv
+++ /dev/null
@@ -1,342 +0,0 @@
-/******************************************************************************
- * SE-VGA
- * Top-level module 
- * techav
- * 2021-10-12
- ******************************************************************************
- * This is ... mostly working. It has some write glitches and a vertical line
- * five pixels from the left side of the screen.
- *****************************************************************************/
-
-module sevga (
-    input wire              nReset,     // System reset signal
-    input wire              pixClk,     // 65MHz pixel clock
-    output wire             nhSync,     // HSync signal
-    output wire             nvSync,     // VSync signal
-    output wire             vidOut,     // 1-bit Monochrome video signal
-
-    output logic [14:0]     vramAddr,   // VRAM Address bus
-    inout logic [7:0]       vramData,   // VRAM Data bus
-    output wire             nvramOE,    // VRAM Read strobe
-    output wire             nvramWE,    // VRAM Write strobe
-    output wire             nvramCE0,   // VRAM Main chip select signal
-    output wire             nvramCE1,   // VRAM Alt chip select signal
-
-    input logic [23:1]      cpuAddr,    // CPU Address bus
-    input logic [15:0]      cpuData,    // CPU Data bus
-    input wire              ncpuAS,     // CPU Address Strobe signal
-    input wire              ncpuUDS,    // CPU Upper Data Strobe signal
-    input wire              ncpuLDS,    // CPU Lower Data Strobe signal
-    input wire              cpuRnW,     // CPU Read/Write select signal
-    input logic [2:0]       ramSize     // Select installed RAM size
-);
-
-/******************************************************************************
- * Initial Video Signal Timing
- * The following four functions establish the basic XGA signal timing and 
- * assert the horizontal and vertical sync signals as appropriate.
- * These functions are the minimum required for a signal presence detect test.
- *****************************************************************************/
-logic [10:0] hCount;    // 0..1343
-logic [9:0] vCount;     // 0..805
-wire nhSyncInner;
-
-// Primary video sync counters -- Now more synchronous!
-always @(negedge pixClk) begin
-    if(hCount < 11'd1343) hCount <= hCount + 11'd1;
-    else begin
-        hCount <= 11'd0;
-        if(vCount < 10'd805) vCount <= vCount + 10'd1;
-        else vCount <= 10'd0;
-    end
-end
-
-// horizontal and vertical sync signals
-always_comb begin
-    //if(hCount >= 11'd1048 && hCount < 11'd1184) nhSyncInner <= 0;
-    if(hCount >= 11'd1052 && hCount < 11'd1187) nhSyncInner <= 0;
-    else nhSyncInner <= 1;
-    nhSync <= nhSyncInner;
-
-    if(vCount >= 10'd729 && vCount < 10'd735) nvSync <= 0;
-    else nvSync <= 1;
-end
-
-/******************************************************************************
- * Useful signals
- * Here we break out a few useful signals, derived from the timing above, that
- * will help us elsewhere.
- *****************************************************************************/
-wire hActive, vActive;      // active video signals. vidout black when negated
-wire vidActive;             // active when both hActive and vActive asserted
-wire hLoad;                 // load pixel data from vram when asserted
-
-assign vidActive = hActive & vActive;
-
-always_comb begin
-    if(hCount >= 3 && hCount < 1027) hActive <= 1;
-    else hActive <= 0;
-
-    if(vCount >= 0 && vCount < 684) vActive <= 1;
-    else vActive <= 0;
-
-    if(hCount >= 0 && hCount < 1024 && vActive) hLoad <= 1;
-    else hLoad <= 0;
-end
-
-/******************************************************************************
- * Primary State Machine
- * This is the primary state machine which runs the entire system, handling
- * VRAM reads, VRAM writes, VIA writes, and idle states
- *****************************************************************************/
-
-// used to align primary state machine with horizontal counter
-wire [3:0] vSeq = hCount[3:0];
-
-// define state machine states (Gray code)
-parameter
-    S0  =   4'b0000,    // VRAM Read 0
-    S1  =   4'b0001,    // VRAM Read 1
-    S2  =   4'b0011,    // Idle
-    S3  =   4'b0010,    // VRAM Write Upper 0
-    S4  =   4'b0110,    // VRAM Write Upper 1
-    S5  =   4'b0111,    // VRAM Write Lower 0
-    S6  =   4'b0101,    // VRAM Write Lower 1
-    S7  =   4'b0100,    // VIA Write
-    S8  =   4'b1100,    // VSync (to be added later)
-    S9  =   4'b1101,    // undefined
-    S10 =   4'b1111,    // undefined
-    S11 =   4'b1110,    // undefined
-    S12 =   4'b1010,    // undefined
-    S13 =   4'b1011,    // undefined
-    S14 =   4'b1001,    // undefined
-    S15 =   4'b1000;    // undefined
-
-logic [3:0] pState;
-
-// And here is the much simplified primary state machine
-always @(negedge pixClk or negedge nReset) begin
-    if(!nReset) pState <= S2;   // resync on reset by jumping to idle state
-    else begin
-        case(pState)
-            S0: pState <= S1;   // first VRAM read state, always move to S1
-            S3: pState <= S4;   // first UDS write state, always move to S4
-            S5: pState <= S6;   // first LDS write state, always move to S6
-            /*S7: begin
-                
-                pState <= S2;
-            end*/
-            S2: begin
-                // here is where everything actually happens.
-                if(vSeq == 4'hF) pState <= S0;   // time for a read state
-                else if(cpuUWriteReq && !cpuUWriteSrv && vSeq < 4'hD) pState <= S3;
-                else if(cpuLWriteReq && !cpuLWriteSrv && vSeq < 4'hD) pState <= S5;
-                else if(cpuVIAReq    && !cpuVIASrv    && vSeq < 4'hE) pState <= S7;
-                else pState <= S2;
-            end
-            default: pState <= S2; // everyone ends up at S2 (idle)
-        endcase
-    end
-end
-
-// primary VRAM signal combination, based on the primary state machine
-always_comb begin
-    // VRAM Read Strobe
-    if((pState == S0 || pState == S1) && hLoad) nvramOE <= 0;
-    else nvramOE <= 1;
-
-    // VRAM Write Strobe
-    if(pState == S3 || pState == S5) nvramWE <= 0;
-    else nvramWE <= 1;
-    
-    // VRAM Chip Enable Signals
-    case(pState)
-        S0, S1: begin
-            if(hLoad) begin
-                nvramCE0 <= ~vidBufSel;
-                nvramCE1 <= vidBufSel;
-            end else begin
-                nvramCE0 <= 1;
-                nvramCE1 <= 1;
-            end
-        end
-        S3, S4, S5, S6: begin
-            nvramCE0 <= ~cpuBufSel;
-            nvramCE1 <= cpuBufSel;
-        end
-        default: begin
-            nvramCE0 <= 1;
-            nvramCE1 <= 1;
-        end
-    endcase
-
-    // VRAM Address Bus
-    case(pState)
-        S0, S1: begin
-            // address bus for read cycles
-            if(hLoad) begin
-                vramAddr[14:6] <= vCount[9:1];
-                vramAddr[5:0] <= hCount[9:4];
-            end else begin
-                vramAddr <= 0;
-            end
-        end
-        S3, S4: begin
-            // address bus for upper write cycles
-            vramAddr[14:1] <= cpuAddrShift;
-            vramAddr[0] <= 0;
-        end
-        S5, S6: begin
-            // address bus for lower write cycles
-            vramAddr[14:1] <= cpuAddrShift;
-            vramAddr[0] <= 1;
-        end
-        default: begin
-            // address bus for idle cycles
-            vramAddr <= 0;
-        end
-    endcase
-
-    // VRAM Data bus
-    case(pState)
-        S3, S4 : vramData <= cpuData[15:8];
-        S5, S6 : vramData <= cpuData[7:0];
-        default: vramData <= 8'hZ;
-    endcase
-end
-
-/******************************************************************************
- * Video Output Sequencing
- * Here is the primary video output shift register sequencing.
- * With these functions in place, it should be possible to strap the VRAM data
- * signals and see the strapped pattern output on screen.
- *****************************************************************************/
-logic [8:0] vidData;        // the video data we are displaying
-
-// output shift register
-always @(posedge pixClk) begin
-    if(pState == S1 && hLoad) begin
-        // store VRAM data in shift register
-        vidData[7:0] <= vramData;
-    end else if(!hCount[0] && vidActive) begin
-        // shift out video data
-        vidData[8:1] <= vidData[7:0];
-        vidData[0] <= 1;
-    end
-end
-
-// final video output
-always_comb begin
-    if(vidActive) vidOut <= ~vidData[8];
-    else vidOut <= 0;
-end
-
-/******************************************************************************
- * CPU Bus Snooping
- * Watch the CPU bus for writes to the video buffer regions of memory and write
- * that data to VRAM. VRAM write cycles can occur during vidSeq 1 through 7.
- * High-order bytes are passed to VRAM on tick states and low-order bytes are 
- * passed to VRAM on tock states. After the VRAM writes are complete, state
- * machine waits for the CPU cycle to end before returning to idle.
- *****************************************************************************/
-
-/* Main framebuffer starts $5900 below the top of RAM, alt frame buffer is
- * $8000 below the main frame buffer
- * ramSize is used to mask the CPU Address bits [21:19] to select the amount
- * of memory installed in the computer. Not all possible ramSize selections
- * are valid memory sizes when using 30-pin SIMMs in the Mac SE. 
- * They may be possible using PDS RAM expansion cards.
- * ramSize mainBuffer altBuffer ramTop+1 ramSize Valid?      Installed SIMMs
- *    $7    $3fa700    $3f2700   $400000  4.0MB    Y    [ 1MB   1MB ][ 1MB   1MB ]
- *    $6    $37a700    $372700   $380000  3.5MB    N
- *    $5    $2fa700    $2f2700   $300000  3.0MB    N
- *    $4    $27a700    $272700   $280000  2.5MB    Y    [ 1MB   1MB ][256kB 256kB]
- *    $3    $1fa700    $1f2700   $200000  2.0MB    Y    [ 1MB   1MB ][ ---   --- ]
- *    $2    $17a700    $172700   $180000  1.5MB    N  
- *    $1    $0fa700    $0f2700   $100000  1.0MB    Y    [256kB 256kB][256kB 256kB]
- *    $0    $07a700    $072700   $080000  0.5MB    Y    [256kB 256kB][ ---   --- ]
- */
-
-// keep track of pending CPU write requests and whether they have been serviced
-wire cpuUWriteReq, cpuLWriteReq, cpuVIAReq;
-reg  cpuUWriteSrv, cpuLWriteSrv, cpuVIASrv;
-wire cpuBufSel;
-wire cpuBufAddr;
-reg vidBufSel;
-wire [13:0] cpuAddrShift = cpuAddr[14:1] - 14'h1380;
-wire cpuBufRange;
-
-// these are some helpful signals that shortcut the CPU buffer & VIA addresses
-always_comb begin
-    /*if(cpuAddr[14:1] >= 14'h1380
-        && cpuAddr[14:1] < 14'h3E40) cpuBufRange <= 1;
-    else cpuBufRange <= 0;*/
-    cpuBufRange <= (cpuAddr[14:1] >= 14'h1380) & (cpuAddr[14:1] < 14'h3E40);
-    if(!ncpuAS && !cpuRnW
-            && !cpuAddr[23] && !cpuAddr[22]     // first two bits always 0
-            && !(cpuAddr[21] ^ ramSize[2])      // compare with RAM Size bits
-            && !(cpuAddr[20] ^ ramSize[1])
-            && !(cpuAddr[19] ^ ramSize[0])
-            && cpuAddr[18] && cpuAddr[17]       // next three bits always 1
-            && cpuAddr[16]                      // skip 15, it selects buffers
-            && cpuBufRange                      // only select buffer addresses
-    ) begin
-        cpuBufAddr <= 1;
-    end else begin
-        cpuBufAddr <= 0;
-    end
-    cpuBufSel <= ~cpuAddr[15];                   // address bit 15 selects buffer
-
-    if(cpuBufAddr && !ncpuUDS) cpuUWriteReq <= 1;
-    else cpuUWriteReq <= 0;
-    if(cpuBufAddr && !ncpuLDS) cpuLWriteReq <= 1;
-    else cpuLWriteReq <= 0;
-
-    // VIA is in address block $E8,0000 - $EF,FFFF
-    // VIA register select pins (RS[3:0]) are wired to cpuAddr[12:9]
-    // VIA Output Register A is selected when RS[3:0]==$F
-    /*if(!ncpuAS && !cpuRnW && !ncpuUDS
-            && cpuAddr[23] && cpuAddr[22]       // VIA Address Select
-            && cpuAddr[21] && !cpuAddr[20]
-            && cpuAddr[19]
-            && cpuAddr[12] && cpuAddr[11]       // VIA ORA
-            && cpuAddr[10] && cpuAddr[9]
-    ) cpuVIAReq <= 1;
-    else cpuVIAReq <= 0;*/
-    // Mac ROM addresses Data Register A as vBase+vBufA:
-    // $EF,E1FE + (512*15) = $EF,FFFE
-    // shift right by one because no A0 and we get $77,FFFF
-    // This bit is giving me hell, so let's expand it
-    if(ncpuAS==0 && cpuRnW==0 && ncpuUDS==0
-            && cpuAddr == 22'h77FFFF) cpuVIAReq <= 1;
-    else cpuVIAReq <= 0;
-end
-
-// if there's an active CPU request and we've reached the state for servicing
-// that CPU request, then set a flag to mark that we have serviced it
-always @(posedge pixClk or posedge ncpuAS) begin
-    if(ncpuAS) begin
-        cpuUWriteSrv <= 0;
-        cpuLWriteSrv <= 0;
-        cpuVIASrv    <= 0;
-    end else begin
-        if(ncpuAS) begin
-            cpuUWriteSrv <= 0;
-            cpuLWriteSrv <= 0;
-            cpuVIASrv    <= 0;
-        end else begin
-            if(cpuUWriteReq && pState == S3) cpuUWriteSrv <= 1;
-            if(cpuLWriteReq && pState == S5) cpuLWriteSrv <= 1;
-            if(cpuVIAReq    && pState == S7) cpuVIASrv    <= 1;
-        end
-    end
-end
-
-// store the video buffer selection bit
-always @(posedge pixClk or negedge nReset) begin
-    if(!nReset) vidBufSel <= 0;
-    // fine. no video buffer select. we use Main only.
-    //else if(pState == S7) vidBufSel <= ~cpuData[14];
-end
-
-endmodule
\ No newline at end of file
diff --git a/old/se-xga_bad.sv b/old/se-xga_bad.sv
new file mode 100644
index 0000000..e5a4cd1
--- /dev/null
+++ b/old/se-xga_bad.sv
@@ -0,0 +1,229 @@
+/******************************************************************************
+ * SE-VGA
+ * Top-level module 
+ * techav
+ * 2021-10-16
+ ******************************************************************************
+ * Trying again again again
+ *****************************************************************************/
+
+module sevga (
+    input wire              nReset,     // System reset signal
+    input wire              pixClk,     // 65MHz pixel clock
+    output reg              nhSync,     // HSync signal
+    output reg              nvSync,     // VSync signal
+    output reg              vidOut,     // 1-bit Monochrome video signal
+
+    output logic [14:0]     vramAddr,   // VRAM Address bus
+    inout logic [7:0]       vramData,   // VRAM Data bus
+    output reg              nvramOE,    // VRAM Read strobe
+    output reg              nvramWE,    // VRAM Write strobe
+    output reg              nvramCE0,   // VRAM Main chip select signal
+    output reg              nvramCE1,   // VRAM Alt chip select signal
+
+    input wire [23:1]       cpuAddr,    // CPU Address bus
+    input wire [15:0]       cpuData,    // CPU Data bus
+    input wire              ncpuAS,     // CPU Address Strobe signal
+    input wire              ncpuUDS,    // CPU Upper Data Strobe signal
+    input wire              ncpuLDS,    // CPU Lower Data Strobe signal
+    input wire              cpuRnW,     // CPU Read/Write select signal
+    input logic [2:0]       ramSize     // Select installed RAM size
+);
+
+/******************************************************************************
+ * Initial Video Signal Timing
+ * The following functions establish the basic XGA signal timing and 
+ * assert the horizontal and vertical sync signals as appropriate.
+ * These functions are the minimum required for a signal presence detect test.
+ *****************************************************************************/
+
+// Primary sync counters
+logic [10:0] hCount;    // 0..1343
+logic [9:0] vCount;     // 0..805
+always @(negedge pixClk) begin
+    if(hCount < 1343) hCount <= hCount + 11'h1;
+    else begin
+        hCount <= 0;
+        if(vCount <= 805) vCount <= vCount + 10'h1;
+        else vCount <= 0;
+    end
+end
+
+// Horizontal sync
+always @(negedge pixClk) begin
+    if(hCount == 0) nhSync <= 1;
+    else if(hCount == 1052) nhSync <= 0;
+    else if(hCount == 1186) nhSync <= 1;
+end
+
+// Vertical sync
+always @(negedge pixClk) begin
+    if(vCount == 0) nvSync <= 1;
+    else if(vCount == 729) nvSync <= 0;
+    else if(vCount == 734) nvSync <= 0;
+end
+
+/******************************************************************************
+ * Useful signals
+ * Here we break out a few useful signals, derived from the timing above, that
+ * will help us elsewhere.
+ *****************************************************************************/
+
+// Horizontal active
+reg hActive;
+always @(negedge pixClk) begin
+    if(hCount == 0) hActive <= 1;
+    else if(hCount == 1023) hActive <= 0;
+    else if(hCount == 1343) hActive <= 1;
+end
+
+// Vertical active
+reg vActive;
+always @(negedge pixClk) begin
+    if(vCount == 0) vActive <= 1;
+    else if(vCount == 683) vActive <= 0;
+    else if(vCount == 805) vActive <= 1;
+end
+
+// Horizontal fetch active
+// asserted just before active video to enable video data pre-fetch
+reg fhActive;
+always @(negedge pixClk) begin
+    if(hCount == 0) fhActive <= 1;
+    else if(hCount == 1022) fhActive <= 0;
+    else if(hCount == 1342) fhActive <= 1;
+end
+
+// Vertical fetch active
+// 
+reg fvActive;
+always @(negedge pixClk) begin
+    if(vCount == 0) fvActive <= 1;
+    else if(vCount == 684) fvActive <= 0;
+    if(vCount == 805) fvActive <= 1; 
+end
+
+// combined active signals
+wire vidActive = hActive & vActive;
+wire fetchActive = fhActive & fvActive;
+
+/******************************************************************************
+ * VRAM State Machine
+ * Coordinates VRAM load/store actions
+ *****************************************************************************/
+
+// rising edge signals: nvramWE, nvramOE, nvramCE[1:0]
+// falling edge signals: vramAddr, vramData
+
+// VRAM read signal
+//always @(posedge pixClk) begin nvramOE <= ~(hCount == 7); end
+
+// VRAM write signal
+always @(posedge pixClk) begin
+    if(hCount[3:1] == 0) nvramWE <= 1;
+    else if(hCount[3:1] == 1) nvramWE <= 0;
+    else if(hCount[3:1] == 6) nvramWE <= 1;
+end
+
+// VRAM data/address busses
+always @(negedge pixClk) begin
+    if(hCount[0] && !hCount[1]) begin
+        case(hCount[3:2])
+            3: begin
+                // start read cycle
+                vramData <= 8'hZ;
+                vramAddr[14:6] <= vCount[9:1];
+                vramAddr[5:0] <= hCount[9:4];
+            end
+            default: begin
+                // write slots
+                vramAddr[14:1] <= cpuAddr[14:1] - 14'h1380;
+                if(!ncpuUDSr && !cpuLDSsrv) begin
+                    vramAddr[0] <= 0;
+                    vramData <= cpuData[15:8];
+                end else if(!ncpuLDSr && !cpuLDSsrv) begin
+                    vramAddr[0] <= 1;
+                    vramData <= cpuData[7:0];
+                end
+            end
+        endcase
+    end
+end
+
+// VRAM chip enable signals
+reg cpuUDSsrv, cpuLDSsrv;
+always @(posedge pixClk) begin
+    if(hCount[3:1] == 7 && fetchActive) begin
+        nvramCE0 <= vidBufSel;
+        nvramCE1 <= ~vidBufSel;
+        nvramOE <= 0;
+    end else if(!hCount[0] && hCount[1]) begin
+        // write cycle
+        if(!ncpuUDSr && !cpuUDSsrv) begin
+            nvramCE0 <= ~cpuAddr[15];
+            nvramCE1 <= cpuAddr[15];
+            cpuUDSsrv <= 1;
+        end else if(!ncpuLDSr && !cpuLDSsrv) begin
+            nvramCE0 <= ~cpuAddr[15];
+            nvramCE1 <= cpuAddr[15];
+            cpuLDSsrv <= 1;
+        end else begin
+            nvramCE0 <= 1;
+            nvramCE1 <= 1;
+        end
+        nvramOE <= 1;
+    end else begin
+        nvramCE0 <= 1;
+        nvramCE1 <= 1;
+        nvramOE <= 1;
+    end
+    // reset the upper/lower serve signals when cycle ended by CPU
+    if(ncpuLDS) cpuLDSsrv <= 0;
+    if(ncpuUDS) cpuUDSsrv <= 0;
+end
+
+// Video data shift register & output
+reg [7:0] vidShiftr;
+always @(negedge pixClk) begin
+    if(hCount[3:0] == 4'hF) vidShiftr <= ~vramData;
+    else if(hCount[0]) begin
+        vidShiftr[7:1] <= vidShiftr[6:0];
+        vidShiftr[0] <= 0;
+    end
+end
+always_comb begin
+    if(vidActive) vidOut = vidShiftr[7];
+    else vidOut <= 0;
+end
+
+/******************************************************************************
+ * CPU Bus Snooping
+ * Watches the CPU bus and aligns its operations with the pixel clock
+ *****************************************************************************/
+reg ncpuUDSr, ncpuLDSr;
+always @(negedge pixClk) begin
+    // this condition evaluates true when cpu is writing to video buffer
+    if(!ncpuAS && !cpuRnW
+        && !cpuAddr[23] && !cpuAddr[22]
+        && !(cpuAddr[21] ^ ramSize[2])
+        && !(cpuAddr[20] ^ ramSize[1])
+        && !(cpuAddr[19] ^ ramSize[0])
+        && cpuAddr[18] && cpuAddr[17]
+        && cpuAddr[16]
+        && ((cpuAddr[14:1] >= 14'h1380)
+        && (cpuAddr[14:1] < 14'h3E40))) 
+    begin
+        if(!ncpuUDS) ncpuUDSr <= 0;
+        else ncpuUDSr <= 1;
+        if(!ncpuLDS) ncpuLDSr <= 0;
+        else ncpuLDSr <= 1;
+    end else begin
+        ncpuUDSr <= 1;
+        ncpuLDSr <= 1;
+    end
+end
+
+// hold low for now
+reg vidBufSel = 0;
+
+endmodule
\ No newline at end of file
diff --git a/se-xga.sv b/se-xga.sv
index e5a4cd1..12c0e64 100644
--- a/se-xga.sv
+++ b/se-xga.sv
@@ -2,27 +2,28 @@
  * SE-VGA
  * Top-level module 
  * techav
- * 2021-10-16
+ * 2021-10-12
  ******************************************************************************
- * Trying again again again
+ * This is ... mostly working. It has some write glitches and a vertical line
+ * five pixels from the left side of the screen.
  *****************************************************************************/
 
 module sevga (
     input wire              nReset,     // System reset signal
     input wire              pixClk,     // 65MHz pixel clock
-    output reg              nhSync,     // HSync signal
-    output reg              nvSync,     // VSync signal
-    output reg              vidOut,     // 1-bit Monochrome video signal
+    output wire             nhSync,     // HSync signal
+    output wire             nvSync,     // VSync signal
+    output wire             vidOut,     // 1-bit Monochrome video signal
 
     output logic [14:0]     vramAddr,   // VRAM Address bus
     inout logic [7:0]       vramData,   // VRAM Data bus
-    output reg              nvramOE,    // VRAM Read strobe
-    output reg              nvramWE,    // VRAM Write strobe
-    output reg              nvramCE0,   // VRAM Main chip select signal
-    output reg              nvramCE1,   // VRAM Alt chip select signal
+    output wire             nvramOE,    // VRAM Read strobe
+    output wire             nvramWE,    // VRAM Write strobe
+    output wire             nvramCE0,   // VRAM Main chip select signal
+    output wire             nvramCE1,   // VRAM Alt chip select signal
 
-    input wire [23:1]       cpuAddr,    // CPU Address bus
-    input wire [15:0]       cpuData,    // CPU Data bus
+    input logic [23:1]      cpuAddr,    // CPU Address bus
+    input logic [15:0]      cpuData,    // CPU Data bus
     input wire              ncpuAS,     // CPU Address Strobe signal
     input wire              ncpuUDS,    // CPU Upper Data Strobe signal
     input wire              ncpuLDS,    // CPU Lower Data Strobe signal
@@ -32,35 +33,33 @@ module sevga (
 
 /******************************************************************************
  * Initial Video Signal Timing
- * The following functions establish the basic XGA signal timing and 
+ * The following four functions establish the basic XGA signal timing and 
  * assert the horizontal and vertical sync signals as appropriate.
  * These functions are the minimum required for a signal presence detect test.
  *****************************************************************************/
-
-// Primary sync counters
 logic [10:0] hCount;    // 0..1343
 logic [9:0] vCount;     // 0..805
+wire nhSyncInner;
+
+// Primary video sync counters -- Now more synchronous!
 always @(negedge pixClk) begin
-    if(hCount < 1343) hCount <= hCount + 11'h1;
+    if(hCount < 11'd1343) hCount <= hCount + 11'd1;
     else begin
-        hCount <= 0;
-        if(vCount <= 805) vCount <= vCount + 10'h1;
-        else vCount <= 0;
+        hCount <= 11'd0;
+        if(vCount < 10'd805) vCount <= vCount + 10'd1;
+        else vCount <= 10'd0;
     end
 end
 
-// Horizontal sync
-always @(negedge pixClk) begin
-    if(hCount == 0) nhSync <= 1;
-    else if(hCount == 1052) nhSync <= 0;
-    else if(hCount == 1186) nhSync <= 1;
-end
+// horizontal and vertical sync signals
+always_comb begin
+    //if(hCount >= 11'd1048 && hCount < 11'd1184) nhSyncInner <= 0;
+    if(hCount >= 11'd1052 && hCount < 11'd1187) nhSyncInner <= 0;
+    else nhSyncInner <= 1;
+    nhSync <= nhSyncInner;
 
-// Vertical sync
-always @(negedge pixClk) begin
-    if(vCount == 0) nvSync <= 1;
-    else if(vCount == 729) nvSync <= 0;
-    else if(vCount == 734) nvSync <= 0;
+    if(vCount >= 10'd729 && vCount < 10'd735) nvSync <= 0;
+    else nvSync <= 1;
 end
 
 /******************************************************************************
@@ -68,162 +67,276 @@ end
  * Here we break out a few useful signals, derived from the timing above, that
  * will help us elsewhere.
  *****************************************************************************/
+wire hActive, vActive;      // active video signals. vidout black when negated
+wire vidActive;             // active when both hActive and vActive asserted
+wire hLoad;                 // load pixel data from vram when asserted
 
-// Horizontal active
-reg hActive;
-always @(negedge pixClk) begin
-    if(hCount == 0) hActive <= 1;
-    else if(hCount == 1023) hActive <= 0;
-    else if(hCount == 1343) hActive <= 1;
+assign vidActive = hActive & vActive;
+
+always_comb begin
+    if(hCount >= 3 && hCount < 1027) hActive <= 1;
+    else hActive <= 0;
+
+    if(vCount >= 0 && vCount < 684) vActive <= 1;
+    else vActive <= 0;
+
+    if(hCount >= 0 && hCount < 1024 && vActive) hLoad <= 1;
+    else hLoad <= 0;
 end
 
-// Vertical active
-reg vActive;
-always @(negedge pixClk) begin
-    if(vCount == 0) vActive <= 1;
-    else if(vCount == 683) vActive <= 0;
-    else if(vCount == 805) vActive <= 1;
-end
-
-// Horizontal fetch active
-// asserted just before active video to enable video data pre-fetch
-reg fhActive;
-always @(negedge pixClk) begin
-    if(hCount == 0) fhActive <= 1;
-    else if(hCount == 1022) fhActive <= 0;
-    else if(hCount == 1342) fhActive <= 1;
-end
-
-// Vertical fetch active
-// 
-reg fvActive;
-always @(negedge pixClk) begin
-    if(vCount == 0) fvActive <= 1;
-    else if(vCount == 684) fvActive <= 0;
-    if(vCount == 805) fvActive <= 1; 
-end
-
-// combined active signals
-wire vidActive = hActive & vActive;
-wire fetchActive = fhActive & fvActive;
-
 /******************************************************************************
- * VRAM State Machine
- * Coordinates VRAM load/store actions
+ * Primary State Machine
+ * This is the primary state machine which runs the entire system, handling
+ * VRAM reads, VRAM writes, VIA writes, and idle states
  *****************************************************************************/
 
-// rising edge signals: nvramWE, nvramOE, nvramCE[1:0]
-// falling edge signals: vramAddr, vramData
+// used to align primary state machine with horizontal counter
+wire [3:0] vSeq = hCount[3:0];
 
-// VRAM read signal
-//always @(posedge pixClk) begin nvramOE <= ~(hCount == 7); end
+// define state machine states (Gray code)
+parameter
+    S0  =   4'b0000,    // VRAM Read 0
+    S1  =   4'b0001,    // VRAM Read 1
+    S2  =   4'b0011,    // Idle
+    S3  =   4'b0010,    // VRAM Write Upper 0
+    S4  =   4'b0110,    // VRAM Write Upper 1
+    S5  =   4'b0111,    // VRAM Write Lower 0
+    S6  =   4'b0101,    // VRAM Write Lower 1
+    S7  =   4'b0100,    // VIA Write
+    S8  =   4'b1100,    // VSync (to be added later)
+    S9  =   4'b1101,    // undefined
+    S10 =   4'b1111,    // undefined
+    S11 =   4'b1110,    // undefined
+    S12 =   4'b1010,    // undefined
+    S13 =   4'b1011,    // undefined
+    S14 =   4'b1001,    // undefined
+    S15 =   4'b1000;    // undefined
 
-// VRAM write signal
-always @(posedge pixClk) begin
-    if(hCount[3:1] == 0) nvramWE <= 1;
-    else if(hCount[3:1] == 1) nvramWE <= 0;
-    else if(hCount[3:1] == 6) nvramWE <= 1;
-end
+logic [3:0] pState;
 
-// VRAM data/address busses
-always @(negedge pixClk) begin
-    if(hCount[0] && !hCount[1]) begin
-        case(hCount[3:2])
-            3: begin
-                // start read cycle
-                vramData <= 8'hZ;
-                vramAddr[14:6] <= vCount[9:1];
-                vramAddr[5:0] <= hCount[9:4];
-            end
-            default: begin
-                // write slots
-                vramAddr[14:1] <= cpuAddr[14:1] - 14'h1380;
-                if(!ncpuUDSr && !cpuLDSsrv) begin
-                    vramAddr[0] <= 0;
-                    vramData <= cpuData[15:8];
-                end else if(!ncpuLDSr && !cpuLDSsrv) begin
-                    vramAddr[0] <= 1;
-                    vramData <= cpuData[7:0];
-                end
+// And here is the much simplified primary state machine
+always @(negedge pixClk or negedge nReset) begin
+    if(!nReset) pState <= S2;   // resync on reset by jumping to idle state
+    else begin
+        case(pState)
+            S0: pState <= S1;   // first VRAM read state, always move to S1
+            S3: pState <= S4;   // first UDS write state, always move to S4
+            S5: pState <= S6;   // first LDS write state, always move to S6
+            /*S7: begin
+                
+                pState <= S2;
+            end*/
+            S2: begin
+                // here is where everything actually happens.
+                if(vSeq == 4'hF) pState <= S0;   // time for a read state
+                else if(cpuUWriteReq && !cpuUWriteSrv && vSeq < 4'hD) pState <= S3;
+                else if(cpuLWriteReq && !cpuLWriteSrv && vSeq < 4'hD) pState <= S5;
+                else if(cpuVIAReq    && !cpuVIASrv    && vSeq < 4'hE) pState <= S7;
+                else pState <= S2;
             end
+            default: pState <= S2; // everyone ends up at S2 (idle)
         endcase
     end
 end
 
-// VRAM chip enable signals
-reg cpuUDSsrv, cpuLDSsrv;
-always @(posedge pixClk) begin
-    if(hCount[3:1] == 7 && fetchActive) begin
-        nvramCE0 <= vidBufSel;
-        nvramCE1 <= ~vidBufSel;
-        nvramOE <= 0;
-    end else if(!hCount[0] && hCount[1]) begin
-        // write cycle
-        if(!ncpuUDSr && !cpuUDSsrv) begin
-            nvramCE0 <= ~cpuAddr[15];
-            nvramCE1 <= cpuAddr[15];
-            cpuUDSsrv <= 1;
-        end else if(!ncpuLDSr && !cpuLDSsrv) begin
-            nvramCE0 <= ~cpuAddr[15];
-            nvramCE1 <= cpuAddr[15];
-            cpuLDSsrv <= 1;
-        end else begin
+// primary VRAM signal combination, based on the primary state machine
+always_comb begin
+    // VRAM Read Strobe
+    if((pState == S0 || pState == S1) && hLoad) nvramOE <= 0;
+    else nvramOE <= 1;
+
+    // VRAM Write Strobe
+    if(pState == S3 || pState == S5) nvramWE <= 0;
+    else nvramWE <= 1;
+    
+    // VRAM Chip Enable Signals
+    case(pState)
+        S0, S1: begin
+            if(hLoad) begin
+                nvramCE0 <= ~vidBufSel;
+                nvramCE1 <= vidBufSel;
+            end else begin
+                nvramCE0 <= 1;
+                nvramCE1 <= 1;
+            end
+        end
+        S3, S4, S5, S6: begin
+            nvramCE0 <= ~cpuBufSel;
+            nvramCE1 <= cpuBufSel;
+        end
+        default: begin
             nvramCE0 <= 1;
             nvramCE1 <= 1;
         end
-        nvramOE <= 1;
-    end else begin
-        nvramCE0 <= 1;
-        nvramCE1 <= 1;
-        nvramOE <= 1;
-    end
-    // reset the upper/lower serve signals when cycle ended by CPU
-    if(ncpuLDS) cpuLDSsrv <= 0;
-    if(ncpuUDS) cpuUDSsrv <= 0;
+    endcase
+
+    // VRAM Address Bus
+    case(pState)
+        S0, S1: begin
+            // address bus for read cycles
+            if(hLoad) begin
+                vramAddr[14:6] <= vCount[9:1];
+                vramAddr[5:0] <= hCount[9:4];
+            end else begin
+                vramAddr <= 0;
+            end
+        end
+        S3, S4: begin
+            // address bus for upper write cycles
+            vramAddr[14:1] <= cpuAddrShift;
+            vramAddr[0] <= 0;
+        end
+        S5, S6: begin
+            // address bus for lower write cycles
+            vramAddr[14:1] <= cpuAddrShift;
+            vramAddr[0] <= 1;
+        end
+        default: begin
+            // address bus for idle cycles
+            vramAddr <= 0;
+        end
+    endcase
+
+    // VRAM Data bus
+    case(pState)
+        S3, S4 : vramData <= cpuData[15:8];
+        S5, S6 : vramData <= cpuData[7:0];
+        default: vramData <= 8'hZ;
+    endcase
 end
 
-// Video data shift register & output
-reg [7:0] vidShiftr;
-always @(negedge pixClk) begin
-    if(hCount[3:0] == 4'hF) vidShiftr <= ~vramData;
-    else if(hCount[0]) begin
-        vidShiftr[7:1] <= vidShiftr[6:0];
-        vidShiftr[0] <= 0;
+/******************************************************************************
+ * Video Output Sequencing
+ * Here is the primary video output shift register sequencing.
+ * With these functions in place, it should be possible to strap the VRAM data
+ * signals and see the strapped pattern output on screen.
+ *****************************************************************************/
+logic [8:0] vidData;        // the video data we are displaying
+
+// output shift register
+always @(posedge pixClk) begin
+    if(pState == S1 && hLoad) begin
+        // store VRAM data in shift register
+        vidData[7:0] <= vramData;
+    end else if(!hCount[0] && vidActive) begin
+        // shift out video data
+        vidData[8:1] <= vidData[7:0];
+        vidData[0] <= 1;
     end
 end
+
+// final video output
 always_comb begin
-    if(vidActive) vidOut = vidShiftr[7];
+    if(vidActive) vidOut <= ~vidData[8];
     else vidOut <= 0;
 end
 
 /******************************************************************************
  * CPU Bus Snooping
- * Watches the CPU bus and aligns its operations with the pixel clock
+ * Watch the CPU bus for writes to the video buffer regions of memory and write
+ * that data to VRAM. VRAM write cycles can occur during vidSeq 1 through 7.
+ * High-order bytes are passed to VRAM on tick states and low-order bytes are 
+ * passed to VRAM on tock states. After the VRAM writes are complete, state
+ * machine waits for the CPU cycle to end before returning to idle.
  *****************************************************************************/
-reg ncpuUDSr, ncpuLDSr;
-always @(negedge pixClk) begin
-    // this condition evaluates true when cpu is writing to video buffer
+
+/* Main framebuffer starts $5900 below the top of RAM, alt frame buffer is
+ * $8000 below the main frame buffer
+ * ramSize is used to mask the CPU Address bits [21:19] to select the amount
+ * of memory installed in the computer. Not all possible ramSize selections
+ * are valid memory sizes when using 30-pin SIMMs in the Mac SE. 
+ * They may be possible using PDS RAM expansion cards.
+ * ramSize mainBuffer altBuffer ramTop+1 ramSize Valid?      Installed SIMMs
+ *    $7    $3fa700    $3f2700   $400000  4.0MB    Y    [ 1MB   1MB ][ 1MB   1MB ]
+ *    $6    $37a700    $372700   $380000  3.5MB    N
+ *    $5    $2fa700    $2f2700   $300000  3.0MB    N
+ *    $4    $27a700    $272700   $280000  2.5MB    Y    [ 1MB   1MB ][256kB 256kB]
+ *    $3    $1fa700    $1f2700   $200000  2.0MB    Y    [ 1MB   1MB ][ ---   --- ]
+ *    $2    $17a700    $172700   $180000  1.5MB    N  
+ *    $1    $0fa700    $0f2700   $100000  1.0MB    Y    [256kB 256kB][256kB 256kB]
+ *    $0    $07a700    $072700   $080000  0.5MB    Y    [256kB 256kB][ ---   --- ]
+ */
+
+// keep track of pending CPU write requests and whether they have been serviced
+wire cpuUWriteReq, cpuLWriteReq, cpuVIAReq;
+reg  cpuUWriteSrv, cpuLWriteSrv, cpuVIASrv;
+wire cpuBufSel;
+wire cpuBufAddr;
+reg vidBufSel;
+wire [13:0] cpuAddrShift = cpuAddr[14:1] - 14'h1380;
+wire cpuBufRange;
+
+// these are some helpful signals that shortcut the CPU buffer & VIA addresses
+always_comb begin
+    /*if(cpuAddr[14:1] >= 14'h1380
+        && cpuAddr[14:1] < 14'h3E40) cpuBufRange <= 1;
+    else cpuBufRange <= 0;*/
+    cpuBufRange <= (cpuAddr[14:1] >= 14'h1380) & (cpuAddr[14:1] < 14'h3E40);
     if(!ncpuAS && !cpuRnW
-        && !cpuAddr[23] && !cpuAddr[22]
-        && !(cpuAddr[21] ^ ramSize[2])
-        && !(cpuAddr[20] ^ ramSize[1])
-        && !(cpuAddr[19] ^ ramSize[0])
-        && cpuAddr[18] && cpuAddr[17]
-        && cpuAddr[16]
-        && ((cpuAddr[14:1] >= 14'h1380)
-        && (cpuAddr[14:1] < 14'h3E40))) 
-    begin
-        if(!ncpuUDS) ncpuUDSr <= 0;
-        else ncpuUDSr <= 1;
-        if(!ncpuLDS) ncpuLDSr <= 0;
-        else ncpuLDSr <= 1;
+            && !cpuAddr[23] && !cpuAddr[22]     // first two bits always 0
+            && !(cpuAddr[21] ^ ramSize[2])      // compare with RAM Size bits
+            && !(cpuAddr[20] ^ ramSize[1])
+            && !(cpuAddr[19] ^ ramSize[0])
+            && cpuAddr[18] && cpuAddr[17]       // next three bits always 1
+            && cpuAddr[16]                      // skip 15, it selects buffers
+            && cpuBufRange                      // only select buffer addresses
+    ) begin
+        cpuBufAddr <= 1;
     end else begin
-        ncpuUDSr <= 1;
-        ncpuLDSr <= 1;
+        cpuBufAddr <= 0;
+    end
+    cpuBufSel <= ~cpuAddr[15];                   // address bit 15 selects buffer
+
+    if(cpuBufAddr && !ncpuUDS) cpuUWriteReq <= 1;
+    else cpuUWriteReq <= 0;
+    if(cpuBufAddr && !ncpuLDS) cpuLWriteReq <= 1;
+    else cpuLWriteReq <= 0;
+
+    // VIA is in address block $E8,0000 - $EF,FFFF
+    // VIA register select pins (RS[3:0]) are wired to cpuAddr[12:9]
+    // VIA Output Register A is selected when RS[3:0]==$F
+    /*if(!ncpuAS && !cpuRnW && !ncpuUDS
+            && cpuAddr[23] && cpuAddr[22]       // VIA Address Select
+            && cpuAddr[21] && !cpuAddr[20]
+            && cpuAddr[19]
+            && cpuAddr[12] && cpuAddr[11]       // VIA ORA
+            && cpuAddr[10] && cpuAddr[9]
+    ) cpuVIAReq <= 1;
+    else cpuVIAReq <= 0;*/
+    // Mac ROM addresses Data Register A as vBase+vBufA:
+    // $EF,E1FE + (512*15) = $EF,FFFE
+    // shift right by one because no A0 and we get $77,FFFF
+    // This bit is giving me hell, so let's expand it
+    if(ncpuAS==0 && cpuRnW==0 && ncpuUDS==0
+            && cpuAddr == 22'h77FFFF) cpuVIAReq <= 1;
+    else cpuVIAReq <= 0;
+end
+
+// if there's an active CPU request and we've reached the state for servicing
+// that CPU request, then set a flag to mark that we have serviced it
+always @(posedge pixClk or posedge ncpuAS) begin
+    if(ncpuAS) begin
+        cpuUWriteSrv <= 0;
+        cpuLWriteSrv <= 0;
+        cpuVIASrv    <= 0;
+    end else begin
+        if(ncpuAS) begin
+            cpuUWriteSrv <= 0;
+            cpuLWriteSrv <= 0;
+            cpuVIASrv    <= 0;
+        end else begin
+            if(cpuUWriteReq && pState == S3) cpuUWriteSrv <= 1;
+            if(cpuLWriteReq && pState == S5) cpuLWriteSrv <= 1;
+            if(cpuVIAReq    && pState == S7) cpuVIASrv    <= 1;
+        end
     end
 end
 
-// hold low for now
-reg vidBufSel = 0;
+// store the video buffer selection bit
+always @(posedge pixClk or negedge nReset) begin
+    if(!nReset) vidBufSel <= 0;
+    // fine. no video buffer select. we use Main only.
+    //else if(pState == S7) vidBufSel <= ~cpuData[14];
+end
 
 endmodule
\ No newline at end of file