diff --git a/old/cpusnoop.sv b/old/cpusnoop.sv
deleted file mode 100644
index b4fab32..0000000
--- a/old/cpusnoop.sv
+++ /dev/null
@@ -1,245 +0,0 @@
-/******************************************************************************
- * SE-VGA
- * CPU Bus Snoop
- * techav
- * 2021-04-06
- ******************************************************************************
- * Watches for writes to frame buffer memory addresses and copies that data
- * into VRAM
- *****************************************************************************/
-
-module cpusnoop (
-    input wire              nReset,     // System Reset signal
-    input wire              pixClock,   // 25.175MHz Pixel Clock
-    input logic [2:0]       seq,        // Sequence count (low 3 bits of hCount)
-    input logic [22:0]      cpuAddr,    // CPU Address bus
-    input logic [15:0]      cpuData,    // CPU Data bus
-    input wire              ncpuAS,     // CPU Address Strobe signal
-    input wire              ncpuUDS,    // CPU Upper Data Strobe signal
-    input wire              ncpuLDS,    // CPU Lower Data Strobe signal
-    input wire              cpuRnW,     // CPU Read/Write select signal
-    input wire              cpuClk,     // CPU Clock
-    output logic [14:0]     vramAddr,   // VRAM Address Bus
-    output logic [7:0]      vramDataOut,// VRAM Data Bus Output
-    output wire             nvramWE,    // VRAM Write strobe
-    output wire             nvramCE0,   // VRAM Main select
-    output wire             nvramCE1,   // VRAM Alt select
-    output wire             vidBufSelOut,// VRAM Video Buffer selection
-    input logic [2:0]       ramSize     // CPU RAM size selection
-);
-
-    wire pendWriteLo;           // low byte write to VRAM pending
-    wire pendWriteHi;           // high byte write to VRAM pending
-    logic [13:0] addrCache;     // store address for cpu writes to framebuffer
-    logic [7:0] dataCacheLo;    // store data for cpu writes to low byte
-    logic [7:0] dataCacheHi;    // store data for cpu writes to high byte
-    wire cpuBufSel;             // is CPU accessing frame buffer?
-    logic [2:0] cycleState;     // state machine state
-    reg cpuCycleEnded;          // mark cpu has ended its cycle
-    reg cpuCycleBufSel;         // which frame buffer was selected for the cpu cycle
-    reg vidBufSel;              // which frame buffer was selected for video output
-
-    // define state machine states
-    parameter
-        S0  =   0,
-        S1  =   1,
-        S2  =   2,
-        S3  =   3,
-        S4  =   4,
-        S5  =   5;
-    
-    // when cpu addresses the framebuffer, set our enable signal
-    /* Main framebuffer starts $5900 below the top of RAM, alt frame buffer is
-     * $8000 below the main frame buffer
-     * ramSize is used to mask the CPU Address bits [21:19] to select the amount
-     * of memory installed in the computer. Not all possible ramSize selections
-     * are valid memory sizes when using 30-pin SIMMs in the Mac SE. 
-     * They may be possible using PDS RAM expansion cards.
-     * ramSize  mainBuffer  altBuffer     ramTop+1    ramSize  Valid?       Installed SIMMs
-     *    $7     $3fa700     $3f2700       $400000     4.0MB     Y     [ 1MB   1MB ][ 1MB   1MB ]
-     *    $6     $37a700     $372700       $380000     3.5MB     N
-     *    $5     $2fa700     $2f2700       $300000     3.0MB     N
-     *    $4     $27a700     $272700       $280000     2.5MB     Y     [ 1MB   1MB ][256kB 256kB]
-     *    $3     $1fa700     $1f2700       $200000     2.0MB     Y     [ 1MB   1MB ][ ---   --- ]
-     *    $2     $17a700     $172700       $180000     1.5MB     N  
-     *    $1     $0fa700     $0f2700       $100000     1.0MB     Y     [256kB 256kB][256kB 256kB]
-     *    $0     $07a700     $072700       $080000     0.5MB     Y     [256kB 256kB][ ---   --- ]
-     */
-    always_comb begin
-        // remember cpuAddr is shifted right by one since 68000 does not output A0
-        if(cpuAddr[22:21] == 2'b00                  // initial constant
-                && ramSize == cpuAddr[20:18]        // ram size selection
-                && cpuAddr[17:15] == 3'b111         // trailing constant
-                                                    // next bit is main/alt select
-                && (cpuAddr[13:0] >= 14'h1380       // bottom of buffer range (0x2700>>1)
-                    && cpuAddr[13:0] <= 14'h3e3f)   // top of buffer range (0x7C70>>1)
-                ) begin
-            cpuBufSel <= 1'b1;
-        end else begin
-            cpuBufSel <= 1'b0;
-        end
-    end
-
-    // keep an eye out for cpu ending its cycle
-    always @(negedge pixClock or negedge nReset) begin
-        if(!nReset) cpuCycleEnded <= 0;
-        else if(cycleState == S2) cpuCycleEnded <= 0;
-        else if(ncpuUDS && ncpuLDS
-                    && (cycleState == S3 
-                        || cycleState == S4 
-                        || cycleState == S5
-                        || cycleState == S1)
-                    ) begin
-            cpuCycleEnded <= 1;
-        end else cpuCycleEnded <= cpuCycleEnded;
-    end
-    
-    // CPU Write to VRAM state machine
-    always @(negedge pixClock or negedge nReset) begin
-        if(!nReset) begin
-            cycleState <= S0;
-            pendWriteHi <= 0;
-            pendWriteLo <= 0;
-            addrCache <= 0;
-            dataCacheHi <= 0;
-            dataCacheLo <= 0;
-        end else begin
-            case (cycleState)
-                S0 : begin
-                    // idle state, wait for valid address and ncpuAS asserted
-                    if(ncpuAS == 0 
-                            && cpuBufSel == 1 
-                            && cpuRnW == 0 
-                            && (ncpuLDS == 0 
-                                || ncpuUDS == 0)) begin
-                        pendWriteHi <= !ncpuUDS;
-                        pendWriteLo <= !ncpuLDS;
-                        dataCacheHi <= cpuData[15:8];
-                        dataCacheLo <= cpuData[7:0];
-                        // Valid CPU-VRAM cycle, so subtract constant $1380 from the 
-                        // cpu address and store the result in addrCache register.
-                        // Constant $1380 corresponds to $2700 shifted right by 1.
-                        // Once the selection bits above are masked out, we're left
-                        // with buffer addresses starting at $2700
-                        // e.g. with 4MB of RAM, fram buffer starts at $3FA700
-                        //   buffer address: 0011 1111 1010 0111 0000 0000 = $3FA700
-                        //   vram addr mask: 0000 0000 0011 1111 1111 1111 - $003FFF
-                        //   vram address:   0000 0000 0010 0111 0000 0000 = $002700
-                        // Since CPU is 16-bit and does not provide A0, our cpuAddr
-                        // signals are shifted right by one, so we need to do the same
-                        // to our offset before subtracting it from cpuAddr
-                        //   offset:         0000 0000 0010 0111 0000 0000 = $002700
-                        //   shifted offset: 0000 0000 0001 0011 1000 0000 = $001380
-                        addrCache <= cpuAddr[13:0] - 14'h1380;
-                        // The next address bit selects which frame buffer the CPU
-                        // is writing to for this cycle. 1 = Main ; 0 = Alt
-                        // Invert & save for later
-                        cpuCycleBufSel <= !cpuAddr[14];
-                        
-                        cycleState <= S2;
-                    end else if(ncpuAS == 0 
-                                    && cpuRnW == 0 
-                                    && ncpuUDS == 0 
-                                    && cpuAddr[22:18] == 5'h1D 
-                                    && cpuAddr[11:7] == 5'h1F) begin
-                        // the CPU is addressing VIA Port A. We need to check what
-                        // bit 6 is set to to determine which buffer is selected
-                        // for video output. 1 = Main ; 0 = Alt
-                        vidBufSel <= !cpuData[14];
-                        // now that we've saved the buffer selection, go to state
-                        // S5 to wait for the CPU to end the bus cycle.
-                        cycleState <= S5;
-                    end else begin
-                        cycleState <= S0;
-                    end
-                end
-                S2 : begin
-                    // wait for sequence
-                    if(pendWriteLo && !seq[0]) cycleState <= S3;
-                    else if (pendWriteHi && !seq[0]) cycleState <= S4;
-                    else if (!pendWriteHi && !pendWriteLo) cycleState <= S0;    // in case something weird happens
-                    else cycleState <= S2;
-                end
-                S3 : begin
-                    // write CPU low byte to VRAM
-                    if (seq == 0) begin
-                        cycleState <= S3;   // we shouldn't be here during a read cycle, so delay
-                    end else if(pendWriteHi == 1) begin
-                        cycleState <= S1;   // move on to delay before second write cycle
-                    end else begin
-                        cycleState <= S5;
-                    end
-                    pendWriteLo <= 0;
-                end
-                S4 : begin
-                    // write CPU high byte to VRAM
-                    if (seq == 0) begin
-                        cycleState <= S4;   // we shouldn't be here during a read cycle, so delay
-                    end else begin
-                        cycleState <= S5;
-                    end
-                    pendWriteHi <= 0;
-                end
-                S5 : begin
-                    // wait for CPU to negate both ncpuUDS and ncpuLDS
-                    if(cpuCycleEnded == 1) begin
-                        cycleState <= S0;
-                    end else begin
-                        cycleState <= S5;
-                    end
-                end
-                S1 : begin
-                    // delay moving to second write cycle
-                    if (!seq[0]) cycleState <= S4;
-                    else cycleState <= S1;
-                end
-                default: begin
-                    // how did we end up here? reset to S0
-                    cycleState <= S0;
-                end
-            endcase
-        end
-    end
-
-    always_comb begin
-        // output VRAM address
-        // we actually do an endian swap here assigning the low-order bit of
-        // the VRAM address because the video shift register in the SE loads
-        // a full 16-bit word and shifts out starting with the MSB.
-        // An endian swap here ensures that when we load the VRAM for output
-        // the bits are in the right order. 
-        vramAddr[14:1] <= addrCache[13:0];
-        if(cycleState == S4) begin
-            vramAddr[0] <= 0;
-        end else begin
-            vramAddr[0] <= 1;
-        end
-
-        // Assert VRAM Write signal during CPU Cycle states S3 & S4
-        // Also assert VRAM chip enable signals based on which buffer the CPU
-        // addressed for the VRAM write cycle
-        if(seq != 0 && (cycleState == S3 || cycleState == S4)) begin
-            nvramWE <= 0;
-            nvramCE0 <= cpuCycleBufSel;
-            nvramCE1 <= !cpuCycleBufSel;
-        end else begin
-            nvramWE <= 1;
-            nvramCE0 <= 1;
-            nvramCE1 <= 1;
-        end
-
-        // Output our internal data cache registers on CPU Cycle states S3 & S4
-        // Otherwise, just output 0. This will be muxed for the VRAM data bus
-        // in the next module outside of here.
-        if(cycleState == S3) begin
-            vramDataOut <= dataCacheLo;
-        end else if(cycleState == S4) begin
-            vramDataOut <= dataCacheHi;
-        end else begin
-            vramDataOut <= 0;
-        end
-    end
-
-    assign vidBufSelOut = vidBufSel;
-
-endmodule
\ No newline at end of file
diff --git a/old/se-vga.sv b/old/se-vga.sv
deleted file mode 100644
index e039d9c..0000000
--- a/old/se-vga.sv
+++ /dev/null
@@ -1,124 +0,0 @@
-/******************************************************************************
- * SE-VGA
- * Top-level module 
- * techav
- * 2021-04-06
- ******************************************************************************
- * Pulls together all the smaller modules to form the SE-VGA adapter
- *****************************************************************************/
-
-module sevga (
-    input wire              nReset,     // System reset signal
-    input wire              pixClk,     // 25.175MHz pixel clock
-    output wire             nhSync,     // HSync signal
-    output wire             nvSync,     // VSync signal
-    output wire             vidOut,     // 1-bit Monochrome video signal
-
-    output logic [14:0]     vramAddr,   // VRAM Address bus
-    inout logic [7:0]       vramData,   // VRAM Data bus
-    output wire             nvramOE,    // VRAM Read strobe
-    output wire             nvramWE,    // VRAM Write strobe
-    output wire             nvramCE0,   // VRAM Main chip select signal
-    output wire             nvramCE1,   // VRAM Alt chip select signal
-
-    input logic [23:1]      cpuAddr,    // CPU Address bus
-    input logic [15:0]      cpuData,    // CPU Data bus
-    input wire              ncpuAS,     // CPU Address Strobe signal
-    input wire              ncpuUDS,    // CPU Upper Data Strobe signal
-    input wire              ncpuLDS,    // CPU Lower Data Strobe signal
-    input wire              cpuRnW,     // CPU Read/Write select signal
-    input logic [2:0]       ramSize     // Select installed RAM size
-);
-
-logic [9:0] hCount;
-logic [9:0] vCount;
-wire hActive;
-wire hSEActive;
-wire vActive;
-wire vSEActive;
-wire nvramWEpre;            // VRAM Write signal from cpu snoop
-wire nvramCE0pre;
-wire nvramCE1pre;
-wire vidBufSel;
-
-logic [14:0] vidVramAddr;
-logic [14:0] cpuVramAddr;
-logic [7:0] vidVramData;
-wire [7:0] cpuVramData;
-
-// link module that generates all our timing signals
-vgagen vgatiming(
-    .nReset(nReset),
-    .pixClk(pixClk),
-    .hCount(hCount),
-    .hActive(hActive),
-    .hSEActive(hSEActive),
-    .nhSync(nhSync),
-    .vCount(vCount),
-    .vActive(vActive),
-    .vSEActive(vSEActive),
-    .nvSync(nvSync)
-);
-
-// link module that fetches & outputs video data
-vgaout vidvram(
-    .pixClock(pixClk),
-    .nReset(nReset),
-    .hCount(hCount),
-    .vCount(vCount),
-    .hSEActive(hSEActive),
-    .vSEActive(vSEActive),
-    .vramData(vidVramData),
-    .vramAddr(vidVramAddr),
-    .nvramOE(nvramOE),
-    .vidOut(vidOut)
-);
-
-// link module that snoops cpu writes
-cpusnoop cpusnp(    
-    .nReset(nReset),
-    .pixClock(pixClk),
-    .seq(hCount[2:0]),
-    .cpuAddr(cpuAddr),
-    .cpuData(cpuData),
-    .ncpuAS(ncpuAS),
-    .ncpuUDS(ncpuUDS),
-    .ncpuLDS(ncpuLDS),
-    .cpuRnW(cpuRnW),
-    .cpuClk(cpuClk),
-    .vramAddr(cpuVramAddr),
-    .vramDataOut(cpuVramData),
-    .nvramWE(nvramWEpre),
-    .nvramCE0(nvramCE0pre),
-    .nvramCE1(nvramCE1pre),
-    .vidBufSelOut(vidBufSel),
-    .ramSize(ramSize)
-);
-
-always_comb begin
-    // vramAddr muxing
-    if(nvramWEpre == 1'b0) begin
-        vramAddr <= cpuVramAddr;
-    end else if(nvramOE == 0) begin
-        vramAddr <= vidVramAddr;
-    end else begin
-        vramAddr <= 0;
-    end
-end
-
-always_comb begin
-    if(nvramWEpre == 1'b0) begin
-        vramData <= cpuVramData;
-    end else begin
-        vramData <= 8'bZZZZZZZZ;
-    end
-    vidVramData <= vramData;
-end
-
-assign nvramCE0 = (nvramWEpre | nvramCE0pre) & (nvramOE | vidBufSel);
-assign nvramCE1 = (nvramWEpre | nvramCE1pre) & (nvramOE | ~vidBufSel);
-
-//assign nvramWE = nvramWEpre | pixClk;
-assign nvramWE = nvramWEpre;
-
-endmodule
\ No newline at end of file
diff --git a/old/se-xga_bad.sv b/old/se-xga_bad.sv
deleted file mode 100644
index e5a4cd1..0000000
--- a/old/se-xga_bad.sv
+++ /dev/null
@@ -1,229 +0,0 @@
-/******************************************************************************
- * SE-VGA
- * Top-level module 
- * techav
- * 2021-10-16
- ******************************************************************************
- * Trying again again again
- *****************************************************************************/
-
-module sevga (
-    input wire              nReset,     // System reset signal
-    input wire              pixClk,     // 65MHz pixel clock
-    output reg              nhSync,     // HSync signal
-    output reg              nvSync,     // VSync signal
-    output reg              vidOut,     // 1-bit Monochrome video signal
-
-    output logic [14:0]     vramAddr,   // VRAM Address bus
-    inout logic [7:0]       vramData,   // VRAM Data bus
-    output reg              nvramOE,    // VRAM Read strobe
-    output reg              nvramWE,    // VRAM Write strobe
-    output reg              nvramCE0,   // VRAM Main chip select signal
-    output reg              nvramCE1,   // VRAM Alt chip select signal
-
-    input wire [23:1]       cpuAddr,    // CPU Address bus
-    input wire [15:0]       cpuData,    // CPU Data bus
-    input wire              ncpuAS,     // CPU Address Strobe signal
-    input wire              ncpuUDS,    // CPU Upper Data Strobe signal
-    input wire              ncpuLDS,    // CPU Lower Data Strobe signal
-    input wire              cpuRnW,     // CPU Read/Write select signal
-    input logic [2:0]       ramSize     // Select installed RAM size
-);
-
-/******************************************************************************
- * Initial Video Signal Timing
- * The following functions establish the basic XGA signal timing and 
- * assert the horizontal and vertical sync signals as appropriate.
- * These functions are the minimum required for a signal presence detect test.
- *****************************************************************************/
-
-// Primary sync counters
-logic [10:0] hCount;    // 0..1343
-logic [9:0] vCount;     // 0..805
-always @(negedge pixClk) begin
-    if(hCount < 1343) hCount <= hCount + 11'h1;
-    else begin
-        hCount <= 0;
-        if(vCount <= 805) vCount <= vCount + 10'h1;
-        else vCount <= 0;
-    end
-end
-
-// Horizontal sync
-always @(negedge pixClk) begin
-    if(hCount == 0) nhSync <= 1;
-    else if(hCount == 1052) nhSync <= 0;
-    else if(hCount == 1186) nhSync <= 1;
-end
-
-// Vertical sync
-always @(negedge pixClk) begin
-    if(vCount == 0) nvSync <= 1;
-    else if(vCount == 729) nvSync <= 0;
-    else if(vCount == 734) nvSync <= 0;
-end
-
-/******************************************************************************
- * Useful signals
- * Here we break out a few useful signals, derived from the timing above, that
- * will help us elsewhere.
- *****************************************************************************/
-
-// Horizontal active
-reg hActive;
-always @(negedge pixClk) begin
-    if(hCount == 0) hActive <= 1;
-    else if(hCount == 1023) hActive <= 0;
-    else if(hCount == 1343) hActive <= 1;
-end
-
-// Vertical active
-reg vActive;
-always @(negedge pixClk) begin
-    if(vCount == 0) vActive <= 1;
-    else if(vCount == 683) vActive <= 0;
-    else if(vCount == 805) vActive <= 1;
-end
-
-// Horizontal fetch active
-// asserted just before active video to enable video data pre-fetch
-reg fhActive;
-always @(negedge pixClk) begin
-    if(hCount == 0) fhActive <= 1;
-    else if(hCount == 1022) fhActive <= 0;
-    else if(hCount == 1342) fhActive <= 1;
-end
-
-// Vertical fetch active
-// 
-reg fvActive;
-always @(negedge pixClk) begin
-    if(vCount == 0) fvActive <= 1;
-    else if(vCount == 684) fvActive <= 0;
-    if(vCount == 805) fvActive <= 1; 
-end
-
-// combined active signals
-wire vidActive = hActive & vActive;
-wire fetchActive = fhActive & fvActive;
-
-/******************************************************************************
- * VRAM State Machine
- * Coordinates VRAM load/store actions
- *****************************************************************************/
-
-// rising edge signals: nvramWE, nvramOE, nvramCE[1:0]
-// falling edge signals: vramAddr, vramData
-
-// VRAM read signal
-//always @(posedge pixClk) begin nvramOE <= ~(hCount == 7); end
-
-// VRAM write signal
-always @(posedge pixClk) begin
-    if(hCount[3:1] == 0) nvramWE <= 1;
-    else if(hCount[3:1] == 1) nvramWE <= 0;
-    else if(hCount[3:1] == 6) nvramWE <= 1;
-end
-
-// VRAM data/address busses
-always @(negedge pixClk) begin
-    if(hCount[0] && !hCount[1]) begin
-        case(hCount[3:2])
-            3: begin
-                // start read cycle
-                vramData <= 8'hZ;
-                vramAddr[14:6] <= vCount[9:1];
-                vramAddr[5:0] <= hCount[9:4];
-            end
-            default: begin
-                // write slots
-                vramAddr[14:1] <= cpuAddr[14:1] - 14'h1380;
-                if(!ncpuUDSr && !cpuLDSsrv) begin
-                    vramAddr[0] <= 0;
-                    vramData <= cpuData[15:8];
-                end else if(!ncpuLDSr && !cpuLDSsrv) begin
-                    vramAddr[0] <= 1;
-                    vramData <= cpuData[7:0];
-                end
-            end
-        endcase
-    end
-end
-
-// VRAM chip enable signals
-reg cpuUDSsrv, cpuLDSsrv;
-always @(posedge pixClk) begin
-    if(hCount[3:1] == 7 && fetchActive) begin
-        nvramCE0 <= vidBufSel;
-        nvramCE1 <= ~vidBufSel;
-        nvramOE <= 0;
-    end else if(!hCount[0] && hCount[1]) begin
-        // write cycle
-        if(!ncpuUDSr && !cpuUDSsrv) begin
-            nvramCE0 <= ~cpuAddr[15];
-            nvramCE1 <= cpuAddr[15];
-            cpuUDSsrv <= 1;
-        end else if(!ncpuLDSr && !cpuLDSsrv) begin
-            nvramCE0 <= ~cpuAddr[15];
-            nvramCE1 <= cpuAddr[15];
-            cpuLDSsrv <= 1;
-        end else begin
-            nvramCE0 <= 1;
-            nvramCE1 <= 1;
-        end
-        nvramOE <= 1;
-    end else begin
-        nvramCE0 <= 1;
-        nvramCE1 <= 1;
-        nvramOE <= 1;
-    end
-    // reset the upper/lower serve signals when cycle ended by CPU
-    if(ncpuLDS) cpuLDSsrv <= 0;
-    if(ncpuUDS) cpuUDSsrv <= 0;
-end
-
-// Video data shift register & output
-reg [7:0] vidShiftr;
-always @(negedge pixClk) begin
-    if(hCount[3:0] == 4'hF) vidShiftr <= ~vramData;
-    else if(hCount[0]) begin
-        vidShiftr[7:1] <= vidShiftr[6:0];
-        vidShiftr[0] <= 0;
-    end
-end
-always_comb begin
-    if(vidActive) vidOut = vidShiftr[7];
-    else vidOut <= 0;
-end
-
-/******************************************************************************
- * CPU Bus Snooping
- * Watches the CPU bus and aligns its operations with the pixel clock
- *****************************************************************************/
-reg ncpuUDSr, ncpuLDSr;
-always @(negedge pixClk) begin
-    // this condition evaluates true when cpu is writing to video buffer
-    if(!ncpuAS && !cpuRnW
-        && !cpuAddr[23] && !cpuAddr[22]
-        && !(cpuAddr[21] ^ ramSize[2])
-        && !(cpuAddr[20] ^ ramSize[1])
-        && !(cpuAddr[19] ^ ramSize[0])
-        && cpuAddr[18] && cpuAddr[17]
-        && cpuAddr[16]
-        && ((cpuAddr[14:1] >= 14'h1380)
-        && (cpuAddr[14:1] < 14'h3E40))) 
-    begin
-        if(!ncpuUDS) ncpuUDSr <= 0;
-        else ncpuUDSr <= 1;
-        if(!ncpuLDS) ncpuLDSr <= 0;
-        else ncpuLDSr <= 1;
-    end else begin
-        ncpuUDSr <= 1;
-        ncpuLDSr <= 1;
-    end
-end
-
-// hold low for now
-reg vidBufSel = 0;
-
-endmodule
\ No newline at end of file
diff --git a/old/sevga.vwf b/old/sevga.vwf
deleted file mode 100644
index 56e4767..0000000
--- a/old/sevga.vwf
+++ /dev/null
@@ -1,3971 +0,0 @@
-/*
-WARNING: Do NOT edit the input and output ports in this file in a text
-editor if you plan to continue editing the block that represents it in
-the Block Editor! File corruption is VERY likely to occur.
-*/
-
-/*
-Copyright (C) 1991-2013 Altera Corporation
-Your use of Altera Corporation's design tools, logic functions 
-and other software and tools, and its AMPP partner logic 
-functions, and any output files from any of the foregoing 
-(including device programming or simulation files), and any 
-associated documentation or information are expressly subject 
-to the terms and conditions of the Altera Program License 
-Subscription Agreement, Altera MegaCore Function License 
-Agreement, or other applicable license agreement, including, 
-without limitation, that your use is for the sole purpose of 
-programming logic devices manufactured by Altera and sold by 
-Altera or its authorized distributors.  Please refer to the 
-applicable agreement for further details.
-*/
-
-HEADER
-{
-	VERSION = 1;
-	TIME_UNIT = ns;
-	DATA_OFFSET = 0.0;
-	DATA_DURATION = 33000.0;
-	SIMULATION_TIME = 0.0;
-	GRID_PHASE = 0.0;
-	GRID_PERIOD = 10.0;
-	GRID_DUTY_CYCLE = 50;
-}
-
-SIGNAL("cpuAddr[1]")
-{
-	VALUE_TYPE = NINE_LEVEL_BIT;
-	SIGNAL_TYPE = SINGLE_BIT;
-	WIDTH = 1;
-	LSB_INDEX = -1;
-	DIRECTION = INPUT;
-	PARENT = "";
-}
-
-SIGNAL("cpuAddr[2]")
-{
-	VALUE_TYPE = NINE_LEVEL_BIT;
-	SIGNAL_TYPE = SINGLE_BIT;
-	WIDTH = 1;
-	LSB_INDEX = -1;
-	DIRECTION = INPUT;
-	PARENT = "";
-}
-
-SIGNAL("cpuAddr[3]")
-{
-	VALUE_TYPE = NINE_LEVEL_BIT;
-	SIGNAL_TYPE = SINGLE_BIT;
-	WIDTH = 1;
-	LSB_INDEX = -1;
-	DIRECTION = INPUT;
-	PARENT = "";
-}
-
-SIGNAL("cpuAddr[4]")
-{
-	VALUE_TYPE = NINE_LEVEL_BIT;
-	SIGNAL_TYPE = SINGLE_BIT;
-	WIDTH = 1;
-	LSB_INDEX = -1;
-	DIRECTION = INPUT;
-	PARENT = "";
-}
-
-SIGNAL("cpuAddr[5]")
-{
-	VALUE_TYPE = NINE_LEVEL_BIT;
-	SIGNAL_TYPE = SINGLE_BIT;
-	WIDTH = 1;
-	LSB_INDEX = -1;
-	DIRECTION = INPUT;
-	PARENT = "";
-}
-
-SIGNAL("cpuAddr[6]")
-{
-	VALUE_TYPE = NINE_LEVEL_BIT;
-	SIGNAL_TYPE = SINGLE_BIT;
-	WIDTH = 1;
-	LSB_INDEX = -1;
-	DIRECTION = INPUT;
-	PARENT = "";
-}
-
-SIGNAL("cpuAddr[7]")
-{
-	VALUE_TYPE = NINE_LEVEL_BIT;
-	SIGNAL_TYPE = SINGLE_BIT;
-	WIDTH = 1;
-	LSB_INDEX = -1;
-	DIRECTION = INPUT;
-	PARENT = "";
-}
-
-SIGNAL("cpuAddr[8]")
-{
-	VALUE_TYPE = NINE_LEVEL_BIT;
-	SIGNAL_TYPE = SINGLE_BIT;
-	WIDTH = 1;
-	LSB_INDEX = -1;
-	DIRECTION = INPUT;
-	PARENT = "";
-}
-
-SIGNAL("cpuAddr[9]")
-{
-	VALUE_TYPE = NINE_LEVEL_BIT;
-	SIGNAL_TYPE = SINGLE_BIT;
-	WIDTH = 1;
-	LSB_INDEX = -1;
-	DIRECTION = INPUT;
-	PARENT = "";
-}
-
-SIGNAL("cpuAddr[10]")
-{
-	VALUE_TYPE = NINE_LEVEL_BIT;
-	SIGNAL_TYPE = SINGLE_BIT;
-	WIDTH = 1;
-	LSB_INDEX = -1;
-	DIRECTION = INPUT;
-	PARENT = "";
-}
-
-SIGNAL("cpuAddr[11]")
-{
-	VALUE_TYPE = NINE_LEVEL_BIT;
-	SIGNAL_TYPE = SINGLE_BIT;
-	WIDTH = 1;
-	LSB_INDEX = -1;
-	DIRECTION = INPUT;
-	PARENT = "";
-}
-
-SIGNAL("cpuAddr[12]")
-{
-	VALUE_TYPE = NINE_LEVEL_BIT;
-	SIGNAL_TYPE = SINGLE_BIT;
-	WIDTH = 1;
-	LSB_INDEX = -1;
-	DIRECTION = INPUT;
-	PARENT = "";
-}
-
-SIGNAL("cpuAddr[13]")
-{
-	VALUE_TYPE = NINE_LEVEL_BIT;
-	SIGNAL_TYPE = SINGLE_BIT;
-	WIDTH = 1;
-	LSB_INDEX = -1;
-	DIRECTION = INPUT;
-	PARENT = "";
-}
-
-SIGNAL("cpuAddr[14]")
-{
-	VALUE_TYPE = NINE_LEVEL_BIT;
-	SIGNAL_TYPE = SINGLE_BIT;
-	WIDTH = 1;
-	LSB_INDEX = -1;
-	DIRECTION = INPUT;
-	PARENT = "";
-}
-
-SIGNAL("cpuAddr[15]")
-{
-	VALUE_TYPE = NINE_LEVEL_BIT;
-	SIGNAL_TYPE = SINGLE_BIT;
-	WIDTH = 1;
-	LSB_INDEX = -1;
-	DIRECTION = INPUT;
-	PARENT = "";
-}
-
-SIGNAL("cpuAddr[16]")
-{
-	VALUE_TYPE = NINE_LEVEL_BIT;
-	SIGNAL_TYPE = SINGLE_BIT;
-	WIDTH = 1;
-	LSB_INDEX = -1;
-	DIRECTION = INPUT;
-	PARENT = "";
-}
-
-SIGNAL("cpuAddr[17]")
-{
-	VALUE_TYPE = NINE_LEVEL_BIT;
-	SIGNAL_TYPE = SINGLE_BIT;
-	WIDTH = 1;
-	LSB_INDEX = -1;
-	DIRECTION = INPUT;
-	PARENT = "";
-}
-
-SIGNAL("cpuAddr[18]")
-{
-	VALUE_TYPE = NINE_LEVEL_BIT;
-	SIGNAL_TYPE = SINGLE_BIT;
-	WIDTH = 1;
-	LSB_INDEX = -1;
-	DIRECTION = INPUT;
-	PARENT = "";
-}
-
-SIGNAL("cpuAddr[19]")
-{
-	VALUE_TYPE = NINE_LEVEL_BIT;
-	SIGNAL_TYPE = SINGLE_BIT;
-	WIDTH = 1;
-	LSB_INDEX = -1;
-	DIRECTION = INPUT;
-	PARENT = "";
-}
-
-SIGNAL("cpuAddr[20]")
-{
-	VALUE_TYPE = NINE_LEVEL_BIT;
-	SIGNAL_TYPE = SINGLE_BIT;
-	WIDTH = 1;
-	LSB_INDEX = -1;
-	DIRECTION = INPUT;
-	PARENT = "";
-}
-
-SIGNAL("cpuAddr[21]")
-{
-	VALUE_TYPE = NINE_LEVEL_BIT;
-	SIGNAL_TYPE = SINGLE_BIT;
-	WIDTH = 1;
-	LSB_INDEX = -1;
-	DIRECTION = INPUT;
-	PARENT = "";
-}
-
-SIGNAL("cpuAddr[22]")
-{
-	VALUE_TYPE = NINE_LEVEL_BIT;
-	SIGNAL_TYPE = SINGLE_BIT;
-	WIDTH = 1;
-	LSB_INDEX = -1;
-	DIRECTION = INPUT;
-	PARENT = "";
-}
-
-SIGNAL("cpuAddr[23]")
-{
-	VALUE_TYPE = NINE_LEVEL_BIT;
-	SIGNAL_TYPE = SINGLE_BIT;
-	WIDTH = 1;
-	LSB_INDEX = -1;
-	DIRECTION = INPUT;
-	PARENT = "";
-}
-
-SIGNAL("cpuClk")
-{
-	VALUE_TYPE = NINE_LEVEL_BIT;
-	SIGNAL_TYPE = SINGLE_BIT;
-	WIDTH = 1;
-	LSB_INDEX = -1;
-	DIRECTION = INPUT;
-	PARENT = "";
-}
-
-SIGNAL("cpuData")
-{
-	VALUE_TYPE = NINE_LEVEL_BIT;
-	SIGNAL_TYPE = BUS;
-	WIDTH = 16;
-	LSB_INDEX = 0;
-	DIRECTION = INPUT;
-	PARENT = "";
-}
-
-SIGNAL("cpuData[15]")
-{
-	VALUE_TYPE = NINE_LEVEL_BIT;
-	SIGNAL_TYPE = SINGLE_BIT;
-	WIDTH = 1;
-	LSB_INDEX = -1;
-	DIRECTION = INPUT;
-	PARENT = "cpuData";
-}
-
-SIGNAL("cpuData[14]")
-{
-	VALUE_TYPE = NINE_LEVEL_BIT;
-	SIGNAL_TYPE = SINGLE_BIT;
-	WIDTH = 1;
-	LSB_INDEX = -1;
-	DIRECTION = INPUT;
-	PARENT = "cpuData";
-}
-
-SIGNAL("cpuData[13]")
-{
-	VALUE_TYPE = NINE_LEVEL_BIT;
-	SIGNAL_TYPE = SINGLE_BIT;
-	WIDTH = 1;
-	LSB_INDEX = -1;
-	DIRECTION = INPUT;
-	PARENT = "cpuData";
-}
-
-SIGNAL("cpuData[12]")
-{
-	VALUE_TYPE = NINE_LEVEL_BIT;
-	SIGNAL_TYPE = SINGLE_BIT;
-	WIDTH = 1;
-	LSB_INDEX = -1;
-	DIRECTION = INPUT;
-	PARENT = "cpuData";
-}
-
-SIGNAL("cpuData[11]")
-{
-	VALUE_TYPE = NINE_LEVEL_BIT;
-	SIGNAL_TYPE = SINGLE_BIT;
-	WIDTH = 1;
-	LSB_INDEX = -1;
-	DIRECTION = INPUT;
-	PARENT = "cpuData";
-}
-
-SIGNAL("cpuData[10]")
-{
-	VALUE_TYPE = NINE_LEVEL_BIT;
-	SIGNAL_TYPE = SINGLE_BIT;
-	WIDTH = 1;
-	LSB_INDEX = -1;
-	DIRECTION = INPUT;
-	PARENT = "cpuData";
-}
-
-SIGNAL("cpuData[9]")
-{
-	VALUE_TYPE = NINE_LEVEL_BIT;
-	SIGNAL_TYPE = SINGLE_BIT;
-	WIDTH = 1;
-	LSB_INDEX = -1;
-	DIRECTION = INPUT;
-	PARENT = "cpuData";
-}
-
-SIGNAL("cpuData[8]")
-{
-	VALUE_TYPE = NINE_LEVEL_BIT;
-	SIGNAL_TYPE = SINGLE_BIT;
-	WIDTH = 1;
-	LSB_INDEX = -1;
-	DIRECTION = INPUT;
-	PARENT = "cpuData";
-}
-
-SIGNAL("cpuData[7]")
-{
-	VALUE_TYPE = NINE_LEVEL_BIT;
-	SIGNAL_TYPE = SINGLE_BIT;
-	WIDTH = 1;
-	LSB_INDEX = -1;
-	DIRECTION = INPUT;
-	PARENT = "cpuData";
-}
-
-SIGNAL("cpuData[6]")
-{
-	VALUE_TYPE = NINE_LEVEL_BIT;
-	SIGNAL_TYPE = SINGLE_BIT;
-	WIDTH = 1;
-	LSB_INDEX = -1;
-	DIRECTION = INPUT;
-	PARENT = "cpuData";
-}
-
-SIGNAL("cpuData[5]")
-{
-	VALUE_TYPE = NINE_LEVEL_BIT;
-	SIGNAL_TYPE = SINGLE_BIT;
-	WIDTH = 1;
-	LSB_INDEX = -1;
-	DIRECTION = INPUT;
-	PARENT = "cpuData";
-}
-
-SIGNAL("cpuData[4]")
-{
-	VALUE_TYPE = NINE_LEVEL_BIT;
-	SIGNAL_TYPE = SINGLE_BIT;
-	WIDTH = 1;
-	LSB_INDEX = -1;
-	DIRECTION = INPUT;
-	PARENT = "cpuData";
-}
-
-SIGNAL("cpuData[3]")
-{
-	VALUE_TYPE = NINE_LEVEL_BIT;
-	SIGNAL_TYPE = SINGLE_BIT;
-	WIDTH = 1;
-	LSB_INDEX = -1;
-	DIRECTION = INPUT;
-	PARENT = "cpuData";
-}
-
-SIGNAL("cpuData[2]")
-{
-	VALUE_TYPE = NINE_LEVEL_BIT;
-	SIGNAL_TYPE = SINGLE_BIT;
-	WIDTH = 1;
-	LSB_INDEX = -1;
-	DIRECTION = INPUT;
-	PARENT = "cpuData";
-}
-
-SIGNAL("cpuData[1]")
-{
-	VALUE_TYPE = NINE_LEVEL_BIT;
-	SIGNAL_TYPE = SINGLE_BIT;
-	WIDTH = 1;
-	LSB_INDEX = -1;
-	DIRECTION = INPUT;
-	PARENT = "cpuData";
-}
-
-SIGNAL("cpuData[0]")
-{
-	VALUE_TYPE = NINE_LEVEL_BIT;
-	SIGNAL_TYPE = SINGLE_BIT;
-	WIDTH = 1;
-	LSB_INDEX = -1;
-	DIRECTION = INPUT;
-	PARENT = "cpuData";
-}
-
-SIGNAL("cpuRnW")
-{
-	VALUE_TYPE = NINE_LEVEL_BIT;
-	SIGNAL_TYPE = SINGLE_BIT;
-	WIDTH = 1;
-	LSB_INDEX = -1;
-	DIRECTION = INPUT;
-	PARENT = "";
-}
-
-SIGNAL("nReset")
-{
-	VALUE_TYPE = NINE_LEVEL_BIT;
-	SIGNAL_TYPE = SINGLE_BIT;
-	WIDTH = 1;
-	LSB_INDEX = -1;
-	DIRECTION = INPUT;
-	PARENT = "";
-}
-
-SIGNAL("ncpuAS")
-{
-	VALUE_TYPE = NINE_LEVEL_BIT;
-	SIGNAL_TYPE = SINGLE_BIT;
-	WIDTH = 1;
-	LSB_INDEX = -1;
-	DIRECTION = INPUT;
-	PARENT = "";
-}
-
-SIGNAL("ncpuLDS")
-{
-	VALUE_TYPE = NINE_LEVEL_BIT;
-	SIGNAL_TYPE = SINGLE_BIT;
-	WIDTH = 1;
-	LSB_INDEX = -1;
-	DIRECTION = INPUT;
-	PARENT = "";
-}
-
-SIGNAL("ncpuUDS")
-{
-	VALUE_TYPE = NINE_LEVEL_BIT;
-	SIGNAL_TYPE = SINGLE_BIT;
-	WIDTH = 1;
-	LSB_INDEX = -1;
-	DIRECTION = INPUT;
-	PARENT = "";
-}
-
-SIGNAL("nhSync")
-{
-	VALUE_TYPE = NINE_LEVEL_BIT;
-	SIGNAL_TYPE = SINGLE_BIT;
-	WIDTH = 1;
-	LSB_INDEX = -1;
-	DIRECTION = OUTPUT;
-	PARENT = "";
-}
-
-SIGNAL("nvSync")
-{
-	VALUE_TYPE = NINE_LEVEL_BIT;
-	SIGNAL_TYPE = SINGLE_BIT;
-	WIDTH = 1;
-	LSB_INDEX = -1;
-	DIRECTION = OUTPUT;
-	PARENT = "";
-}
-
-SIGNAL("nvramOE")
-{
-	VALUE_TYPE = NINE_LEVEL_BIT;
-	SIGNAL_TYPE = SINGLE_BIT;
-	WIDTH = 1;
-	LSB_INDEX = -1;
-	DIRECTION = OUTPUT;
-	PARENT = "";
-}
-
-SIGNAL("nvramWE")
-{
-	VALUE_TYPE = NINE_LEVEL_BIT;
-	SIGNAL_TYPE = SINGLE_BIT;
-	WIDTH = 1;
-	LSB_INDEX = -1;
-	DIRECTION = OUTPUT;
-	PARENT = "";
-}
-
-SIGNAL("pixClk")
-{
-	VALUE_TYPE = NINE_LEVEL_BIT;
-	SIGNAL_TYPE = SINGLE_BIT;
-	WIDTH = 1;
-	LSB_INDEX = -1;
-	DIRECTION = INPUT;
-	PARENT = "";
-}
-
-SIGNAL("ramSize")
-{
-	VALUE_TYPE = NINE_LEVEL_BIT;
-	SIGNAL_TYPE = BUS;
-	WIDTH = 3;
-	LSB_INDEX = 0;
-	DIRECTION = INPUT;
-	PARENT = "";
-}
-
-SIGNAL("ramSize[2]")
-{
-	VALUE_TYPE = NINE_LEVEL_BIT;
-	SIGNAL_TYPE = SINGLE_BIT;
-	WIDTH = 1;
-	LSB_INDEX = -1;
-	DIRECTION = INPUT;
-	PARENT = "ramSize";
-}
-
-SIGNAL("ramSize[1]")
-{
-	VALUE_TYPE = NINE_LEVEL_BIT;
-	SIGNAL_TYPE = SINGLE_BIT;
-	WIDTH = 1;
-	LSB_INDEX = -1;
-	DIRECTION = INPUT;
-	PARENT = "ramSize";
-}
-
-SIGNAL("ramSize[0]")
-{
-	VALUE_TYPE = NINE_LEVEL_BIT;
-	SIGNAL_TYPE = SINGLE_BIT;
-	WIDTH = 1;
-	LSB_INDEX = -1;
-	DIRECTION = INPUT;
-	PARENT = "ramSize";
-}
-
-SIGNAL("vidOut")
-{
-	VALUE_TYPE = NINE_LEVEL_BIT;
-	SIGNAL_TYPE = SINGLE_BIT;
-	WIDTH = 1;
-	LSB_INDEX = -1;
-	DIRECTION = OUTPUT;
-	PARENT = "";
-}
-
-SIGNAL("vramAddr")
-{
-	VALUE_TYPE = NINE_LEVEL_BIT;
-	SIGNAL_TYPE = BUS;
-	WIDTH = 15;
-	LSB_INDEX = 0;
-	DIRECTION = OUTPUT;
-	PARENT = "";
-}
-
-SIGNAL("vramAddr[14]")
-{
-	VALUE_TYPE = NINE_LEVEL_BIT;
-	SIGNAL_TYPE = SINGLE_BIT;
-	WIDTH = 1;
-	LSB_INDEX = -1;
-	DIRECTION = OUTPUT;
-	PARENT = "vramAddr";
-}
-
-SIGNAL("vramAddr[13]")
-{
-	VALUE_TYPE = NINE_LEVEL_BIT;
-	SIGNAL_TYPE = SINGLE_BIT;
-	WIDTH = 1;
-	LSB_INDEX = -1;
-	DIRECTION = OUTPUT;
-	PARENT = "vramAddr";
-}
-
-SIGNAL("vramAddr[12]")
-{
-	VALUE_TYPE = NINE_LEVEL_BIT;
-	SIGNAL_TYPE = SINGLE_BIT;
-	WIDTH = 1;
-	LSB_INDEX = -1;
-	DIRECTION = OUTPUT;
-	PARENT = "vramAddr";
-}
-
-SIGNAL("vramAddr[11]")
-{
-	VALUE_TYPE = NINE_LEVEL_BIT;
-	SIGNAL_TYPE = SINGLE_BIT;
-	WIDTH = 1;
-	LSB_INDEX = -1;
-	DIRECTION = OUTPUT;
-	PARENT = "vramAddr";
-}
-
-SIGNAL("vramAddr[10]")
-{
-	VALUE_TYPE = NINE_LEVEL_BIT;
-	SIGNAL_TYPE = SINGLE_BIT;
-	WIDTH = 1;
-	LSB_INDEX = -1;
-	DIRECTION = OUTPUT;
-	PARENT = "vramAddr";
-}
-
-SIGNAL("vramAddr[9]")
-{
-	VALUE_TYPE = NINE_LEVEL_BIT;
-	SIGNAL_TYPE = SINGLE_BIT;
-	WIDTH = 1;
-	LSB_INDEX = -1;
-	DIRECTION = OUTPUT;
-	PARENT = "vramAddr";
-}
-
-SIGNAL("vramAddr[8]")
-{
-	VALUE_TYPE = NINE_LEVEL_BIT;
-	SIGNAL_TYPE = SINGLE_BIT;
-	WIDTH = 1;
-	LSB_INDEX = -1;
-	DIRECTION = OUTPUT;
-	PARENT = "vramAddr";
-}
-
-SIGNAL("vramAddr[7]")
-{
-	VALUE_TYPE = NINE_LEVEL_BIT;
-	SIGNAL_TYPE = SINGLE_BIT;
-	WIDTH = 1;
-	LSB_INDEX = -1;
-	DIRECTION = OUTPUT;
-	PARENT = "vramAddr";
-}
-
-SIGNAL("vramAddr[6]")
-{
-	VALUE_TYPE = NINE_LEVEL_BIT;
-	SIGNAL_TYPE = SINGLE_BIT;
-	WIDTH = 1;
-	LSB_INDEX = -1;
-	DIRECTION = OUTPUT;
-	PARENT = "vramAddr";
-}
-
-SIGNAL("vramAddr[5]")
-{
-	VALUE_TYPE = NINE_LEVEL_BIT;
-	SIGNAL_TYPE = SINGLE_BIT;
-	WIDTH = 1;
-	LSB_INDEX = -1;
-	DIRECTION = OUTPUT;
-	PARENT = "vramAddr";
-}
-
-SIGNAL("vramAddr[4]")
-{
-	VALUE_TYPE = NINE_LEVEL_BIT;
-	SIGNAL_TYPE = SINGLE_BIT;
-	WIDTH = 1;
-	LSB_INDEX = -1;
-	DIRECTION = OUTPUT;
-	PARENT = "vramAddr";
-}
-
-SIGNAL("vramAddr[3]")
-{
-	VALUE_TYPE = NINE_LEVEL_BIT;
-	SIGNAL_TYPE = SINGLE_BIT;
-	WIDTH = 1;
-	LSB_INDEX = -1;
-	DIRECTION = OUTPUT;
-	PARENT = "vramAddr";
-}
-
-SIGNAL("vramAddr[2]")
-{
-	VALUE_TYPE = NINE_LEVEL_BIT;
-	SIGNAL_TYPE = SINGLE_BIT;
-	WIDTH = 1;
-	LSB_INDEX = -1;
-	DIRECTION = OUTPUT;
-	PARENT = "vramAddr";
-}
-
-SIGNAL("vramAddr[1]")
-{
-	VALUE_TYPE = NINE_LEVEL_BIT;
-	SIGNAL_TYPE = SINGLE_BIT;
-	WIDTH = 1;
-	LSB_INDEX = -1;
-	DIRECTION = OUTPUT;
-	PARENT = "vramAddr";
-}
-
-SIGNAL("vramAddr[0]")
-{
-	VALUE_TYPE = NINE_LEVEL_BIT;
-	SIGNAL_TYPE = SINGLE_BIT;
-	WIDTH = 1;
-	LSB_INDEX = -1;
-	DIRECTION = OUTPUT;
-	PARENT = "vramAddr";
-}
-
-SIGNAL("vramData")
-{
-	VALUE_TYPE = NINE_LEVEL_BIT;
-	SIGNAL_TYPE = BUS;
-	WIDTH = 8;
-	LSB_INDEX = 0;
-	DIRECTION = BIDIR;
-	PARENT = "";
-}
-
-SIGNAL("vramData[7]")
-{
-	VALUE_TYPE = NINE_LEVEL_BIT;
-	SIGNAL_TYPE = SINGLE_BIT;
-	WIDTH = 1;
-	LSB_INDEX = -1;
-	DIRECTION = BIDIR;
-	PARENT = "vramData";
-}
-
-SIGNAL("vramData[6]")
-{
-	VALUE_TYPE = NINE_LEVEL_BIT;
-	SIGNAL_TYPE = SINGLE_BIT;
-	WIDTH = 1;
-	LSB_INDEX = -1;
-	DIRECTION = BIDIR;
-	PARENT = "vramData";
-}
-
-SIGNAL("vramData[5]")
-{
-	VALUE_TYPE = NINE_LEVEL_BIT;
-	SIGNAL_TYPE = SINGLE_BIT;
-	WIDTH = 1;
-	LSB_INDEX = -1;
-	DIRECTION = BIDIR;
-	PARENT = "vramData";
-}
-
-SIGNAL("vramData[4]")
-{
-	VALUE_TYPE = NINE_LEVEL_BIT;
-	SIGNAL_TYPE = SINGLE_BIT;
-	WIDTH = 1;
-	LSB_INDEX = -1;
-	DIRECTION = BIDIR;
-	PARENT = "vramData";
-}
-
-SIGNAL("vramData[3]")
-{
-	VALUE_TYPE = NINE_LEVEL_BIT;
-	SIGNAL_TYPE = SINGLE_BIT;
-	WIDTH = 1;
-	LSB_INDEX = -1;
-	DIRECTION = BIDIR;
-	PARENT = "vramData";
-}
-
-SIGNAL("vramData[2]")
-{
-	VALUE_TYPE = NINE_LEVEL_BIT;
-	SIGNAL_TYPE = SINGLE_BIT;
-	WIDTH = 1;
-	LSB_INDEX = -1;
-	DIRECTION = BIDIR;
-	PARENT = "vramData";
-}
-
-SIGNAL("vramData[1]")
-{
-	VALUE_TYPE = NINE_LEVEL_BIT;
-	SIGNAL_TYPE = SINGLE_BIT;
-	WIDTH = 1;
-	LSB_INDEX = -1;
-	DIRECTION = BIDIR;
-	PARENT = "vramData";
-}
-
-SIGNAL("vramData[0]")
-{
-	VALUE_TYPE = NINE_LEVEL_BIT;
-	SIGNAL_TYPE = SINGLE_BIT;
-	WIDTH = 1;
-	LSB_INDEX = -1;
-	DIRECTION = BIDIR;
-	PARENT = "vramData";
-}
-
-SIGNAL("cpusnoop:cpusnp|addrCache")
-{
-	VALUE_TYPE = NINE_LEVEL_BIT;
-	SIGNAL_TYPE = BUS;
-	WIDTH = 14;
-	LSB_INDEX = 0;
-	DIRECTION = REGISTERED;
-	PARENT = "";
-}
-
-SIGNAL("cpusnoop:cpusnp|addrCache[13]")
-{
-	VALUE_TYPE = NINE_LEVEL_BIT;
-	SIGNAL_TYPE = SINGLE_BIT;
-	WIDTH = 1;
-	LSB_INDEX = -1;
-	DIRECTION = REGISTERED;
-	PARENT = "cpusnoop:cpusnp|addrCache";
-}
-
-SIGNAL("cpusnoop:cpusnp|addrCache[12]")
-{
-	VALUE_TYPE = NINE_LEVEL_BIT;
-	SIGNAL_TYPE = SINGLE_BIT;
-	WIDTH = 1;
-	LSB_INDEX = -1;
-	DIRECTION = REGISTERED;
-	PARENT = "cpusnoop:cpusnp|addrCache";
-}
-
-SIGNAL("cpusnoop:cpusnp|addrCache[11]")
-{
-	VALUE_TYPE = NINE_LEVEL_BIT;
-	SIGNAL_TYPE = SINGLE_BIT;
-	WIDTH = 1;
-	LSB_INDEX = -1;
-	DIRECTION = REGISTERED;
-	PARENT = "cpusnoop:cpusnp|addrCache";
-}
-
-SIGNAL("cpusnoop:cpusnp|addrCache[10]")
-{
-	VALUE_TYPE = NINE_LEVEL_BIT;
-	SIGNAL_TYPE = SINGLE_BIT;
-	WIDTH = 1;
-	LSB_INDEX = -1;
-	DIRECTION = REGISTERED;
-	PARENT = "cpusnoop:cpusnp|addrCache";
-}
-
-SIGNAL("cpusnoop:cpusnp|addrCache[9]")
-{
-	VALUE_TYPE = NINE_LEVEL_BIT;
-	SIGNAL_TYPE = SINGLE_BIT;
-	WIDTH = 1;
-	LSB_INDEX = -1;
-	DIRECTION = REGISTERED;
-	PARENT = "cpusnoop:cpusnp|addrCache";
-}
-
-SIGNAL("cpusnoop:cpusnp|addrCache[8]")
-{
-	VALUE_TYPE = NINE_LEVEL_BIT;
-	SIGNAL_TYPE = SINGLE_BIT;
-	WIDTH = 1;
-	LSB_INDEX = -1;
-	DIRECTION = REGISTERED;
-	PARENT = "cpusnoop:cpusnp|addrCache";
-}
-
-SIGNAL("cpusnoop:cpusnp|addrCache[7]")
-{
-	VALUE_TYPE = NINE_LEVEL_BIT;
-	SIGNAL_TYPE = SINGLE_BIT;
-	WIDTH = 1;
-	LSB_INDEX = -1;
-	DIRECTION = REGISTERED;
-	PARENT = "cpusnoop:cpusnp|addrCache";
-}
-
-SIGNAL("cpusnoop:cpusnp|addrCache[6]")
-{
-	VALUE_TYPE = NINE_LEVEL_BIT;
-	SIGNAL_TYPE = SINGLE_BIT;
-	WIDTH = 1;
-	LSB_INDEX = -1;
-	DIRECTION = REGISTERED;
-	PARENT = "cpusnoop:cpusnp|addrCache";
-}
-
-SIGNAL("cpusnoop:cpusnp|addrCache[5]")
-{
-	VALUE_TYPE = NINE_LEVEL_BIT;
-	SIGNAL_TYPE = SINGLE_BIT;
-	WIDTH = 1;
-	LSB_INDEX = -1;
-	DIRECTION = REGISTERED;
-	PARENT = "cpusnoop:cpusnp|addrCache";
-}
-
-SIGNAL("cpusnoop:cpusnp|addrCache[4]")
-{
-	VALUE_TYPE = NINE_LEVEL_BIT;
-	SIGNAL_TYPE = SINGLE_BIT;
-	WIDTH = 1;
-	LSB_INDEX = -1;
-	DIRECTION = REGISTERED;
-	PARENT = "cpusnoop:cpusnp|addrCache";
-}
-
-SIGNAL("cpusnoop:cpusnp|addrCache[3]")
-{
-	VALUE_TYPE = NINE_LEVEL_BIT;
-	SIGNAL_TYPE = SINGLE_BIT;
-	WIDTH = 1;
-	LSB_INDEX = -1;
-	DIRECTION = REGISTERED;
-	PARENT = "cpusnoop:cpusnp|addrCache";
-}
-
-SIGNAL("cpusnoop:cpusnp|addrCache[2]")
-{
-	VALUE_TYPE = NINE_LEVEL_BIT;
-	SIGNAL_TYPE = SINGLE_BIT;
-	WIDTH = 1;
-	LSB_INDEX = -1;
-	DIRECTION = REGISTERED;
-	PARENT = "cpusnoop:cpusnp|addrCache";
-}
-
-SIGNAL("cpusnoop:cpusnp|addrCache[1]")
-{
-	VALUE_TYPE = NINE_LEVEL_BIT;
-	SIGNAL_TYPE = SINGLE_BIT;
-	WIDTH = 1;
-	LSB_INDEX = -1;
-	DIRECTION = REGISTERED;
-	PARENT = "cpusnoop:cpusnp|addrCache";
-}
-
-SIGNAL("cpusnoop:cpusnp|addrCache[0]")
-{
-	VALUE_TYPE = NINE_LEVEL_BIT;
-	SIGNAL_TYPE = SINGLE_BIT;
-	WIDTH = 1;
-	LSB_INDEX = -1;
-	DIRECTION = REGISTERED;
-	PARENT = "cpusnoop:cpusnp|addrCache";
-}
-
-SIGNAL("cpusnoop:cpusnp|dataCacheHi")
-{
-	VALUE_TYPE = NINE_LEVEL_BIT;
-	SIGNAL_TYPE = BUS;
-	WIDTH = 8;
-	LSB_INDEX = 0;
-	DIRECTION = REGISTERED;
-	PARENT = "";
-}
-
-SIGNAL("cpusnoop:cpusnp|dataCacheHi[7]")
-{
-	VALUE_TYPE = NINE_LEVEL_BIT;
-	SIGNAL_TYPE = SINGLE_BIT;
-	WIDTH = 1;
-	LSB_INDEX = -1;
-	DIRECTION = REGISTERED;
-	PARENT = "cpusnoop:cpusnp|dataCacheHi";
-}
-
-SIGNAL("cpusnoop:cpusnp|dataCacheHi[6]")
-{
-	VALUE_TYPE = NINE_LEVEL_BIT;
-	SIGNAL_TYPE = SINGLE_BIT;
-	WIDTH = 1;
-	LSB_INDEX = -1;
-	DIRECTION = REGISTERED;
-	PARENT = "cpusnoop:cpusnp|dataCacheHi";
-}
-
-SIGNAL("cpusnoop:cpusnp|dataCacheHi[5]")
-{
-	VALUE_TYPE = NINE_LEVEL_BIT;
-	SIGNAL_TYPE = SINGLE_BIT;
-	WIDTH = 1;
-	LSB_INDEX = -1;
-	DIRECTION = REGISTERED;
-	PARENT = "cpusnoop:cpusnp|dataCacheHi";
-}
-
-SIGNAL("cpusnoop:cpusnp|dataCacheHi[4]")
-{
-	VALUE_TYPE = NINE_LEVEL_BIT;
-	SIGNAL_TYPE = SINGLE_BIT;
-	WIDTH = 1;
-	LSB_INDEX = -1;
-	DIRECTION = REGISTERED;
-	PARENT = "cpusnoop:cpusnp|dataCacheHi";
-}
-
-SIGNAL("cpusnoop:cpusnp|dataCacheHi[3]")
-{
-	VALUE_TYPE = NINE_LEVEL_BIT;
-	SIGNAL_TYPE = SINGLE_BIT;
-	WIDTH = 1;
-	LSB_INDEX = -1;
-	DIRECTION = REGISTERED;
-	PARENT = "cpusnoop:cpusnp|dataCacheHi";
-}
-
-SIGNAL("cpusnoop:cpusnp|dataCacheHi[2]")
-{
-	VALUE_TYPE = NINE_LEVEL_BIT;
-	SIGNAL_TYPE = SINGLE_BIT;
-	WIDTH = 1;
-	LSB_INDEX = -1;
-	DIRECTION = REGISTERED;
-	PARENT = "cpusnoop:cpusnp|dataCacheHi";
-}
-
-SIGNAL("cpusnoop:cpusnp|dataCacheHi[1]")
-{
-	VALUE_TYPE = NINE_LEVEL_BIT;
-	SIGNAL_TYPE = SINGLE_BIT;
-	WIDTH = 1;
-	LSB_INDEX = -1;
-	DIRECTION = REGISTERED;
-	PARENT = "cpusnoop:cpusnp|dataCacheHi";
-}
-
-SIGNAL("cpusnoop:cpusnp|dataCacheHi[0]")
-{
-	VALUE_TYPE = NINE_LEVEL_BIT;
-	SIGNAL_TYPE = SINGLE_BIT;
-	WIDTH = 1;
-	LSB_INDEX = -1;
-	DIRECTION = REGISTERED;
-	PARENT = "cpusnoop:cpusnp|dataCacheHi";
-}
-
-SIGNAL("cpusnoop:cpusnp|dataCacheLo")
-{
-	VALUE_TYPE = NINE_LEVEL_BIT;
-	SIGNAL_TYPE = BUS;
-	WIDTH = 8;
-	LSB_INDEX = 0;
-	DIRECTION = REGISTERED;
-	PARENT = "";
-}
-
-SIGNAL("cpusnoop:cpusnp|dataCacheLo[7]")
-{
-	VALUE_TYPE = NINE_LEVEL_BIT;
-	SIGNAL_TYPE = SINGLE_BIT;
-	WIDTH = 1;
-	LSB_INDEX = -1;
-	DIRECTION = REGISTERED;
-	PARENT = "cpusnoop:cpusnp|dataCacheLo";
-}
-
-SIGNAL("cpusnoop:cpusnp|dataCacheLo[6]")
-{
-	VALUE_TYPE = NINE_LEVEL_BIT;
-	SIGNAL_TYPE = SINGLE_BIT;
-	WIDTH = 1;
-	LSB_INDEX = -1;
-	DIRECTION = REGISTERED;
-	PARENT = "cpusnoop:cpusnp|dataCacheLo";
-}
-
-SIGNAL("cpusnoop:cpusnp|dataCacheLo[5]")
-{
-	VALUE_TYPE = NINE_LEVEL_BIT;
-	SIGNAL_TYPE = SINGLE_BIT;
-	WIDTH = 1;
-	LSB_INDEX = -1;
-	DIRECTION = REGISTERED;
-	PARENT = "cpusnoop:cpusnp|dataCacheLo";
-}
-
-SIGNAL("cpusnoop:cpusnp|dataCacheLo[4]")
-{
-	VALUE_TYPE = NINE_LEVEL_BIT;
-	SIGNAL_TYPE = SINGLE_BIT;
-	WIDTH = 1;
-	LSB_INDEX = -1;
-	DIRECTION = REGISTERED;
-	PARENT = "cpusnoop:cpusnp|dataCacheLo";
-}
-
-SIGNAL("cpusnoop:cpusnp|dataCacheLo[3]")
-{
-	VALUE_TYPE = NINE_LEVEL_BIT;
-	SIGNAL_TYPE = SINGLE_BIT;
-	WIDTH = 1;
-	LSB_INDEX = -1;
-	DIRECTION = REGISTERED;
-	PARENT = "cpusnoop:cpusnp|dataCacheLo";
-}
-
-SIGNAL("cpusnoop:cpusnp|dataCacheLo[2]")
-{
-	VALUE_TYPE = NINE_LEVEL_BIT;
-	SIGNAL_TYPE = SINGLE_BIT;
-	WIDTH = 1;
-	LSB_INDEX = -1;
-	DIRECTION = REGISTERED;
-	PARENT = "cpusnoop:cpusnp|dataCacheLo";
-}
-
-SIGNAL("cpusnoop:cpusnp|dataCacheLo[1]")
-{
-	VALUE_TYPE = NINE_LEVEL_BIT;
-	SIGNAL_TYPE = SINGLE_BIT;
-	WIDTH = 1;
-	LSB_INDEX = -1;
-	DIRECTION = REGISTERED;
-	PARENT = "cpusnoop:cpusnp|dataCacheLo";
-}
-
-SIGNAL("cpusnoop:cpusnp|dataCacheLo[0]")
-{
-	VALUE_TYPE = NINE_LEVEL_BIT;
-	SIGNAL_TYPE = SINGLE_BIT;
-	WIDTH = 1;
-	LSB_INDEX = -1;
-	DIRECTION = REGISTERED;
-	PARENT = "cpusnoop:cpusnp|dataCacheLo";
-}
-
-SIGNAL("cpusnoop:cpusnp|pendWriteHi")
-{
-	VALUE_TYPE = NINE_LEVEL_BIT;
-	SIGNAL_TYPE = SINGLE_BIT;
-	WIDTH = 1;
-	LSB_INDEX = -1;
-	DIRECTION = REGISTERED;
-	PARENT = "";
-}
-
-SIGNAL("cpusnoop:cpusnp|pendWriteLo")
-{
-	VALUE_TYPE = NINE_LEVEL_BIT;
-	SIGNAL_TYPE = SINGLE_BIT;
-	WIDTH = 1;
-	LSB_INDEX = -1;
-	DIRECTION = REGISTERED;
-	PARENT = "";
-}
-
-SIGNAL("nvramCE0")
-{
-	VALUE_TYPE = NINE_LEVEL_BIT;
-	SIGNAL_TYPE = SINGLE_BIT;
-	WIDTH = 1;
-	LSB_INDEX = -1;
-	DIRECTION = OUTPUT;
-	PARENT = "";
-}
-
-SIGNAL("nvramCE1")
-{
-	VALUE_TYPE = NINE_LEVEL_BIT;
-	SIGNAL_TYPE = SINGLE_BIT;
-	WIDTH = 1;
-	LSB_INDEX = -1;
-	DIRECTION = OUTPUT;
-	PARENT = "";
-}
-
-GROUP("cpuAddr")
-{
-	MEMBERS = "cpuAddr[1]", "cpuAddr[2]", "cpuAddr[3]", "cpuAddr[4]", "cpuAddr[5]", "cpuAddr[6]", "cpuAddr[7]", "cpuAddr[8]", "cpuAddr[9]", "cpuAddr[10]", "cpuAddr[11]", "cpuAddr[12]", "cpuAddr[13]", "cpuAddr[14]", "cpuAddr[15]", "cpuAddr[16]", "cpuAddr[17]", "cpuAddr[18]", "cpuAddr[19]", "cpuAddr[20]", "cpuAddr[21]", "cpuAddr[22]", "cpuAddr[23]";
-}
-
-TRANSITION_LIST("cpuAddr[1]")
-{
-	NODE
-	{
-		REPEAT = 1;
-		LEVEL 0 FOR 1280.0;
-		LEVEL 1 FOR 420.0;
-		LEVEL 0 FOR 31300.0;
-	}
-}
-
-TRANSITION_LIST("cpuAddr[2]")
-{
-	NODE
-	{
-		REPEAT = 1;
-		LEVEL 0 FOR 960.0;
-		LEVEL 1 FOR 740.0;
-		LEVEL 0 FOR 31300.0;
-	}
-}
-
-TRANSITION_LIST("cpuAddr[3]")
-{
-	NODE
-	{
-		REPEAT = 1;
-		LEVEL 0 FOR 33000.0;
-	}
-}
-
-TRANSITION_LIST("cpuAddr[4]")
-{
-	NODE
-	{
-		REPEAT = 1;
-		LEVEL 0 FOR 33000.0;
-	}
-}
-
-TRANSITION_LIST("cpuAddr[5]")
-{
-	NODE
-	{
-		REPEAT = 1;
-		LEVEL 0 FOR 600.0;
-		LEVEL 1 FOR 320.0;
-		LEVEL 0 FOR 40.0;
-		LEVEL 1 FOR 740.0;
-		LEVEL 0 FOR 31300.0;
-	}
-}
-
-TRANSITION_LIST("cpuAddr[6]")
-{
-	NODE
-	{
-		REPEAT = 1;
-		LEVEL 0 FOR 33000.0;
-	}
-}
-
-TRANSITION_LIST("cpuAddr[7]")
-{
-	NODE
-	{
-		REPEAT = 1;
-		LEVEL 0 FOR 33000.0;
-	}
-}
-
-TRANSITION_LIST("cpuAddr[8]")
-{
-	NODE
-	{
-		REPEAT = 1;
-		LEVEL 0 FOR 600.0;
-		LEVEL 1 FOR 320.0;
-		LEVEL 0 FOR 40.0;
-		LEVEL 1 FOR 740.0;
-		LEVEL 0 FOR 31300.0;
-	}
-}
-
-TRANSITION_LIST("cpuAddr[9]")
-{
-	NODE
-	{
-		REPEAT = 1;
-		LEVEL 0 FOR 600.0;
-		LEVEL 1 FOR 320.0;
-		LEVEL 0 FOR 40.0;
-		LEVEL 1 FOR 740.0;
-		LEVEL 0 FOR 31300.0;
-	}
-}
-
-TRANSITION_LIST("cpuAddr[10]")
-{
-	NODE
-	{
-		REPEAT = 1;
-		LEVEL 0 FOR 600.0;
-		LEVEL 1 FOR 320.0;
-		LEVEL 0 FOR 40.0;
-		LEVEL 1 FOR 740.0;
-		LEVEL 0 FOR 31300.0;
-	}
-}
-
-TRANSITION_LIST("cpuAddr[11]")
-{
-	NODE
-	{
-		REPEAT = 1;
-		LEVEL 0 FOR 33000.0;
-	}
-}
-
-TRANSITION_LIST("cpuAddr[12]")
-{
-	NODE
-	{
-		REPEAT = 1;
-		LEVEL 0 FOR 33000.0;
-	}
-}
-
-TRANSITION_LIST("cpuAddr[13]")
-{
-	NODE
-	{
-		REPEAT = 1;
-		LEVEL 0 FOR 600.0;
-		LEVEL 1 FOR 320.0;
-		LEVEL 0 FOR 40.0;
-		LEVEL 1 FOR 740.0;
-		LEVEL 0 FOR 31300.0;
-	}
-}
-
-TRANSITION_LIST("cpuAddr[14]")
-{
-	NODE
-	{
-		REPEAT = 1;
-		LEVEL 0 FOR 33000.0;
-	}
-}
-
-TRANSITION_LIST("cpuAddr[15]")
-{
-	NODE
-	{
-		REPEAT = 1;
-		LEVEL 0 FOR 600.0;
-		LEVEL 1 FOR 320.0;
-		LEVEL 0 FOR 40.0;
-		LEVEL 1 FOR 740.0;
-		LEVEL 0 FOR 31300.0;
-	}
-}
-
-TRANSITION_LIST("cpuAddr[16]")
-{
-	NODE
-	{
-		REPEAT = 1;
-		LEVEL 0 FOR 600.0;
-		LEVEL 1 FOR 320.0;
-		LEVEL 0 FOR 40.0;
-		LEVEL 1 FOR 740.0;
-		LEVEL 0 FOR 31300.0;
-	}
-}
-
-TRANSITION_LIST("cpuAddr[17]")
-{
-	NODE
-	{
-		REPEAT = 1;
-		LEVEL 0 FOR 600.0;
-		LEVEL 1 FOR 320.0;
-		LEVEL 0 FOR 40.0;
-		LEVEL 1 FOR 740.0;
-		LEVEL 0 FOR 31300.0;
-	}
-}
-
-TRANSITION_LIST("cpuAddr[18]")
-{
-	NODE
-	{
-		REPEAT = 1;
-		LEVEL 0 FOR 600.0;
-		LEVEL 1 FOR 320.0;
-		LEVEL 0 FOR 40.0;
-		LEVEL 1 FOR 740.0;
-		LEVEL 0 FOR 31300.0;
-	}
-}
-
-TRANSITION_LIST("cpuAddr[19]")
-{
-	NODE
-	{
-		REPEAT = 1;
-		LEVEL 0 FOR 600.0;
-		LEVEL 1 FOR 320.0;
-		LEVEL 0 FOR 40.0;
-		LEVEL 1 FOR 740.0;
-		LEVEL 0 FOR 31300.0;
-	}
-}
-
-TRANSITION_LIST("cpuAddr[20]")
-{
-	NODE
-	{
-		REPEAT = 1;
-		LEVEL 0 FOR 600.0;
-		LEVEL 1 FOR 320.0;
-		LEVEL 0 FOR 40.0;
-		LEVEL 1 FOR 740.0;
-		LEVEL 0 FOR 31300.0;
-	}
-}
-
-TRANSITION_LIST("cpuAddr[21]")
-{
-	NODE
-	{
-		REPEAT = 1;
-		LEVEL 0 FOR 600.0;
-		LEVEL 1 FOR 320.0;
-		LEVEL 0 FOR 40.0;
-		LEVEL 1 FOR 740.0;
-		LEVEL 0 FOR 31300.0;
-	}
-}
-
-TRANSITION_LIST("cpuAddr[22]")
-{
-	NODE
-	{
-		REPEAT = 1;
-		LEVEL 0 FOR 33000.0;
-	}
-}
-
-TRANSITION_LIST("cpuAddr[23]")
-{
-	NODE
-	{
-		REPEAT = 1;
-		LEVEL 0 FOR 33000.0;
-	}
-}
-
-TRANSITION_LIST("cpuClk")
-{
-	NODE
-	{
-		REPEAT = 1;
-		NODE
-		{
-			REPEAT = 264;
-			LEVEL 0 FOR 62.5;
-			LEVEL 1 FOR 62.5;
-		}
-	}
-}
-
-TRANSITION_LIST("cpuData[15]")
-{
-	NODE
-	{
-		REPEAT = 1;
-		LEVEL 0 FOR 600.0;
-		LEVEL 1 FOR 320.0;
-		LEVEL 0 FOR 40.0;
-		LEVEL 1 FOR 320.0;
-		LEVEL 0 FOR 31720.0;
-	}
-}
-
-TRANSITION_LIST("cpuData[14]")
-{
-	NODE
-	{
-		REPEAT = 1;
-		LEVEL 0 FOR 960.0;
-		LEVEL 1 FOR 740.0;
-		LEVEL 0 FOR 31300.0;
-	}
-}
-
-TRANSITION_LIST("cpuData[13]")
-{
-	NODE
-	{
-		REPEAT = 1;
-		LEVEL 0 FOR 600.0;
-		LEVEL 1 FOR 320.0;
-		LEVEL 0 FOR 360.0;
-		LEVEL 1 FOR 420.0;
-		LEVEL 0 FOR 31300.0;
-	}
-}
-
-TRANSITION_LIST("cpuData[12]")
-{
-	NODE
-	{
-		REPEAT = 1;
-		LEVEL 0 FOR 1280.0;
-		LEVEL 1 FOR 420.0;
-		LEVEL 0 FOR 31300.0;
-	}
-}
-
-TRANSITION_LIST("cpuData[11]")
-{
-	NODE
-	{
-		REPEAT = 1;
-		LEVEL 0 FOR 1280.0;
-		LEVEL 1 FOR 420.0;
-		LEVEL 0 FOR 31300.0;
-	}
-}
-
-TRANSITION_LIST("cpuData[10]")
-{
-	NODE
-	{
-		REPEAT = 1;
-		LEVEL 0 FOR 600.0;
-		LEVEL 1 FOR 320.0;
-		LEVEL 0 FOR 360.0;
-		LEVEL 1 FOR 420.0;
-		LEVEL 0 FOR 31300.0;
-	}
-}
-
-TRANSITION_LIST("cpuData[9]")
-{
-	NODE
-	{
-		REPEAT = 1;
-		LEVEL 0 FOR 960.0;
-		LEVEL 1 FOR 740.0;
-		LEVEL 0 FOR 31300.0;
-	}
-}
-
-TRANSITION_LIST("cpuData[8]")
-{
-	NODE
-	{
-		REPEAT = 1;
-		LEVEL 0 FOR 600.0;
-		LEVEL 1 FOR 320.0;
-		LEVEL 0 FOR 40.0;
-		LEVEL 1 FOR 320.0;
-		LEVEL 0 FOR 31720.0;
-	}
-}
-
-TRANSITION_LIST("cpuData[7]")
-{
-	NODE
-	{
-		REPEAT = 1;
-		LEVEL 0 FOR 600.0;
-		LEVEL 1 FOR 320.0;
-		LEVEL 0 FOR 40.0;
-		LEVEL 1 FOR 320.0;
-		LEVEL 0 FOR 31720.0;
-	}
-}
-
-TRANSITION_LIST("cpuData[6]")
-{
-	NODE
-	{
-		REPEAT = 1;
-		LEVEL 0 FOR 600.0;
-		LEVEL 1 FOR 320.0;
-		LEVEL 0 FOR 360.0;
-		LEVEL 1 FOR 420.0;
-		LEVEL 0 FOR 31300.0;
-	}
-}
-
-TRANSITION_LIST("cpuData[5]")
-{
-	NODE
-	{
-		REPEAT = 1;
-		LEVEL 0 FOR 600.0;
-		LEVEL 1 FOR 320.0;
-		LEVEL 0 FOR 32080.0;
-	}
-}
-
-TRANSITION_LIST("cpuData[4]")
-{
-	NODE
-	{
-		REPEAT = 1;
-		LEVEL 0 FOR 960.0;
-		LEVEL 1 FOR 740.0;
-		LEVEL 0 FOR 31300.0;
-	}
-}
-
-TRANSITION_LIST("cpuData[3]")
-{
-	NODE
-	{
-		REPEAT = 1;
-		LEVEL 0 FOR 1280.0;
-		LEVEL 1 FOR 420.0;
-		LEVEL 0 FOR 31300.0;
-	}
-}
-
-TRANSITION_LIST("cpuData[2]")
-{
-	NODE
-	{
-		REPEAT = 1;
-		LEVEL 0 FOR 600.0;
-		LEVEL 1 FOR 320.0;
-		LEVEL 0 FOR 40.0;
-		LEVEL 1 FOR 320.0;
-		LEVEL 0 FOR 31720.0;
-	}
-}
-
-TRANSITION_LIST("cpuData[1]")
-{
-	NODE
-	{
-		REPEAT = 1;
-		LEVEL 0 FOR 600.0;
-		LEVEL 1 FOR 320.0;
-		LEVEL 0 FOR 40.0;
-		LEVEL 1 FOR 740.0;
-		LEVEL 0 FOR 31300.0;
-	}
-}
-
-TRANSITION_LIST("cpuData[0]")
-{
-	NODE
-	{
-		REPEAT = 1;
-		LEVEL 0 FOR 600.0;
-		LEVEL 1 FOR 320.0;
-		LEVEL 0 FOR 32080.0;
-	}
-}
-
-TRANSITION_LIST("cpuRnW")
-{
-	NODE
-	{
-		REPEAT = 1;
-		LEVEL 1 FOR 600.0;
-		LEVEL 0 FOR 320.0;
-		LEVEL 1 FOR 40.0;
-		LEVEL 0 FOR 320.0;
-		LEVEL 1 FOR 20.0;
-		LEVEL 0 FOR 400.0;
-		LEVEL 1 FOR 31300.0;
-	}
-}
-
-TRANSITION_LIST("nReset")
-{
-	NODE
-	{
-		REPEAT = 1;
-		LEVEL 1 FOR 10.0;
-		LEVEL 0 FOR 20.0;
-		LEVEL 1 FOR 110.0;
-		LEVEL 0 FOR 40.0;
-		LEVEL 1 FOR 32820.0;
-	}
-}
-
-TRANSITION_LIST("ncpuAS")
-{
-	NODE
-	{
-		REPEAT = 1;
-		LEVEL 1 FOR 610.0;
-		LEVEL 0 FOR 310.0;
-		LEVEL 1 FOR 100.0;
-		LEVEL 0 FOR 260.0;
-		LEVEL 1 FOR 40.0;
-		LEVEL 0 FOR 120.0;
-		LEVEL 1 FOR 31560.0;
-	}
-}
-
-TRANSITION_LIST("ncpuLDS")
-{
-	NODE
-	{
-		REPEAT = 1;
-		LEVEL 1 FOR 760.0;
-		LEVEL 0 FOR 160.0;
-		LEVEL 1 FOR 240.0;
-		LEVEL 0 FOR 120.0;
-		LEVEL 1 FOR 31720.0;
-	}
-}
-
-TRANSITION_LIST("ncpuUDS")
-{
-	NODE
-	{
-		REPEAT = 1;
-		LEVEL 1 FOR 760.0;
-		LEVEL 0 FOR 160.0;
-		LEVEL 1 FOR 440.0;
-		LEVEL 0 FOR 80.0;
-		LEVEL 1 FOR 31560.0;
-	}
-}
-
-TRANSITION_LIST("nhSync")
-{
-	NODE
-	{
-		REPEAT = 1;
-		LEVEL X FOR 33000.0;
-	}
-}
-
-TRANSITION_LIST("nvSync")
-{
-	NODE
-	{
-		REPEAT = 1;
-		LEVEL X FOR 33000.0;
-	}
-}
-
-TRANSITION_LIST("nvramOE")
-{
-	NODE
-	{
-		REPEAT = 1;
-		LEVEL X FOR 33000.0;
-	}
-}
-
-TRANSITION_LIST("nvramWE")
-{
-	NODE
-	{
-		REPEAT = 1;
-		LEVEL X FOR 33000.0;
-	}
-}
-
-TRANSITION_LIST("pixClk")
-{
-	NODE
-	{
-		REPEAT = 1;
-		NODE
-		{
-			REPEAT = 825;
-			LEVEL 0 FOR 20.0;
-			LEVEL 1 FOR 20.0;
-		}
-	}
-}
-
-TRANSITION_LIST("ramSize[2]")
-{
-	NODE
-	{
-		REPEAT = 1;
-		LEVEL 1 FOR 33000.0;
-	}
-}
-
-TRANSITION_LIST("ramSize[1]")
-{
-	NODE
-	{
-		REPEAT = 1;
-		LEVEL 1 FOR 33000.0;
-	}
-}
-
-TRANSITION_LIST("ramSize[0]")
-{
-	NODE
-	{
-		REPEAT = 1;
-		LEVEL 1 FOR 33000.0;
-	}
-}
-
-TRANSITION_LIST("vidOut")
-{
-	NODE
-	{
-		REPEAT = 1;
-		LEVEL X FOR 33000.0;
-	}
-}
-
-TRANSITION_LIST("vramAddr[14]")
-{
-	NODE
-	{
-		REPEAT = 1;
-		LEVEL X FOR 33000.0;
-	}
-}
-
-TRANSITION_LIST("vramAddr[13]")
-{
-	NODE
-	{
-		REPEAT = 1;
-		LEVEL X FOR 33000.0;
-	}
-}
-
-TRANSITION_LIST("vramAddr[12]")
-{
-	NODE
-	{
-		REPEAT = 1;
-		LEVEL X FOR 33000.0;
-	}
-}
-
-TRANSITION_LIST("vramAddr[11]")
-{
-	NODE
-	{
-		REPEAT = 1;
-		LEVEL X FOR 33000.0;
-	}
-}
-
-TRANSITION_LIST("vramAddr[10]")
-{
-	NODE
-	{
-		REPEAT = 1;
-		LEVEL X FOR 33000.0;
-	}
-}
-
-TRANSITION_LIST("vramAddr[9]")
-{
-	NODE
-	{
-		REPEAT = 1;
-		LEVEL X FOR 33000.0;
-	}
-}
-
-TRANSITION_LIST("vramAddr[8]")
-{
-	NODE
-	{
-		REPEAT = 1;
-		LEVEL X FOR 33000.0;
-	}
-}
-
-TRANSITION_LIST("vramAddr[7]")
-{
-	NODE
-	{
-		REPEAT = 1;
-		LEVEL X FOR 33000.0;
-	}
-}
-
-TRANSITION_LIST("vramAddr[6]")
-{
-	NODE
-	{
-		REPEAT = 1;
-		LEVEL X FOR 33000.0;
-	}
-}
-
-TRANSITION_LIST("vramAddr[5]")
-{
-	NODE
-	{
-		REPEAT = 1;
-		LEVEL X FOR 33000.0;
-	}
-}
-
-TRANSITION_LIST("vramAddr[4]")
-{
-	NODE
-	{
-		REPEAT = 1;
-		LEVEL X FOR 33000.0;
-	}
-}
-
-TRANSITION_LIST("vramAddr[3]")
-{
-	NODE
-	{
-		REPEAT = 1;
-		LEVEL X FOR 33000.0;
-	}
-}
-
-TRANSITION_LIST("vramAddr[2]")
-{
-	NODE
-	{
-		REPEAT = 1;
-		LEVEL X FOR 33000.0;
-	}
-}
-
-TRANSITION_LIST("vramAddr[1]")
-{
-	NODE
-	{
-		REPEAT = 1;
-		LEVEL X FOR 33000.0;
-	}
-}
-
-TRANSITION_LIST("vramAddr[0]")
-{
-	NODE
-	{
-		REPEAT = 1;
-		LEVEL X FOR 33000.0;
-	}
-}
-
-TRANSITION_LIST("vramData[7]")
-{
-	NODE
-	{
-		REPEAT = 1;
-		LEVEL Z FOR 320.0;
-		LEVEL 1 FOR 40.0;
-		LEVEL Z FOR 240.0;
-		LEVEL 0 FOR 80.0;
-		LEVEL Z FOR 280.0;
-		LEVEL 0 FOR 40.0;
-		LEVEL Z FOR 500.0;
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-		LEVEL 0 FOR 320.0;
-		LEVEL 1 FOR 320.0;
-		LEVEL 0 FOR 640.0;
-		LEVEL 1 FOR 320.0;
-		LEVEL 0 FOR 2880.0;
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-		LEVEL 1 FOR 320.0;
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-		LEVEL 1 FOR 320.0;
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-		LEVEL 1 FOR 960.0;
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-		LEVEL 1 FOR 320.0;
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-		LEVEL 1 FOR 1920.0;
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-		LEVEL 1 FOR 640.0;
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-		LEVEL 1 FOR 320.0;
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-		LEVEL 1 FOR 640.0;
-		LEVEL 0 FOR 640.0;
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-		LEVEL 0 FOR 1920.0;
-		LEVEL 1 FOR 320.0;
-		LEVEL 0 FOR 320.0;
-		LEVEL 1 FOR 320.0;
-		LEVEL 0 FOR 320.0;
-		LEVEL 1 FOR 320.0;
-		LEVEL 0 FOR 1280.0;
-		LEVEL 1 FOR 1280.0;
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-		LEVEL 1 FOR 640.0;
-		LEVEL 0 FOR 320.0;
-		LEVEL 1 FOR 640.0;
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-		LEVEL 1 FOR 640.0;
-		LEVEL 0 FOR 640.0;
-		LEVEL 1 FOR 320.0;
-		LEVEL 0 FOR 320.0;
-		LEVEL 1 FOR 640.0;
-		LEVEL 0 FOR 320.0;
-		LEVEL 1 FOR 40.0;
-	}
-}
-
-TRANSITION_LIST("vramData[6]")
-{
-	NODE
-	{
-		REPEAT = 1;
-		LEVEL Z FOR 320.0;
-		LEVEL 0 FOR 40.0;
-		LEVEL Z FOR 240.0;
-		LEVEL 1 FOR 80.0;
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-		LEVEL 0 FOR 40.0;
-		LEVEL Z FOR 500.0;
-		LEVEL 0 FOR 740.0;
-		LEVEL 1 FOR 320.0;
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-		LEVEL 0 FOR 640.0;
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-		LEVEL 1 FOR 320.0;
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-		LEVEL 1 FOR 640.0;
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-		LEVEL 1 FOR 320.0;
-		LEVEL 0 FOR 1280.0;
-		LEVEL 1 FOR 1280.0;
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-		LEVEL 1 FOR 320.0;
-		LEVEL 0 FOR 1280.0;
-		LEVEL 1 FOR 320.0;
-		LEVEL 0 FOR 320.0;
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-		LEVEL 1 FOR 320.0;
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-		LEVEL 1 FOR 1280.0;
-		LEVEL 0 FOR 320.0;
-		LEVEL 1 FOR 320.0;
-		LEVEL 0 FOR 320.0;
-		LEVEL 1 FOR 640.0;
-		LEVEL 0 FOR 320.0;
-		LEVEL 1 FOR 320.0;
-		LEVEL 0 FOR 1280.0;
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-		LEVEL 0 FOR 320.0;
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-		LEVEL 0 FOR 1280.0;
-		LEVEL 1 FOR 320.0;
-		LEVEL 0 FOR 640.0;
-		LEVEL 1 FOR 320.0;
-		LEVEL 0 FOR 640.0;
-		LEVEL 1 FOR 640.0;
-		LEVEL 0 FOR 1600.0;
-		LEVEL 1 FOR 40.0;
-	}
-}
-
-TRANSITION_LIST("vramData[5]")
-{
-	NODE
-	{
-		REPEAT = 1;
-		LEVEL Z FOR 320.0;
-		LEVEL 0 FOR 40.0;
-		LEVEL Z FOR 240.0;
-		LEVEL 0 FOR 80.0;
-		LEVEL Z FOR 280.0;
-		LEVEL 1 FOR 40.0;
-		LEVEL Z FOR 500.0;
-		LEVEL 0 FOR 100.0;
-		LEVEL 1 FOR 320.0;
-		LEVEL 0 FOR 640.0;
-		LEVEL 1 FOR 1600.0;
-		LEVEL 0 FOR 320.0;
-		LEVEL 1 FOR 960.0;
-		LEVEL 0 FOR 320.0;
-		LEVEL 1 FOR 960.0;
-		LEVEL 0 FOR 640.0;
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-		LEVEL 0 FOR 1280.0;
-		LEVEL 1 FOR 320.0;
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-		LEVEL 1 FOR 640.0;
-		LEVEL 0 FOR 960.0;
-		LEVEL 1 FOR 1280.0;
-		LEVEL 0 FOR 640.0;
-		LEVEL 1 FOR 320.0;
-		LEVEL 0 FOR 1600.0;
-		LEVEL 1 FOR 640.0;
-		LEVEL 0 FOR 320.0;
-		LEVEL 1 FOR 320.0;
-		LEVEL 0 FOR 320.0;
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-		LEVEL 0 FOR 640.0;
-		LEVEL 1 FOR 320.0;
-		LEVEL 0 FOR 960.0;
-		LEVEL 1 FOR 320.0;
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-		LEVEL 1 FOR 320.0;
-		LEVEL 0 FOR 320.0;
-		LEVEL 1 FOR 1600.0;
-		LEVEL 0 FOR 960.0;
-		LEVEL 1 FOR 960.0;
-		LEVEL 0 FOR 320.0;
-		LEVEL 1 FOR 320.0;
-		LEVEL 0 FOR 640.0;
-		LEVEL 1 FOR 640.0;
-		LEVEL 0 FOR 640.0;
-		LEVEL 1 FOR 1600.0;
-		LEVEL 0 FOR 320.0;
-		LEVEL 1 FOR 1280.0;
-		LEVEL 0 FOR 640.0;
-		LEVEL 1 FOR 320.0;
-		LEVEL 0 FOR 320.0;
-		LEVEL 1 FOR 1280.0;
-		LEVEL 0 FOR 320.0;
-		LEVEL 1 FOR 320.0;
-		LEVEL 0 FOR 320.0;
-		LEVEL 1 FOR 40.0;
-	}
-}
-
-TRANSITION_LIST("vramData[4]")
-{
-	NODE
-	{
-		REPEAT = 1;
-		LEVEL Z FOR 320.0;
-		LEVEL 0 FOR 40.0;
-		LEVEL Z FOR 240.0;
-		LEVEL 1 FOR 80.0;
-		LEVEL Z FOR 280.0;
-		LEVEL 1 FOR 40.0;
-		LEVEL Z FOR 500.0;
-		LEVEL 1 FOR 100.0;
-		LEVEL 0 FOR 1600.0;
-		LEVEL 1 FOR 320.0;
-		LEVEL 0 FOR 320.0;
-		LEVEL 1 FOR 1920.0;
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-		LEVEL 1 FOR 640.0;
-		LEVEL 0 FOR 960.0;
-		LEVEL 1 FOR 320.0;
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-		LEVEL 1 FOR 960.0;
-		LEVEL 0 FOR 960.0;
-		LEVEL 1 FOR 640.0;
-		LEVEL 0 FOR 640.0;
-		LEVEL 1 FOR 320.0;
-		LEVEL 0 FOR 640.0;
-		LEVEL 1 FOR 640.0;
-		LEVEL 0 FOR 1280.0;
-		LEVEL 1 FOR 320.0;
-		LEVEL 0 FOR 320.0;
-		LEVEL 1 FOR 320.0;
-		LEVEL 0 FOR 640.0;
-		LEVEL 1 FOR 320.0;
-		LEVEL 0 FOR 640.0;
-		LEVEL 1 FOR 960.0;
-		LEVEL 0 FOR 320.0;
-		LEVEL 1 FOR 1600.0;
-		LEVEL 0 FOR 640.0;
-		LEVEL 1 FOR 320.0;
-		LEVEL 0 FOR 320.0;
-		LEVEL 1 FOR 320.0;
-		LEVEL 0 FOR 320.0;
-		LEVEL 1 FOR 2560.0;
-		LEVEL 0 FOR 640.0;
-		LEVEL 1 FOR 320.0;
-		LEVEL 0 FOR 320.0;
-		LEVEL 1 FOR 640.0;
-		LEVEL 0 FOR 960.0;
-		LEVEL 1 FOR 320.0;
-		LEVEL 0 FOR 320.0;
-		LEVEL 1 FOR 320.0;
-		LEVEL 0 FOR 640.0;
-		LEVEL 1 FOR 640.0;
-		LEVEL 0 FOR 1280.0;
-		LEVEL 1 FOR 320.0;
-		LEVEL 0 FOR 1600.0;
-		LEVEL 1 FOR 40.0;
-	}
-}
-
-TRANSITION_LIST("vramData[3]")
-{
-	NODE
-	{
-		REPEAT = 1;
-		LEVEL Z FOR 320.0;
-		LEVEL 0 FOR 40.0;
-		LEVEL Z FOR 240.0;
-		LEVEL 0 FOR 80.0;
-		LEVEL Z FOR 280.0;
-		LEVEL 1 FOR 40.0;
-		LEVEL Z FOR 500.0;
-		LEVEL 0 FOR 420.0;
-		LEVEL 1 FOR 640.0;
-		LEVEL 0 FOR 640.0;
-		LEVEL 1 FOR 320.0;
-		LEVEL 0 FOR 640.0;
-		LEVEL 1 FOR 960.0;
-		LEVEL 0 FOR 320.0;
-		LEVEL 1 FOR 640.0;
-		LEVEL 0 FOR 640.0;
-		LEVEL 1 FOR 640.0;
-		LEVEL 0 FOR 320.0;
-		LEVEL 1 FOR 320.0;
-		LEVEL 0 FOR 320.0;
-		LEVEL 1 FOR 320.0;
-		LEVEL 0 FOR 320.0;
-		LEVEL 1 FOR 320.0;
-		LEVEL 0 FOR 320.0;
-		LEVEL 1 FOR 640.0;
-		LEVEL 0 FOR 320.0;
-		LEVEL 1 FOR 640.0;
-		LEVEL 0 FOR 320.0;
-		LEVEL 1 FOR 640.0;
-		LEVEL 0 FOR 960.0;
-		LEVEL 1 FOR 640.0;
-		LEVEL 0 FOR 960.0;
-		LEVEL 1 FOR 320.0;
-		LEVEL 0 FOR 320.0;
-		LEVEL 1 FOR 320.0;
-		LEVEL 0 FOR 1280.0;
-		LEVEL 1 FOR 320.0;
-		LEVEL 0 FOR 1280.0;
-		LEVEL 1 FOR 320.0;
-		LEVEL 0 FOR 320.0;
-		LEVEL 1 FOR 960.0;
-		LEVEL 0 FOR 320.0;
-		LEVEL 1 FOR 320.0;
-		LEVEL 0 FOR 1280.0;
-		LEVEL 1 FOR 2560.0;
-		LEVEL 0 FOR 640.0;
-		LEVEL 1 FOR 640.0;
-		LEVEL 0 FOR 960.0;
-		LEVEL 1 FOR 640.0;
-		LEVEL 0 FOR 640.0;
-		LEVEL 1 FOR 960.0;
-		LEVEL 0 FOR 640.0;
-		LEVEL 1 FOR 1600.0;
-		LEVEL 0 FOR 320.0;
-		LEVEL 1 FOR 640.0;
-		LEVEL 0 FOR 320.0;
-		LEVEL 1 FOR 320.0;
-		LEVEL 0 FOR 40.0;
-	}
-}
-
-TRANSITION_LIST("vramData[2]")
-{
-	NODE
-	{
-		REPEAT = 1;
-		LEVEL Z FOR 320.0;
-		LEVEL 0 FOR 40.0;
-		LEVEL Z FOR 240.0;
-		LEVEL 1 FOR 80.0;
-		LEVEL Z FOR 280.0;
-		LEVEL 1 FOR 40.0;
-		LEVEL Z FOR 500.0;
-		LEVEL 1 FOR 740.0;
-		LEVEL 0 FOR 960.0;
-		LEVEL 1 FOR 320.0;
-		LEVEL 0 FOR 640.0;
-		LEVEL 1 FOR 640.0;
-		LEVEL 0 FOR 320.0;
-		LEVEL 1 FOR 640.0;
-		LEVEL 0 FOR 320.0;
-		LEVEL 1 FOR 320.0;
-		LEVEL 0 FOR 320.0;
-		LEVEL 1 FOR 640.0;
-		LEVEL 0 FOR 320.0;
-		LEVEL 1 FOR 640.0;
-		LEVEL 0 FOR 960.0;
-		LEVEL 1 FOR 320.0;
-		LEVEL 0 FOR 320.0;
-		LEVEL 1 FOR 640.0;
-		LEVEL 0 FOR 960.0;
-		LEVEL 1 FOR 320.0;
-		LEVEL 0 FOR 320.0;
-		LEVEL 1 FOR 960.0;
-		LEVEL 0 FOR 320.0;
-		LEVEL 1 FOR 960.0;
-		LEVEL 0 FOR 640.0;
-		LEVEL 1 FOR 640.0;
-		LEVEL 0 FOR 320.0;
-		LEVEL 1 FOR 1920.0;
-		LEVEL 0 FOR 640.0;
-		LEVEL 1 FOR 1600.0;
-		LEVEL 0 FOR 1280.0;
-		LEVEL 1 FOR 320.0;
-		LEVEL 0 FOR 320.0;
-		LEVEL 1 FOR 320.0;
-		LEVEL 0 FOR 320.0;
-		LEVEL 1 FOR 320.0;
-		LEVEL 0 FOR 320.0;
-		LEVEL 1 FOR 320.0;
-		LEVEL 0 FOR 960.0;
-		LEVEL 1 FOR 320.0;
-		LEVEL 0 FOR 960.0;
-		LEVEL 1 FOR 960.0;
-		LEVEL 0 FOR 320.0;
-		LEVEL 1 FOR 320.0;
-		LEVEL 0 FOR 640.0;
-		LEVEL 1 FOR 960.0;
-		LEVEL 0 FOR 640.0;
-		LEVEL 1 FOR 960.0;
-		LEVEL 0 FOR 1600.0;
-		LEVEL 1 FOR 640.0;
-		LEVEL 0 FOR 40.0;
-	}
-}
-
-TRANSITION_LIST("vramData[1]")
-{
-	NODE
-	{
-		REPEAT = 1;
-		LEVEL Z FOR 320.0;
-		LEVEL 1 FOR 40.0;
-		LEVEL Z FOR 240.0;
-		LEVEL 0 FOR 80.0;
-		LEVEL Z FOR 280.0;
-		LEVEL 0 FOR 40.0;
-		LEVEL Z FOR 500.0;
-		LEVEL 1 FOR 420.0;
-		LEVEL 0 FOR 320.0;
-		LEVEL 1 FOR 640.0;
-		LEVEL 0 FOR 640.0;
-		LEVEL 1 FOR 320.0;
-		LEVEL 0 FOR 320.0;
-		LEVEL 1 FOR 960.0;
-		LEVEL 0 FOR 960.0;
-		LEVEL 1 FOR 960.0;
-		LEVEL 0 FOR 320.0;
-		LEVEL 1 FOR 960.0;
-		LEVEL 0 FOR 960.0;
-		LEVEL 1 FOR 2240.0;
-		LEVEL 0 FOR 960.0;
-		LEVEL 1 FOR 320.0;
-		LEVEL 0 FOR 960.0;
-		LEVEL 1 FOR 1920.0;
-		LEVEL 0 FOR 320.0;
-		LEVEL 1 FOR 640.0;
-		LEVEL 0 FOR 320.0;
-		LEVEL 1 FOR 320.0;
-		LEVEL 0 FOR 320.0;
-		LEVEL 1 FOR 640.0;
-		LEVEL 0 FOR 960.0;
-		LEVEL 1 FOR 640.0;
-		LEVEL 0 FOR 640.0;
-		LEVEL 1 FOR 320.0;
-		LEVEL 0 FOR 960.0;
-		LEVEL 1 FOR 320.0;
-		LEVEL 0 FOR 320.0;
-		LEVEL 1 FOR 320.0;
-		LEVEL 0 FOR 960.0;
-		LEVEL 1 FOR 320.0;
-		LEVEL 0 FOR 320.0;
-		LEVEL 1 FOR 640.0;
-		LEVEL 0 FOR 320.0;
-		LEVEL 1 FOR 640.0;
-		LEVEL 0 FOR 320.0;
-		LEVEL 1 FOR 320.0;
-		LEVEL 0 FOR 640.0;
-		LEVEL 1 FOR 320.0;
-		LEVEL 0 FOR 640.0;
-		LEVEL 1 FOR 320.0;
-		LEVEL 0 FOR 960.0;
-		LEVEL 1 FOR 320.0;
-		LEVEL 0 FOR 1280.0;
-		LEVEL 1 FOR 320.0;
-		LEVEL 0 FOR 320.0;
-		LEVEL 1 FOR 320.0;
-		LEVEL 0 FOR 320.0;
-		LEVEL 1 FOR 640.0;
-		LEVEL 0 FOR 40.0;
-	}
-}
-
-TRANSITION_LIST("vramData[0]")
-{
-	NODE
-	{
-		REPEAT = 1;
-		LEVEL Z FOR 320.0;
-		LEVEL 1 FOR 40.0;
-		LEVEL Z FOR 240.0;
-		LEVEL 1 FOR 80.0;
-		LEVEL Z FOR 280.0;
-		LEVEL 0 FOR 40.0;
-		LEVEL Z FOR 500.0;
-		LEVEL 0 FOR 420.0;
-		LEVEL 1 FOR 320.0;
-		LEVEL 0 FOR 320.0;
-		LEVEL 1 FOR 320.0;
-		LEVEL 0 FOR 320.0;
-		LEVEL 1 FOR 320.0;
-		LEVEL 0 FOR 320.0;
-		LEVEL 1 FOR 960.0;
-		LEVEL 0 FOR 960.0;
-		LEVEL 1 FOR 320.0;
-		LEVEL 0 FOR 960.0;
-		LEVEL 1 FOR 320.0;
-		LEVEL 0 FOR 640.0;
-		LEVEL 1 FOR 960.0;
-		LEVEL 0 FOR 640.0;
-		LEVEL 1 FOR 320.0;
-		LEVEL 0 FOR 320.0;
-		LEVEL 1 FOR 320.0;
-		LEVEL 0 FOR 320.0;
-		LEVEL 1 FOR 640.0;
-		LEVEL 0 FOR 640.0;
-		LEVEL 1 FOR 960.0;
-		LEVEL 0 FOR 1920.0;
-		LEVEL 1 FOR 2240.0;
-		LEVEL 0 FOR 960.0;
-		LEVEL 1 FOR 640.0;
-		LEVEL 0 FOR 320.0;
-		LEVEL 1 FOR 320.0;
-		LEVEL 0 FOR 320.0;
-		LEVEL 1 FOR 640.0;
-		LEVEL 0 FOR 960.0;
-		LEVEL 1 FOR 320.0;
-		LEVEL 0 FOR 320.0;
-		LEVEL 1 FOR 320.0;
-		LEVEL 0 FOR 320.0;
-		LEVEL 1 FOR 640.0;
-		LEVEL 0 FOR 1920.0;
-		LEVEL 1 FOR 1920.0;
-		LEVEL 0 FOR 640.0;
-		LEVEL 1 FOR 320.0;
-		LEVEL 0 FOR 640.0;
-		LEVEL 1 FOR 1280.0;
-		LEVEL 0 FOR 2240.0;
-		LEVEL 1 FOR 320.0;
-		LEVEL 0 FOR 360.0;
-	}
-}
-
-TRANSITION_LIST("cpusnoop:cpusnp|addrCache[13]")
-{
-	NODE
-	{
-		REPEAT = 1;
-		LEVEL U FOR 33000.0;
-	}
-}
-
-TRANSITION_LIST("cpusnoop:cpusnp|addrCache[12]")
-{
-	NODE
-	{
-		REPEAT = 1;
-		LEVEL U FOR 33000.0;
-	}
-}
-
-TRANSITION_LIST("cpusnoop:cpusnp|addrCache[11]")
-{
-	NODE
-	{
-		REPEAT = 1;
-		LEVEL U FOR 33000.0;
-	}
-}
-
-TRANSITION_LIST("cpusnoop:cpusnp|addrCache[10]")
-{
-	NODE
-	{
-		REPEAT = 1;
-		LEVEL U FOR 33000.0;
-	}
-}
-
-TRANSITION_LIST("cpusnoop:cpusnp|addrCache[9]")
-{
-	NODE
-	{
-		REPEAT = 1;
-		LEVEL U FOR 33000.0;
-	}
-}
-
-TRANSITION_LIST("cpusnoop:cpusnp|addrCache[8]")
-{
-	NODE
-	{
-		REPEAT = 1;
-		LEVEL U FOR 33000.0;
-	}
-}
-
-TRANSITION_LIST("cpusnoop:cpusnp|addrCache[7]")
-{
-	NODE
-	{
-		REPEAT = 1;
-		LEVEL U FOR 33000.0;
-	}
-}
-
-TRANSITION_LIST("cpusnoop:cpusnp|addrCache[6]")
-{
-	NODE
-	{
-		REPEAT = 1;
-		LEVEL U FOR 33000.0;
-	}
-}
-
-TRANSITION_LIST("cpusnoop:cpusnp|addrCache[5]")
-{
-	NODE
-	{
-		REPEAT = 1;
-		LEVEL U FOR 33000.0;
-	}
-}
-
-TRANSITION_LIST("cpusnoop:cpusnp|addrCache[4]")
-{
-	NODE
-	{
-		REPEAT = 1;
-		LEVEL U FOR 33000.0;
-	}
-}
-
-TRANSITION_LIST("cpusnoop:cpusnp|addrCache[3]")
-{
-	NODE
-	{
-		REPEAT = 1;
-		LEVEL U FOR 33000.0;
-	}
-}
-
-TRANSITION_LIST("cpusnoop:cpusnp|addrCache[2]")
-{
-	NODE
-	{
-		REPEAT = 1;
-		LEVEL U FOR 33000.0;
-	}
-}
-
-TRANSITION_LIST("cpusnoop:cpusnp|addrCache[1]")
-{
-	NODE
-	{
-		REPEAT = 1;
-		LEVEL U FOR 33000.0;
-	}
-}
-
-TRANSITION_LIST("cpusnoop:cpusnp|addrCache[0]")
-{
-	NODE
-	{
-		REPEAT = 1;
-		LEVEL U FOR 33000.0;
-	}
-}
-
-TRANSITION_LIST("cpusnoop:cpusnp|dataCacheHi[7]")
-{
-	NODE
-	{
-		REPEAT = 1;
-		LEVEL U FOR 33000.0;
-	}
-}
-
-TRANSITION_LIST("cpusnoop:cpusnp|dataCacheHi[6]")
-{
-	NODE
-	{
-		REPEAT = 1;
-		LEVEL U FOR 33000.0;
-	}
-}
-
-TRANSITION_LIST("cpusnoop:cpusnp|dataCacheHi[5]")
-{
-	NODE
-	{
-		REPEAT = 1;
-		LEVEL U FOR 33000.0;
-	}
-}
-
-TRANSITION_LIST("cpusnoop:cpusnp|dataCacheHi[4]")
-{
-	NODE
-	{
-		REPEAT = 1;
-		LEVEL U FOR 33000.0;
-	}
-}
-
-TRANSITION_LIST("cpusnoop:cpusnp|dataCacheHi[3]")
-{
-	NODE
-	{
-		REPEAT = 1;
-		LEVEL U FOR 33000.0;
-	}
-}
-
-TRANSITION_LIST("cpusnoop:cpusnp|dataCacheHi[2]")
-{
-	NODE
-	{
-		REPEAT = 1;
-		LEVEL U FOR 33000.0;
-	}
-}
-
-TRANSITION_LIST("cpusnoop:cpusnp|dataCacheHi[1]")
-{
-	NODE
-	{
-		REPEAT = 1;
-		LEVEL U FOR 33000.0;
-	}
-}
-
-TRANSITION_LIST("cpusnoop:cpusnp|dataCacheHi[0]")
-{
-	NODE
-	{
-		REPEAT = 1;
-		LEVEL U FOR 33000.0;
-	}
-}
-
-TRANSITION_LIST("cpusnoop:cpusnp|dataCacheLo[7]")
-{
-	NODE
-	{
-		REPEAT = 1;
-		LEVEL U FOR 33000.0;
-	}
-}
-
-TRANSITION_LIST("cpusnoop:cpusnp|dataCacheLo[6]")
-{
-	NODE
-	{
-		REPEAT = 1;
-		LEVEL U FOR 33000.0;
-	}
-}
-
-TRANSITION_LIST("cpusnoop:cpusnp|dataCacheLo[5]")
-{
-	NODE
-	{
-		REPEAT = 1;
-		LEVEL U FOR 33000.0;
-	}
-}
-
-TRANSITION_LIST("cpusnoop:cpusnp|dataCacheLo[4]")
-{
-	NODE
-	{
-		REPEAT = 1;
-		LEVEL U FOR 33000.0;
-	}
-}
-
-TRANSITION_LIST("cpusnoop:cpusnp|dataCacheLo[3]")
-{
-	NODE
-	{
-		REPEAT = 1;
-		LEVEL U FOR 33000.0;
-	}
-}
-
-TRANSITION_LIST("cpusnoop:cpusnp|dataCacheLo[2]")
-{
-	NODE
-	{
-		REPEAT = 1;
-		LEVEL U FOR 33000.0;
-	}
-}
-
-TRANSITION_LIST("cpusnoop:cpusnp|dataCacheLo[1]")
-{
-	NODE
-	{
-		REPEAT = 1;
-		LEVEL U FOR 33000.0;
-	}
-}
-
-TRANSITION_LIST("cpusnoop:cpusnp|dataCacheLo[0]")
-{
-	NODE
-	{
-		REPEAT = 1;
-		LEVEL U FOR 33000.0;
-	}
-}
-
-TRANSITION_LIST("cpusnoop:cpusnp|pendWriteHi")
-{
-	NODE
-	{
-		REPEAT = 1;
-		LEVEL U FOR 33000.0;
-	}
-}
-
-TRANSITION_LIST("cpusnoop:cpusnp|pendWriteLo")
-{
-	NODE
-	{
-		REPEAT = 1;
-		LEVEL U FOR 33000.0;
-	}
-}
-
-TRANSITION_LIST("nvramCE0")
-{
-	NODE
-	{
-		REPEAT = 1;
-		LEVEL X FOR 33000.0;
-	}
-}
-
-TRANSITION_LIST("nvramCE1")
-{
-	NODE
-	{
-		REPEAT = 1;
-		LEVEL X FOR 33000.0;
-	}
-}
-
-DISPLAY_LINE
-{
-	CHANNEL = "cpuAddr";
-	EXPAND_STATUS = COLLAPSED;
-	RADIX = Hexadecimal;
-	TREE_INDEX = 0;
-	TREE_LEVEL = 0;
-	CHILDREN = 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23;
-}
-
-DISPLAY_LINE
-{
-	CHANNEL = "cpuAddr[23]";
-	EXPAND_STATUS = COLLAPSED;
-	RADIX = Hexadecimal;
-	TREE_INDEX = 1;
-	TREE_LEVEL = 1;
-	PARENT = 0;
-}
-
-DISPLAY_LINE
-{
-	CHANNEL = "cpuAddr[22]";
-	EXPAND_STATUS = COLLAPSED;
-	RADIX = Hexadecimal;
-	TREE_INDEX = 2;
-	TREE_LEVEL = 1;
-	PARENT = 0;
-}
-
-DISPLAY_LINE
-{
-	CHANNEL = "cpuAddr[21]";
-	EXPAND_STATUS = COLLAPSED;
-	RADIX = Hexadecimal;
-	TREE_INDEX = 3;
-	TREE_LEVEL = 1;
-	PARENT = 0;
-}
-
-DISPLAY_LINE
-{
-	CHANNEL = "cpuAddr[20]";
-	EXPAND_STATUS = COLLAPSED;
-	RADIX = Hexadecimal;
-	TREE_INDEX = 4;
-	TREE_LEVEL = 1;
-	PARENT = 0;
-}
-
-DISPLAY_LINE
-{
-	CHANNEL = "cpuAddr[19]";
-	EXPAND_STATUS = COLLAPSED;
-	RADIX = Hexadecimal;
-	TREE_INDEX = 5;
-	TREE_LEVEL = 1;
-	PARENT = 0;
-}
-
-DISPLAY_LINE
-{
-	CHANNEL = "cpuAddr[18]";
-	EXPAND_STATUS = COLLAPSED;
-	RADIX = Hexadecimal;
-	TREE_INDEX = 6;
-	TREE_LEVEL = 1;
-	PARENT = 0;
-}
-
-DISPLAY_LINE
-{
-	CHANNEL = "cpuAddr[17]";
-	EXPAND_STATUS = COLLAPSED;
-	RADIX = Hexadecimal;
-	TREE_INDEX = 7;
-	TREE_LEVEL = 1;
-	PARENT = 0;
-}
-
-DISPLAY_LINE
-{
-	CHANNEL = "cpuAddr[16]";
-	EXPAND_STATUS = COLLAPSED;
-	RADIX = Hexadecimal;
-	TREE_INDEX = 8;
-	TREE_LEVEL = 1;
-	PARENT = 0;
-}
-
-DISPLAY_LINE
-{
-	CHANNEL = "cpuAddr[15]";
-	EXPAND_STATUS = COLLAPSED;
-	RADIX = Hexadecimal;
-	TREE_INDEX = 9;
-	TREE_LEVEL = 1;
-	PARENT = 0;
-}
-
-DISPLAY_LINE
-{
-	CHANNEL = "cpuAddr[14]";
-	EXPAND_STATUS = COLLAPSED;
-	RADIX = Hexadecimal;
-	TREE_INDEX = 10;
-	TREE_LEVEL = 1;
-	PARENT = 0;
-}
-
-DISPLAY_LINE
-{
-	CHANNEL = "cpuAddr[13]";
-	EXPAND_STATUS = COLLAPSED;
-	RADIX = Hexadecimal;
-	TREE_INDEX = 11;
-	TREE_LEVEL = 1;
-	PARENT = 0;
-}
-
-DISPLAY_LINE
-{
-	CHANNEL = "cpuAddr[12]";
-	EXPAND_STATUS = COLLAPSED;
-	RADIX = Hexadecimal;
-	TREE_INDEX = 12;
-	TREE_LEVEL = 1;
-	PARENT = 0;
-}
-
-DISPLAY_LINE
-{
-	CHANNEL = "cpuAddr[11]";
-	EXPAND_STATUS = COLLAPSED;
-	RADIX = Hexadecimal;
-	TREE_INDEX = 13;
-	TREE_LEVEL = 1;
-	PARENT = 0;
-}
-
-DISPLAY_LINE
-{
-	CHANNEL = "cpuAddr[10]";
-	EXPAND_STATUS = COLLAPSED;
-	RADIX = Hexadecimal;
-	TREE_INDEX = 14;
-	TREE_LEVEL = 1;
-	PARENT = 0;
-}
-
-DISPLAY_LINE
-{
-	CHANNEL = "cpuAddr[9]";
-	EXPAND_STATUS = COLLAPSED;
-	RADIX = Hexadecimal;
-	TREE_INDEX = 15;
-	TREE_LEVEL = 1;
-	PARENT = 0;
-}
-
-DISPLAY_LINE
-{
-	CHANNEL = "cpuAddr[8]";
-	EXPAND_STATUS = COLLAPSED;
-	RADIX = Hexadecimal;
-	TREE_INDEX = 16;
-	TREE_LEVEL = 1;
-	PARENT = 0;
-}
-
-DISPLAY_LINE
-{
-	CHANNEL = "cpuAddr[7]";
-	EXPAND_STATUS = COLLAPSED;
-	RADIX = Hexadecimal;
-	TREE_INDEX = 17;
-	TREE_LEVEL = 1;
-	PARENT = 0;
-}
-
-DISPLAY_LINE
-{
-	CHANNEL = "cpuAddr[6]";
-	EXPAND_STATUS = COLLAPSED;
-	RADIX = Hexadecimal;
-	TREE_INDEX = 18;
-	TREE_LEVEL = 1;
-	PARENT = 0;
-}
-
-DISPLAY_LINE
-{
-	CHANNEL = "cpuAddr[5]";
-	EXPAND_STATUS = COLLAPSED;
-	RADIX = Hexadecimal;
-	TREE_INDEX = 19;
-	TREE_LEVEL = 1;
-	PARENT = 0;
-}
-
-DISPLAY_LINE
-{
-	CHANNEL = "cpuAddr[4]";
-	EXPAND_STATUS = COLLAPSED;
-	RADIX = Hexadecimal;
-	TREE_INDEX = 20;
-	TREE_LEVEL = 1;
-	PARENT = 0;
-}
-
-DISPLAY_LINE
-{
-	CHANNEL = "cpuAddr[3]";
-	EXPAND_STATUS = COLLAPSED;
-	RADIX = Hexadecimal;
-	TREE_INDEX = 21;
-	TREE_LEVEL = 1;
-	PARENT = 0;
-}
-
-DISPLAY_LINE
-{
-	CHANNEL = "cpuAddr[2]";
-	EXPAND_STATUS = COLLAPSED;
-	RADIX = Hexadecimal;
-	TREE_INDEX = 22;
-	TREE_LEVEL = 1;
-	PARENT = 0;
-}
-
-DISPLAY_LINE
-{
-	CHANNEL = "cpuAddr[1]";
-	EXPAND_STATUS = COLLAPSED;
-	RADIX = Hexadecimal;
-	TREE_INDEX = 23;
-	TREE_LEVEL = 1;
-	PARENT = 0;
-}
-
-DISPLAY_LINE
-{
-	CHANNEL = "cpuClk";
-	EXPAND_STATUS = COLLAPSED;
-	RADIX = Binary;
-	TREE_INDEX = 24;
-	TREE_LEVEL = 0;
-}
-
-DISPLAY_LINE
-{
-	CHANNEL = "cpuData";
-	EXPAND_STATUS = COLLAPSED;
-	RADIX = Hexadecimal;
-	TREE_INDEX = 25;
-	TREE_LEVEL = 0;
-	CHILDREN = 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41;
-}
-
-DISPLAY_LINE
-{
-	CHANNEL = "cpuData[15]";
-	EXPAND_STATUS = COLLAPSED;
-	RADIX = Hexadecimal;
-	TREE_INDEX = 26;
-	TREE_LEVEL = 1;
-	PARENT = 25;
-}
-
-DISPLAY_LINE
-{
-	CHANNEL = "cpuData[14]";
-	EXPAND_STATUS = COLLAPSED;
-	RADIX = Hexadecimal;
-	TREE_INDEX = 27;
-	TREE_LEVEL = 1;
-	PARENT = 25;
-}
-
-DISPLAY_LINE
-{
-	CHANNEL = "cpuData[13]";
-	EXPAND_STATUS = COLLAPSED;
-	RADIX = Hexadecimal;
-	TREE_INDEX = 28;
-	TREE_LEVEL = 1;
-	PARENT = 25;
-}
-
-DISPLAY_LINE
-{
-	CHANNEL = "cpuData[12]";
-	EXPAND_STATUS = COLLAPSED;
-	RADIX = Hexadecimal;
-	TREE_INDEX = 29;
-	TREE_LEVEL = 1;
-	PARENT = 25;
-}
-
-DISPLAY_LINE
-{
-	CHANNEL = "cpuData[11]";
-	EXPAND_STATUS = COLLAPSED;
-	RADIX = Hexadecimal;
-	TREE_INDEX = 30;
-	TREE_LEVEL = 1;
-	PARENT = 25;
-}
-
-DISPLAY_LINE
-{
-	CHANNEL = "cpuData[10]";
-	EXPAND_STATUS = COLLAPSED;
-	RADIX = Hexadecimal;
-	TREE_INDEX = 31;
-	TREE_LEVEL = 1;
-	PARENT = 25;
-}
-
-DISPLAY_LINE
-{
-	CHANNEL = "cpuData[9]";
-	EXPAND_STATUS = COLLAPSED;
-	RADIX = Hexadecimal;
-	TREE_INDEX = 32;
-	TREE_LEVEL = 1;
-	PARENT = 25;
-}
-
-DISPLAY_LINE
-{
-	CHANNEL = "cpuData[8]";
-	EXPAND_STATUS = COLLAPSED;
-	RADIX = Hexadecimal;
-	TREE_INDEX = 33;
-	TREE_LEVEL = 1;
-	PARENT = 25;
-}
-
-DISPLAY_LINE
-{
-	CHANNEL = "cpuData[7]";
-	EXPAND_STATUS = COLLAPSED;
-	RADIX = Hexadecimal;
-	TREE_INDEX = 34;
-	TREE_LEVEL = 1;
-	PARENT = 25;
-}
-
-DISPLAY_LINE
-{
-	CHANNEL = "cpuData[6]";
-	EXPAND_STATUS = COLLAPSED;
-	RADIX = Hexadecimal;
-	TREE_INDEX = 35;
-	TREE_LEVEL = 1;
-	PARENT = 25;
-}
-
-DISPLAY_LINE
-{
-	CHANNEL = "cpuData[5]";
-	EXPAND_STATUS = COLLAPSED;
-	RADIX = Hexadecimal;
-	TREE_INDEX = 36;
-	TREE_LEVEL = 1;
-	PARENT = 25;
-}
-
-DISPLAY_LINE
-{
-	CHANNEL = "cpuData[4]";
-	EXPAND_STATUS = COLLAPSED;
-	RADIX = Hexadecimal;
-	TREE_INDEX = 37;
-	TREE_LEVEL = 1;
-	PARENT = 25;
-}
-
-DISPLAY_LINE
-{
-	CHANNEL = "cpuData[3]";
-	EXPAND_STATUS = COLLAPSED;
-	RADIX = Hexadecimal;
-	TREE_INDEX = 38;
-	TREE_LEVEL = 1;
-	PARENT = 25;
-}
-
-DISPLAY_LINE
-{
-	CHANNEL = "cpuData[2]";
-	EXPAND_STATUS = COLLAPSED;
-	RADIX = Hexadecimal;
-	TREE_INDEX = 39;
-	TREE_LEVEL = 1;
-	PARENT = 25;
-}
-
-DISPLAY_LINE
-{
-	CHANNEL = "cpuData[1]";
-	EXPAND_STATUS = COLLAPSED;
-	RADIX = Hexadecimal;
-	TREE_INDEX = 40;
-	TREE_LEVEL = 1;
-	PARENT = 25;
-}
-
-DISPLAY_LINE
-{
-	CHANNEL = "cpuData[0]";
-	EXPAND_STATUS = COLLAPSED;
-	RADIX = Hexadecimal;
-	TREE_INDEX = 41;
-	TREE_LEVEL = 1;
-	PARENT = 25;
-}
-
-DISPLAY_LINE
-{
-	CHANNEL = "cpuRnW";
-	EXPAND_STATUS = COLLAPSED;
-	RADIX = Binary;
-	TREE_INDEX = 42;
-	TREE_LEVEL = 0;
-}
-
-DISPLAY_LINE
-{
-	CHANNEL = "nReset";
-	EXPAND_STATUS = COLLAPSED;
-	RADIX = Binary;
-	TREE_INDEX = 43;
-	TREE_LEVEL = 0;
-}
-
-DISPLAY_LINE
-{
-	CHANNEL = "ncpuAS";
-	EXPAND_STATUS = COLLAPSED;
-	RADIX = Binary;
-	TREE_INDEX = 44;
-	TREE_LEVEL = 0;
-}
-
-DISPLAY_LINE
-{
-	CHANNEL = "ncpuLDS";
-	EXPAND_STATUS = COLLAPSED;
-	RADIX = Binary;
-	TREE_INDEX = 45;
-	TREE_LEVEL = 0;
-}
-
-DISPLAY_LINE
-{
-	CHANNEL = "ncpuUDS";
-	EXPAND_STATUS = COLLAPSED;
-	RADIX = Binary;
-	TREE_INDEX = 46;
-	TREE_LEVEL = 0;
-}
-
-DISPLAY_LINE
-{
-	CHANNEL = "nhSync";
-	EXPAND_STATUS = COLLAPSED;
-	RADIX = Binary;
-	TREE_INDEX = 47;
-	TREE_LEVEL = 0;
-}
-
-DISPLAY_LINE
-{
-	CHANNEL = "nvSync";
-	EXPAND_STATUS = COLLAPSED;
-	RADIX = Binary;
-	TREE_INDEX = 48;
-	TREE_LEVEL = 0;
-}
-
-DISPLAY_LINE
-{
-	CHANNEL = "nvramOE";
-	EXPAND_STATUS = COLLAPSED;
-	RADIX = Binary;
-	TREE_INDEX = 49;
-	TREE_LEVEL = 0;
-}
-
-DISPLAY_LINE
-{
-	CHANNEL = "nvramWE";
-	EXPAND_STATUS = COLLAPSED;
-	RADIX = Binary;
-	TREE_INDEX = 50;
-	TREE_LEVEL = 0;
-}
-
-DISPLAY_LINE
-{
-	CHANNEL = "pixClk";
-	EXPAND_STATUS = COLLAPSED;
-	RADIX = Binary;
-	TREE_INDEX = 51;
-	TREE_LEVEL = 0;
-}
-
-DISPLAY_LINE
-{
-	CHANNEL = "ramSize";
-	EXPAND_STATUS = COLLAPSED;
-	RADIX = Octal;
-	TREE_INDEX = 52;
-	TREE_LEVEL = 0;
-	CHILDREN = 53, 54, 55;
-}
-
-DISPLAY_LINE
-{
-	CHANNEL = "ramSize[2]";
-	EXPAND_STATUS = COLLAPSED;
-	RADIX = Octal;
-	TREE_INDEX = 53;
-	TREE_LEVEL = 1;
-	PARENT = 52;
-}
-
-DISPLAY_LINE
-{
-	CHANNEL = "ramSize[1]";
-	EXPAND_STATUS = COLLAPSED;
-	RADIX = Octal;
-	TREE_INDEX = 54;
-	TREE_LEVEL = 1;
-	PARENT = 52;
-}
-
-DISPLAY_LINE
-{
-	CHANNEL = "ramSize[0]";
-	EXPAND_STATUS = COLLAPSED;
-	RADIX = Octal;
-	TREE_INDEX = 55;
-	TREE_LEVEL = 1;
-	PARENT = 52;
-}
-
-DISPLAY_LINE
-{
-	CHANNEL = "vidOut";
-	EXPAND_STATUS = COLLAPSED;
-	RADIX = Binary;
-	TREE_INDEX = 56;
-	TREE_LEVEL = 0;
-}
-
-DISPLAY_LINE
-{
-	CHANNEL = "vramAddr";
-	EXPAND_STATUS = COLLAPSED;
-	RADIX = Hexadecimal;
-	TREE_INDEX = 57;
-	TREE_LEVEL = 0;
-	CHILDREN = 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72;
-}
-
-DISPLAY_LINE
-{
-	CHANNEL = "vramAddr[14]";
-	EXPAND_STATUS = COLLAPSED;
-	RADIX = Hexadecimal;
-	TREE_INDEX = 58;
-	TREE_LEVEL = 1;
-	PARENT = 57;
-}
-
-DISPLAY_LINE
-{
-	CHANNEL = "vramAddr[13]";
-	EXPAND_STATUS = COLLAPSED;
-	RADIX = Hexadecimal;
-	TREE_INDEX = 59;
-	TREE_LEVEL = 1;
-	PARENT = 57;
-}
-
-DISPLAY_LINE
-{
-	CHANNEL = "vramAddr[12]";
-	EXPAND_STATUS = COLLAPSED;
-	RADIX = Hexadecimal;
-	TREE_INDEX = 60;
-	TREE_LEVEL = 1;
-	PARENT = 57;
-}
-
-DISPLAY_LINE
-{
-	CHANNEL = "vramAddr[11]";
-	EXPAND_STATUS = COLLAPSED;
-	RADIX = Hexadecimal;
-	TREE_INDEX = 61;
-	TREE_LEVEL = 1;
-	PARENT = 57;
-}
-
-DISPLAY_LINE
-{
-	CHANNEL = "vramAddr[10]";
-	EXPAND_STATUS = COLLAPSED;
-	RADIX = Hexadecimal;
-	TREE_INDEX = 62;
-	TREE_LEVEL = 1;
-	PARENT = 57;
-}
-
-DISPLAY_LINE
-{
-	CHANNEL = "vramAddr[9]";
-	EXPAND_STATUS = COLLAPSED;
-	RADIX = Hexadecimal;
-	TREE_INDEX = 63;
-	TREE_LEVEL = 1;
-	PARENT = 57;
-}
-
-DISPLAY_LINE
-{
-	CHANNEL = "vramAddr[8]";
-	EXPAND_STATUS = COLLAPSED;
-	RADIX = Hexadecimal;
-	TREE_INDEX = 64;
-	TREE_LEVEL = 1;
-	PARENT = 57;
-}
-
-DISPLAY_LINE
-{
-	CHANNEL = "vramAddr[7]";
-	EXPAND_STATUS = COLLAPSED;
-	RADIX = Hexadecimal;
-	TREE_INDEX = 65;
-	TREE_LEVEL = 1;
-	PARENT = 57;
-}
-
-DISPLAY_LINE
-{
-	CHANNEL = "vramAddr[6]";
-	EXPAND_STATUS = COLLAPSED;
-	RADIX = Hexadecimal;
-	TREE_INDEX = 66;
-	TREE_LEVEL = 1;
-	PARENT = 57;
-}
-
-DISPLAY_LINE
-{
-	CHANNEL = "vramAddr[5]";
-	EXPAND_STATUS = COLLAPSED;
-	RADIX = Hexadecimal;
-	TREE_INDEX = 67;
-	TREE_LEVEL = 1;
-	PARENT = 57;
-}
-
-DISPLAY_LINE
-{
-	CHANNEL = "vramAddr[4]";
-	EXPAND_STATUS = COLLAPSED;
-	RADIX = Hexadecimal;
-	TREE_INDEX = 68;
-	TREE_LEVEL = 1;
-	PARENT = 57;
-}
-
-DISPLAY_LINE
-{
-	CHANNEL = "vramAddr[3]";
-	EXPAND_STATUS = COLLAPSED;
-	RADIX = Hexadecimal;
-	TREE_INDEX = 69;
-	TREE_LEVEL = 1;
-	PARENT = 57;
-}
-
-DISPLAY_LINE
-{
-	CHANNEL = "vramAddr[2]";
-	EXPAND_STATUS = COLLAPSED;
-	RADIX = Hexadecimal;
-	TREE_INDEX = 70;
-	TREE_LEVEL = 1;
-	PARENT = 57;
-}
-
-DISPLAY_LINE
-{
-	CHANNEL = "vramAddr[1]";
-	EXPAND_STATUS = COLLAPSED;
-	RADIX = Hexadecimal;
-	TREE_INDEX = 71;
-	TREE_LEVEL = 1;
-	PARENT = 57;
-}
-
-DISPLAY_LINE
-{
-	CHANNEL = "vramAddr[0]";
-	EXPAND_STATUS = COLLAPSED;
-	RADIX = Hexadecimal;
-	TREE_INDEX = 72;
-	TREE_LEVEL = 1;
-	PARENT = 57;
-}
-
-DISPLAY_LINE
-{
-	CHANNEL = "vramData";
-	EXPAND_STATUS = COLLAPSED;
-	RADIX = Hexadecimal;
-	TREE_INDEX = 73;
-	TREE_LEVEL = 0;
-	CHILDREN = 74, 75, 76, 77, 78, 79, 80, 81;
-}
-
-DISPLAY_LINE
-{
-	CHANNEL = "vramData[7]";
-	EXPAND_STATUS = COLLAPSED;
-	RADIX = Hexadecimal;
-	TREE_INDEX = 74;
-	TREE_LEVEL = 1;
-	PARENT = 73;
-}
-
-DISPLAY_LINE
-{
-	CHANNEL = "vramData[6]";
-	EXPAND_STATUS = COLLAPSED;
-	RADIX = Hexadecimal;
-	TREE_INDEX = 75;
-	TREE_LEVEL = 1;
-	PARENT = 73;
-}
-
-DISPLAY_LINE
-{
-	CHANNEL = "vramData[5]";
-	EXPAND_STATUS = COLLAPSED;
-	RADIX = Hexadecimal;
-	TREE_INDEX = 76;
-	TREE_LEVEL = 1;
-	PARENT = 73;
-}
-
-DISPLAY_LINE
-{
-	CHANNEL = "vramData[4]";
-	EXPAND_STATUS = COLLAPSED;
-	RADIX = Hexadecimal;
-	TREE_INDEX = 77;
-	TREE_LEVEL = 1;
-	PARENT = 73;
-}
-
-DISPLAY_LINE
-{
-	CHANNEL = "vramData[3]";
-	EXPAND_STATUS = COLLAPSED;
-	RADIX = Hexadecimal;
-	TREE_INDEX = 78;
-	TREE_LEVEL = 1;
-	PARENT = 73;
-}
-
-DISPLAY_LINE
-{
-	CHANNEL = "vramData[2]";
-	EXPAND_STATUS = COLLAPSED;
-	RADIX = Hexadecimal;
-	TREE_INDEX = 79;
-	TREE_LEVEL = 1;
-	PARENT = 73;
-}
-
-DISPLAY_LINE
-{
-	CHANNEL = "vramData[1]";
-	EXPAND_STATUS = COLLAPSED;
-	RADIX = Hexadecimal;
-	TREE_INDEX = 80;
-	TREE_LEVEL = 1;
-	PARENT = 73;
-}
-
-DISPLAY_LINE
-{
-	CHANNEL = "vramData[0]";
-	EXPAND_STATUS = COLLAPSED;
-	RADIX = Hexadecimal;
-	TREE_INDEX = 81;
-	TREE_LEVEL = 1;
-	PARENT = 73;
-}
-
-DISPLAY_LINE
-{
-	CHANNEL = "cpusnoop:cpusnp|addrCache";
-	EXPAND_STATUS = COLLAPSED;
-	RADIX = Hexadecimal;
-	TREE_INDEX = 82;
-	TREE_LEVEL = 0;
-	CHILDREN = 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96;
-}
-
-DISPLAY_LINE
-{
-	CHANNEL = "cpusnoop:cpusnp|addrCache[13]";
-	EXPAND_STATUS = COLLAPSED;
-	RADIX = Hexadecimal;
-	TREE_INDEX = 83;
-	TREE_LEVEL = 1;
-	PARENT = 82;
-}
-
-DISPLAY_LINE
-{
-	CHANNEL = "cpusnoop:cpusnp|addrCache[12]";
-	EXPAND_STATUS = COLLAPSED;
-	RADIX = Hexadecimal;
-	TREE_INDEX = 84;
-	TREE_LEVEL = 1;
-	PARENT = 82;
-}
-
-DISPLAY_LINE
-{
-	CHANNEL = "cpusnoop:cpusnp|addrCache[11]";
-	EXPAND_STATUS = COLLAPSED;
-	RADIX = Hexadecimal;
-	TREE_INDEX = 85;
-	TREE_LEVEL = 1;
-	PARENT = 82;
-}
-
-DISPLAY_LINE
-{
-	CHANNEL = "cpusnoop:cpusnp|addrCache[10]";
-	EXPAND_STATUS = COLLAPSED;
-	RADIX = Hexadecimal;
-	TREE_INDEX = 86;
-	TREE_LEVEL = 1;
-	PARENT = 82;
-}
-
-DISPLAY_LINE
-{
-	CHANNEL = "cpusnoop:cpusnp|addrCache[9]";
-	EXPAND_STATUS = COLLAPSED;
-	RADIX = Hexadecimal;
-	TREE_INDEX = 87;
-	TREE_LEVEL = 1;
-	PARENT = 82;
-}
-
-DISPLAY_LINE
-{
-	CHANNEL = "cpusnoop:cpusnp|addrCache[8]";
-	EXPAND_STATUS = COLLAPSED;
-	RADIX = Hexadecimal;
-	TREE_INDEX = 88;
-	TREE_LEVEL = 1;
-	PARENT = 82;
-}
-
-DISPLAY_LINE
-{
-	CHANNEL = "cpusnoop:cpusnp|addrCache[7]";
-	EXPAND_STATUS = COLLAPSED;
-	RADIX = Hexadecimal;
-	TREE_INDEX = 89;
-	TREE_LEVEL = 1;
-	PARENT = 82;
-}
-
-DISPLAY_LINE
-{
-	CHANNEL = "cpusnoop:cpusnp|addrCache[6]";
-	EXPAND_STATUS = COLLAPSED;
-	RADIX = Hexadecimal;
-	TREE_INDEX = 90;
-	TREE_LEVEL = 1;
-	PARENT = 82;
-}
-
-DISPLAY_LINE
-{
-	CHANNEL = "cpusnoop:cpusnp|addrCache[5]";
-	EXPAND_STATUS = COLLAPSED;
-	RADIX = Hexadecimal;
-	TREE_INDEX = 91;
-	TREE_LEVEL = 1;
-	PARENT = 82;
-}
-
-DISPLAY_LINE
-{
-	CHANNEL = "cpusnoop:cpusnp|addrCache[4]";
-	EXPAND_STATUS = COLLAPSED;
-	RADIX = Hexadecimal;
-	TREE_INDEX = 92;
-	TREE_LEVEL = 1;
-	PARENT = 82;
-}
-
-DISPLAY_LINE
-{
-	CHANNEL = "cpusnoop:cpusnp|addrCache[3]";
-	EXPAND_STATUS = COLLAPSED;
-	RADIX = Hexadecimal;
-	TREE_INDEX = 93;
-	TREE_LEVEL = 1;
-	PARENT = 82;
-}
-
-DISPLAY_LINE
-{
-	CHANNEL = "cpusnoop:cpusnp|addrCache[2]";
-	EXPAND_STATUS = COLLAPSED;
-	RADIX = Hexadecimal;
-	TREE_INDEX = 94;
-	TREE_LEVEL = 1;
-	PARENT = 82;
-}
-
-DISPLAY_LINE
-{
-	CHANNEL = "cpusnoop:cpusnp|addrCache[1]";
-	EXPAND_STATUS = COLLAPSED;
-	RADIX = Hexadecimal;
-	TREE_INDEX = 95;
-	TREE_LEVEL = 1;
-	PARENT = 82;
-}
-
-DISPLAY_LINE
-{
-	CHANNEL = "cpusnoop:cpusnp|addrCache[0]";
-	EXPAND_STATUS = COLLAPSED;
-	RADIX = Hexadecimal;
-	TREE_INDEX = 96;
-	TREE_LEVEL = 1;
-	PARENT = 82;
-}
-
-DISPLAY_LINE
-{
-	CHANNEL = "cpusnoop:cpusnp|dataCacheHi";
-	EXPAND_STATUS = COLLAPSED;
-	RADIX = Hexadecimal;
-	TREE_INDEX = 97;
-	TREE_LEVEL = 0;
-	CHILDREN = 98, 99, 100, 101, 102, 103, 104, 105;
-}
-
-DISPLAY_LINE
-{
-	CHANNEL = "cpusnoop:cpusnp|dataCacheHi[7]";
-	EXPAND_STATUS = COLLAPSED;
-	RADIX = Hexadecimal;
-	TREE_INDEX = 98;
-	TREE_LEVEL = 1;
-	PARENT = 97;
-}
-
-DISPLAY_LINE
-{
-	CHANNEL = "cpusnoop:cpusnp|dataCacheHi[6]";
-	EXPAND_STATUS = COLLAPSED;
-	RADIX = Hexadecimal;
-	TREE_INDEX = 99;
-	TREE_LEVEL = 1;
-	PARENT = 97;
-}
-
-DISPLAY_LINE
-{
-	CHANNEL = "cpusnoop:cpusnp|dataCacheHi[5]";
-	EXPAND_STATUS = COLLAPSED;
-	RADIX = Hexadecimal;
-	TREE_INDEX = 100;
-	TREE_LEVEL = 1;
-	PARENT = 97;
-}
-
-DISPLAY_LINE
-{
-	CHANNEL = "cpusnoop:cpusnp|dataCacheHi[4]";
-	EXPAND_STATUS = COLLAPSED;
-	RADIX = Hexadecimal;
-	TREE_INDEX = 101;
-	TREE_LEVEL = 1;
-	PARENT = 97;
-}
-
-DISPLAY_LINE
-{
-	CHANNEL = "cpusnoop:cpusnp|dataCacheHi[3]";
-	EXPAND_STATUS = COLLAPSED;
-	RADIX = Hexadecimal;
-	TREE_INDEX = 102;
-	TREE_LEVEL = 1;
-	PARENT = 97;
-}
-
-DISPLAY_LINE
-{
-	CHANNEL = "cpusnoop:cpusnp|dataCacheHi[2]";
-	EXPAND_STATUS = COLLAPSED;
-	RADIX = Hexadecimal;
-	TREE_INDEX = 103;
-	TREE_LEVEL = 1;
-	PARENT = 97;
-}
-
-DISPLAY_LINE
-{
-	CHANNEL = "cpusnoop:cpusnp|dataCacheHi[1]";
-	EXPAND_STATUS = COLLAPSED;
-	RADIX = Hexadecimal;
-	TREE_INDEX = 104;
-	TREE_LEVEL = 1;
-	PARENT = 97;
-}
-
-DISPLAY_LINE
-{
-	CHANNEL = "cpusnoop:cpusnp|dataCacheHi[0]";
-	EXPAND_STATUS = COLLAPSED;
-	RADIX = Hexadecimal;
-	TREE_INDEX = 105;
-	TREE_LEVEL = 1;
-	PARENT = 97;
-}
-
-DISPLAY_LINE
-{
-	CHANNEL = "cpusnoop:cpusnp|dataCacheLo";
-	EXPAND_STATUS = COLLAPSED;
-	RADIX = Hexadecimal;
-	TREE_INDEX = 106;
-	TREE_LEVEL = 0;
-	CHILDREN = 107, 108, 109, 110, 111, 112, 113, 114;
-}
-
-DISPLAY_LINE
-{
-	CHANNEL = "cpusnoop:cpusnp|dataCacheLo[7]";
-	EXPAND_STATUS = COLLAPSED;
-	RADIX = Hexadecimal;
-	TREE_INDEX = 107;
-	TREE_LEVEL = 1;
-	PARENT = 106;
-}
-
-DISPLAY_LINE
-{
-	CHANNEL = "cpusnoop:cpusnp|dataCacheLo[6]";
-	EXPAND_STATUS = COLLAPSED;
-	RADIX = Hexadecimal;
-	TREE_INDEX = 108;
-	TREE_LEVEL = 1;
-	PARENT = 106;
-}
-
-DISPLAY_LINE
-{
-	CHANNEL = "cpusnoop:cpusnp|dataCacheLo[5]";
-	EXPAND_STATUS = COLLAPSED;
-	RADIX = Hexadecimal;
-	TREE_INDEX = 109;
-	TREE_LEVEL = 1;
-	PARENT = 106;
-}
-
-DISPLAY_LINE
-{
-	CHANNEL = "cpusnoop:cpusnp|dataCacheLo[4]";
-	EXPAND_STATUS = COLLAPSED;
-	RADIX = Hexadecimal;
-	TREE_INDEX = 110;
-	TREE_LEVEL = 1;
-	PARENT = 106;
-}
-
-DISPLAY_LINE
-{
-	CHANNEL = "cpusnoop:cpusnp|dataCacheLo[3]";
-	EXPAND_STATUS = COLLAPSED;
-	RADIX = Hexadecimal;
-	TREE_INDEX = 111;
-	TREE_LEVEL = 1;
-	PARENT = 106;
-}
-
-DISPLAY_LINE
-{
-	CHANNEL = "cpusnoop:cpusnp|dataCacheLo[2]";
-	EXPAND_STATUS = COLLAPSED;
-	RADIX = Hexadecimal;
-	TREE_INDEX = 112;
-	TREE_LEVEL = 1;
-	PARENT = 106;
-}
-
-DISPLAY_LINE
-{
-	CHANNEL = "cpusnoop:cpusnp|dataCacheLo[1]";
-	EXPAND_STATUS = COLLAPSED;
-	RADIX = Hexadecimal;
-	TREE_INDEX = 113;
-	TREE_LEVEL = 1;
-	PARENT = 106;
-}
-
-DISPLAY_LINE
-{
-	CHANNEL = "cpusnoop:cpusnp|dataCacheLo[0]";
-	EXPAND_STATUS = COLLAPSED;
-	RADIX = Hexadecimal;
-	TREE_INDEX = 114;
-	TREE_LEVEL = 1;
-	PARENT = 106;
-}
-
-DISPLAY_LINE
-{
-	CHANNEL = "cpusnoop:cpusnp|pendWriteHi";
-	EXPAND_STATUS = COLLAPSED;
-	RADIX = Binary;
-	TREE_INDEX = 115;
-	TREE_LEVEL = 0;
-}
-
-DISPLAY_LINE
-{
-	CHANNEL = "cpusnoop:cpusnp|pendWriteLo";
-	EXPAND_STATUS = COLLAPSED;
-	RADIX = Binary;
-	TREE_INDEX = 116;
-	TREE_LEVEL = 0;
-}
-
-DISPLAY_LINE
-{
-	CHANNEL = "nvramCE0";
-	EXPAND_STATUS = COLLAPSED;
-	RADIX = Binary;
-	TREE_INDEX = 117;
-	TREE_LEVEL = 0;
-}
-
-DISPLAY_LINE
-{
-	CHANNEL = "nvramCE1";
-	EXPAND_STATUS = COLLAPSED;
-	RADIX = Binary;
-	TREE_INDEX = 118;
-	TREE_LEVEL = 0;
-}
-
-TIME_BAR
-{
-	TIME = 0;
-	MASTER = TRUE;
-}
-;
diff --git a/old/vgacount.sv b/old/vgacount.sv
deleted file mode 100644
index bdff37e..0000000
--- a/old/vgacount.sv
+++ /dev/null
@@ -1,74 +0,0 @@
-/******************************************************************************
- * SE-VGA
- * VGA signal counter
- * techav
- * 2021-04-06
- ******************************************************************************
- * Low-level VGA signal counter
- *****************************************************************************/
-
-`ifndef VGACOUNT
-    `define VGACOUNT
-
-module vgacount (
-    input wire              nReset,         // system reset signal
-    input wire              clock,          // counter increment clock
-    output logic [9:0]      count,          // count output
-    output wire             nSync,          // sync pulse
-    output wire             activeVid,      // active video signal
-    output wire             activeSE        // secondary active video signal (SE)
-);
-
-parameter   COUNTMAX=800,       // Total dot count per line or line count per frame
-            SYNCBEGIN=592,      // Dot/Line count where sync pulse begins
-            SYNCEND=688,        // Dot/Line count +1 where sync pulse ends
-            ACTBEGIN=576,       // Dot/Line count where VGA active video begins
-            ACTEND=736,         // Dot/Line count +1 where VGA active video ends
-            SEACTBEGIN=512;     // Dot/Line count +1 where SE video window ends
-
-logic [9:0] counter;
-
-// primary counter
-always @(negedge clock or negedge nReset) begin
-    if(nReset == 1'b0) begin
-        counter <= 10'h0;
-    end else begin
-        if (counter < COUNTMAX) begin
-            counter <= counter + 10'h1;
-        end else begin
-            counter <= 10'h0;
-        end
-    end
-end
-
-
-// combinatorial logic derived from the counters
-always_comb begin
-    // output the count signals
-    count <= counter;
-
-    // Sync pulse
-    if(count >= SYNCBEGIN && count < SYNCEND) begin
-        nSync <= 1'b0;
-    end else begin
-        nSync <= 1'b1;
-    end
-
-    // VGA active video range
-    if(count >= ACTBEGIN && count < ACTEND) begin
-        activeVid <= 1'b0;
-    end else begin
-        activeVid <= 1'b1;
-    end
-
-    // SE active video window within VGA active video range
-    if(count >= SEACTBEGIN) begin
-        activeSE <= 1'b0;
-    end else begin
-        activeSE <= 1'b1;
-    end
-end
-
-endmodule
-
-`endif
\ No newline at end of file
diff --git a/old/vgagen.sv b/old/vgagen.sv
deleted file mode 100644
index 06f25c3..0000000
--- a/old/vgagen.sv
+++ /dev/null
@@ -1,35 +0,0 @@
-/******************************************************************************
- * SE-VGA
- * VGA timing generator
- * techav
- * 2021-04-06
- ******************************************************************************
- * Generates VGA timing signals & counters
- *****************************************************************************/
-
-`ifndef VGAGEN
-    `define VGAGEN
-
-`include "vgacount.sv"
-
-module vgagen (
-    input wire             nReset,     // master reset signal
-    input wire             pixClk,     // 25.175MHz pixel clock
-    output logic [9:0]     hCount,     // horizontal pixel count
-    output wire            hActive,    // horizontal VGA active video signal
-    output wire            hSEActive,  // horizontal SE active video signal
-    output wire            nhSync,     // horizontal sync pulse signal
-    output logic [9:0]     vCount,     // vertical line count
-    output wire            vActive,    // vertical VGA active video signal
-    output wire            vSEActive,  // vertical SE active video signal
-    output wire            nvSync      // vertical sync pulse signal
-);
-
-// Generate horizontal signal timing
-vgacount #(800,592,688,576,736,512) hoz(nReset,pixClk,hCount,nhSync,hActive,hSEActive);
-// Generate vertical signal timing
-vgacount #(525,421,423,411,456,342) ver(nReset,nhSync,vCount,nvSync,vActive,vSEActive);
-
-endmodule
-
-`endif
\ No newline at end of file
diff --git a/old/vgaout.sv b/old/vgaout.sv
deleted file mode 100644
index 5bea941..0000000
--- a/old/vgaout.sv
+++ /dev/null
@@ -1,68 +0,0 @@
-/******************************************************************************
- * SE-VGA
- * VGA video output
- * techav
- * 2021-04-06
- ******************************************************************************
- * Fetches video data from VRAM and shifts out
- *****************************************************************************/
-
-`include "vgashiftout.sv"
-
-module vgaout (
-    input wire          pixClock,
-    input wire          nReset,
-    input logic [9:0]   hCount,
-    input logic [9:0]   vCount,
-    input wire          hSEActive,
-    input wire          vSEActive,
-    input logic [7:0]   vramData,
-    output logic [14:0] vramAddr,
-    output wire         nvramOE,
-    output wire         vidOut
-);
-
-wire vidMuxOut; // pixel data shift out
-wire vidActive; // combined active video signal
-
-wire nVidLoad;  // Load VRAM data into shifter
-vgaShiftOut vOut(
-    .nReset(nReset),
-    .clk(pixClock),
-    .nLoad(nVidLoad),
-    .parIn(vramData),
-    .out(vidMuxOut)
-);
-
-always_comb begin
-    if(hCount[2:0] == 0) nVidLoad <= 0;
-    else nVidLoad <= 1;
-
-    // combined video active signal
-    if(hSEActive == 1'b1 && vSEActive == 1'b1) begin
-        vidActive <= 1'b1;
-    end else begin
-        vidActive <= 1'b0;
-    end
-
-    // video data output
-    if(vidActive == 1'b1) begin
-        vidOut <= ~vidMuxOut;
-    end else begin
-        vidOut <= 1'b0;
-    end
-
-    // vram read signal
-    if(vidActive == 1'b1 && hCount[2:0] == 0) begin
-        nvramOE <= 1'b0;
-    end else begin
-        nvramOE <= 1'b1;
-    end
-
-    // vram address signals
-    // these will be mux'd with cpu addresses externally
-    vramAddr[14:6] <= vCount[8:0];
-    vramAddr[5:0]  <= hCount[8:3];
-end
-    
-endmodule
diff --git a/old/vgashiftout.sv b/old/vgashiftout.sv
deleted file mode 100644
index 75abdad..0000000
--- a/old/vgashiftout.sv
+++ /dev/null
@@ -1,84 +0,0 @@
-/******************************************************************************
- * SE-VGA
- * VGA Shift Out
- * techav
- * 2021-04-06
- ******************************************************************************
- * 2-stage shift register for storing & shifting out pixel data
- *****************************************************************************/
-
-`ifndef VGASHIFTOUT
-    `define VGASHIFTOUT
-
-module vgaShiftOut (
-    input wire nReset, clk, nLoad,
-    input logic [7:0] parIn,
-    output wire out
-);
-
-reg [8:0] shiftReg;
-
-always @(negedge clk or negedge nReset) begin
-    if(!nReset) shiftReg <= 0;
-    else begin
-        if(!nLoad) begin
-            shiftReg[8] <= shiftReg[7];
-            shiftReg[7:0] <= parIn;
-        end else begin
-            shiftReg[8:1] <= shiftReg[7:0];
-            shiftReg[0] <= 0;
-        end
-    end
-end
-
-assign out = shiftReg[8];
-
-endmodule
-
-/*
-module vgaShiftOut (
-    input wire nReset,
-    input wire clk,
-    input wire shiftEn,
-    input wire nLoad1,
-    input wire nLoad2,
-    input logic [7:0] parIn,
-    output wire out
-);
-
-    reg [7:0] inReg;
-    reg [7:0] outReg;
-
-    // load data into first stage register on rising edge of pixel clock
-    // if nLoad1 is asserted
-    always @(posedge clk or negedge nReset) begin
-        if(!nReset) inReg <= 0;
-        else if(!nLoad1) inReg <= parIn;
-    end
-
-    // load data into second stage register on falling edge of pixel clock
-    // if nLoad2 is asserted, otherwise if shiftEn is asserted, then shift
-    // video data out. Shift in 0 to fill empty registers
-    always @(negedge clk or negedge nReset) begin
-        if(!nReset) outReg <= 0;
-        else begin
-            if(!nLoad2) outReg <= inReg;
-            else if(shiftEn) begin
-                outReg[7] <= outReg[6];
-                outReg[6] <= outReg[5];
-                outReg[5] <= outReg[4];
-                outReg[4] <= outReg[3];
-                outReg[3] <= outReg[2];
-                outReg[2] <= outReg[1];
-                outReg[1] <= outReg[0];
-                outReg[0] <= 0;
-            end
-        end
-    end
-
-    // high-order bit of the shift register (second stage) is the serial output
-    assign out = outReg[7];
-endmodule
-*/
-
-`endif
\ No newline at end of file
diff --git a/old/vgatest.sv b/old/vgatest.sv
deleted file mode 100644
index ba65b93..0000000
--- a/old/vgatest.sv
+++ /dev/null
@@ -1,75 +0,0 @@
-/******************************************************************************
- * SE-VGA
- * VGA Output Test
- * techav
- * 2021-05-14
- ******************************************************************************
- * Test configuration for testily testing testy test hardware. 
- * This is not a part of the actual configuration. It is a separate top-level
- * entity for testing modules and hardware. Outputs a 512x342 pixel window of
- * alternating black and white pixels in a 640x480 resolution screen.
- *****************************************************************************/
-
-// all the same I's and O's as our proper configuration
-module vgatest (
-    input wire              nReset,     // System reset signal
-    input wire              pixClk,     // 25.175MHz pixel clock
-    output wire             nhSync,     // HSync signal
-    output wire             nvSync,     // VSync signal
-    output wire             vidOut,     // 1-bit Monochrome video signal
-
-    output logic [14:0]     vramAddr,   // VRAM Address bus
-    //inout logic [7:0]       vramData,   // VRAM Data bus
-    input logic [7:0]       vramData,
-    output wire             nvramOE,    // VRAM Read strobe
-    output wire             nvramWE,    // VRAM Write strobe
-    output wire             nvramCE0,   // VRAM Main chip select signal
-    output wire             nvramCE1,   // VRAM Alt chip select signal
-
-    input logic [23:1]      cpuAddr,    // CPU Address bus
-    //input logic [15:0]      cpuData,    // CPU Data bus
-    output logic [15:0]     cpuData,
-    input wire              ncpuAS,     // CPU Address Strobe signal
-    input wire              ncpuUDS,    // CPU Upper Data Strobe signal
-    input wire              ncpuLDS,    // CPU Lower Data Strobe signal
-    input wire              cpuRnW,     // CPU Read/Write select signal
-    input logic [2:0]       ramSize     // Select installed RAM size
-);
-
-logic [9:0] hCount, vCount;
-wire hActive, hSEActive;
-wire vActive, vSEActive;
-
-vgagen vgatiming(
-    .nReset(nReset),
-    .pixClk(pixClk),
-    .hCount(hCount),
-    .hActive(hActive),
-    .hSEActive(hSEActive),
-    .nhSync(nhSync),
-    .vCount(vCount),
-    .vActive(vActive),
-    .vSEActive(vSEActive),
-    .nvSync(nvSync)
-);
-
-reg outTog;
-
-always @(negedge pixClk or negedge nReset) begin
-    if(nReset == 0) begin
-        outTog <= 0;
-    end else begin
-        outTog <= !outTog;
-    end
-end
-
-assign vidOut = outTog & hSEActive & vSEActive;
-assign vramAddr = 0;
-assign nvramOE = 1;
-assign nvramWE = 1;
-assign nvramCE0 = 1;
-assign nvramCE1 = 1;
-assign cpuData[7:0] = ~vramData;
-assign cpuData[15:8] = vramData;
-
-endmodule