Rebuilt state machine again
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techav
parent
6f2f67ef05
commit
5377d05895
303
se-xga.sv
303
se-xga.sv
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@ -40,19 +40,11 @@ logic [10:0] hCount; // 0..1343
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logic [9:0] vCount; // 0..805
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wire nhSyncInner;
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// horizontal counter
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always @(negedge pixClk or negedge nReset) begin
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if(!nReset) hCount <= 0;
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else begin
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if(hCount < 11'd1343) hCount <= hCount + 11'd1;
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else hCount <= 11'd0;
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end
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end
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// vertical counter
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always @(negedge nhSyncInner or negedge nReset) begin
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if(!nReset) vCount <= 0;
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// Primary video sync counters -- Now more synchronous!
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always @(negedge pixClk) begin
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if(hCount < 11'd1343) hCount <= hCount + 11'd1;
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else begin
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hCount <= 11'd0;
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if(vCount < 10'd805) vCount <= vCount + 10'd1;
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else vCount <= 10'd0;
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end
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@ -96,138 +88,79 @@ end
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* VRAM reads, VRAM writes, VIA writes, and idle states
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*****************************************************************************/
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// used to align primary state machine with horizontal counter
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wire [3:0] vSeq = hCount[3:0];
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// define state machine states (Gray code)
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parameter
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P0 = 4'b0000, // VRAM Read 0
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P1 = 4'b0001, // VRAM Read 1
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P2 = 4'b0011, // Idle 0
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P3 = 4'b0010, // Idle 1
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P4 = 4'b0110, // VRAM Write Upper 0
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P5 = 4'b0111, // VRAM Write Upper 1
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P6 = 4'b0101, // VRAM Write Lower 0
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P7 = 4'b0100, // VRAM Write Lower 1
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P8 = 4'b1100, // VIA Write 0
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P9 = 4'b1101, // VIA Write 1
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P10 = 4'b1111, // undefined
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P11 = 4'b1110, // undefined
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P12 = 4'b1010, // undefined
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P13 = 4'b1011, // undefined
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P14 = 4'b1001, // undefined
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P15 = 4'b1000; // undefined
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S0 = 4'b0000, // VRAM Read 0
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S1 = 4'b0001, // VRAM Read 1
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S2 = 4'b0011, // Idle
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S3 = 4'b0010, // VRAM Write Upper 0
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S4 = 4'b0110, // VRAM Write Upper 1
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S5 = 4'b0111, // VRAM Write Lower 0
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S6 = 4'b0101, // VRAM Write Lower 1
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S7 = 4'b0100, // VIA Write
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S8 = 4'b1100, // VSync (to be added later)
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S9 = 4'b1101, // undefined
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S10 = 4'b1111, // undefined
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S11 = 4'b1110, // undefined
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S12 = 4'b1010, // undefined
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S13 = 4'b1011, // undefined
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S14 = 4'b1001, // undefined
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S15 = 4'b1000; // undefined
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logic [3:0] pState;
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// And here is the much simplified primary state machine
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always @(negedge pixClk or negedge nReset) begin
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if(!nReset) pState <= P0;
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if(!nReset) pState <= S2; // resync on reset by jumping to idle state
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else begin
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case (pState)
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P0 : begin
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// first VRAM read state, always move to P1
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pState <= P1;
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end
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P1 : begin
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// move to appropriate VRAM write state or idle
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if(cpuUWriteReq && !cpuUWriteSrv) pState <= P4;
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else if(cpuLWriteReq && !cpuLWriteSrv) pState <= P6;
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else if(cpuVIAReq && !cpuVIASrv) pState <= P8;
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else pState <= P2;
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end
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P2 : begin
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// first idle state.
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// we'll use this state to make sure we're synchronized with
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// the tick-tock clock states, so if we've made it here on a
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// tock state, stay here until the next tick state.
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if(tick) pState <= P3;
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else pState <= P2;
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end
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P3 : begin
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// second idle state. Here is where things get fun.
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case (vidSeq)
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7 : begin
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pState <= P0;
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end
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6 : begin
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if(cpuUWriteReq && !cpuUWriteSrv && !cpuLWriteReq) pState <= P4;
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else if(cpuLWriteReq && !cpuLWriteSrv) pState <= P6;
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else if(cpuVIAReq && !cpuVIASrv) pState <= P8;
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else pState <= P2;
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end
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default: begin
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if(cpuUWriteReq && !cpuUWriteSrv) pState <= P4;
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else if(cpuLWriteReq && !cpuLWriteSrv) pState <= P6;
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else if(cpuVIAReq && !cpuVIASrv) pState <= P8;
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else pState <= P2;
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end
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endcase
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end
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P4 : begin
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// first VRAM Write Upper state, always move to P5
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pState <= P5;
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end
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P5 : begin
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// second VRAM Write Upper state,
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if(vidSeq == 7) pState <= P0;
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else if(cpuBufAddr && !ncpuLDS) pState <= P6;
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else pState <= P2;
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end
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P6 : begin
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// first VRAM Write Lower state, always move to P7
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pState <= P7;
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end
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P7 : begin
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// second VRAM Write Lower state
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if(vidSeq == 7) pState <= P0;
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else pState <= P2;
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end
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P8 : begin
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// first VIA write state, always move to P9
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pState <= P9;
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end
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P9 : begin
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// second VIA write state
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vidBufSel <= ~cpuData[14];
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if(vidSeq == 7) pState <= P0;
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else pState <= P2;
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end
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default: begin
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// how did we end up here? We need to align with the sequence
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// counter before we move to S0
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if(vidSeq == 7 && tock) pState <= P0;
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else if(tick) pState <= P3;
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else pState <= P2;
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case(pState)
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S0: pState <= S1; // first VRAM read state, always move to S1
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S3: pState <= S4; // first UDS write state, always move to S4
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S5: pState <= S6; // first LDS write state, always move to S6
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/*S7: begin
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pState <= S2;
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end*/
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S2: begin
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// here is where everything actually happens.
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if(vSeq == 4'hF) pState <= S0; // time for a read state
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else if(cpuUWriteReq && !cpuUWriteSrv && vSeq < 4'hD) pState <= S3;
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else if(cpuLWriteReq && !cpuLWriteSrv && vSeq < 4'hD) pState <= S5;
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else if(cpuVIAReq && !cpuVIASrv && vSeq < 4'hE) pState <= S7;
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else pState <= S2;
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end
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default: pState <= S2; // everyone ends up at S2 (idle)
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endcase
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end
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end
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// primary signal combination, based on the state machine above
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// primary VRAM signal combination, based on the primary state machine
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always_comb begin
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// VRAM Read strobe
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if((pState == P0 || pState == P1) && vidActive) nvramOE <= 0;
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// VRAM Read Strobe
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if((pState == S0 || pState == S1) && hLoad) nvramOE <= 0;
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else nvramOE <= 1;
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// VRAM Write strobe
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if(pState == P4 || pState == P6) nvramWE <= 0;
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// VRAM Write Strobe
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if(pState == S3 || pState == S5) nvramWE <= 0;
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else nvramWE <= 1;
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// VRAM Chip Enable signals
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// VRAM Chip Enable Signals
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case(pState)
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P0, P1 : begin
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if(vidActive) begin
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nvramCE0 <= hCount[4];
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nvramCE1 <= ~hCount[4];
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S0, S1: begin
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if(hLoad) begin
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nvramCE0 <= ~vidBufSel;
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nvramCE1 <= vidBufSel;
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end else begin
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nvramCE0 <= 1;
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nvramCE1 <= 1;
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end
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end
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P4, P5 : begin
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nvramCE0 <= 0;
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nvramCE1 <= 1;
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end
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P6, P7 : begin
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nvramCE0 <= 1;
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nvramCE1 <= 0;
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S3, S4, S5, S6: begin
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nvramCE0 <= ~cpuBufSel;
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nvramCE1 <= cpuBufSel;
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end
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default: begin
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nvramCE0 <= 1;
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@ -235,30 +168,37 @@ always_comb begin
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end
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endcase
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// VRAM Address bus
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// VRAM Address Bus
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case(pState)
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P0, P1 : begin
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S0, S1: begin
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// address bus for read cycles
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if(hLoad) begin
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vramAddr[14] <= vidBufSel;
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vramAddr[13:5] <= vCount[9:1];
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vramAddr[4:0] <= hCount[9:5];
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vramAddr[14:6] <= vCount[9:1];
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vramAddr[5:0] <= hCount[9:4];
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end else begin
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vramAddr <= 0;
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end
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end
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P4, P5, P6, P7 : begin
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vramAddr[14] <= cpuBufSel;
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vramAddr[13:0] <= cpuAddr[14:1] - 14'h1380;
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S3, S4: begin
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// address bus for upper write cycles
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vramAddr[14:1] <= cpuAddr[14:1] - 14'h1380;
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vramAddr[0] <= 0;
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end
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S5, S6: begin
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// address bus for lower write cycles
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vramAddr[14:1] <= cpuAddr[14:1] - 14'h1380;
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vramAddr[0] <= 1;
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end
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default: begin
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// address bus for idle cycles
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vramAddr <= 0;
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end
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endcase
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// VRAM Data bus
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case(pState)
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P4, P5 : vramData <= cpuData[15:8];
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P6, P7 : vramData <= cpuData[7:0];
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S3, S4 : vramData <= cpuData[15:8];
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S5, S6 : vramData <= cpuData[7:0];
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default: vramData <= 8'hZ;
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endcase
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end
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@ -270,39 +210,27 @@ end
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* signals and see the strapped pattern output on screen.
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*****************************************************************************/
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logic [8:0] vidData; // the video data we are displaying
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wire [2:0] vidSeq; // sequence counter, derived from hCount
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wire tick, tock; // even/odd pulses of pixel clock divided by 2
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//wire [2:0] vidSeq; // sequence counter, derived from hCount
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//wire tick, tock; // even/odd pulses of pixel clock divided by 2
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assign vidSeq = hCount[3:1];
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assign tick = !hCount[0];
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assign tock = hCount[0];
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// for some reason changing this function to use pState==P1 instead of the old
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// tock && vidSeq==0 caused utilization to jump up 10 macrocells, and the
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// monitor reported sync out of range. No idea what happened there so we'll
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// leave this function as it is, since it seems to be working.
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always @(negedge pixClk or negedge nReset) begin
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if(!nReset) vidData <= 0;
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else begin
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if(tock && hLoad && vidSeq == 3'd0) begin
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//if(pState == P1 && hLoad) begin
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// store the VRAM data in vidData[7:0]
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vidData[7:0] <= vramData;
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end else if(tick && hLoad) begin
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// shift vidData
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vidData[8:1] <= vidData[7:0];
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vidData[0] <= 0;
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end
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// output shift register
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always @(posedge pixClk) begin
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if(pState == S1 && hLoad) begin
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// store VRAM data in shift register
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vidData[7:0] <= vramData;
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end else if(!hCount[0] && vidActive) begin
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// shift out video data
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vidData[8:1] <= vidData[7:0];
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vidData[0] <= 0;
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end
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end
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// final video output
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always_comb begin
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// here is where the shifted video data actually gets output
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if(vidActive) vidOut <= ~vidData[8];
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else vidOut <= 0;
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end
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/******************************************************************************
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* CPU Bus Snooping
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* Watch the CPU bus for writes to the video buffer regions of memory and write
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@ -332,34 +260,49 @@ end
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// keep track of pending CPU write requests and whether they have been serviced
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wire cpuUWriteReq, cpuLWriteReq, cpuVIAReq;
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reg cpuUWriteSrv, cpuLWriteSrv, cpuVIASrv;
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wire cpuBufSel = ~cpuAddr[15];
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wire cpuBufSel;
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wire cpuBufAddr;
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reg vidBufSel;
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// these are some helpful signals that shortcut the CPU buffer & VIA addresses
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always_comb begin
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// remember cpuAddr is shifted right by one since 68000 does not output A0
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if(!ncpuAS && !cpuRnW
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&& cpuAddr[23:22] == 2'b00 // initial constant
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&& ramSize == cpuAddr[21:19] // ram size selection
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&& cpuAddr[18:16] == 3'b111 // trailing constant
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// next bit is main/alt select
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&& (cpuAddr[14:1] >= 14'h1380 // bottom of buffer range (0x2700>>1)
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&& cpuAddr[14:1] <= 14'h3e3f) // top of buffer range (0x7C70>>1)
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) begin
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cpuBufAddr <= 1'b1;
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&& !cpuAddr[23] && !cpuAddr[22] // first two bits always 0
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&& !(cpuAddr[21] ^ ramSize[2]) // compare with RAM Size bits
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&& !(cpuAddr[20] ^ ramSize[1])
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&& !(cpuAddr[19] ^ ramSize[0])
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&& cpuAddr[18] && cpuAddr[17] // next three bits always 1
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&& cpuAddr[16] // skip 15, it selects buffers
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&& (cpuAddr[14] || cpuAddr[13]) // if neither 13|14 then not buffer
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) begin
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cpuBufAddr <= 1;
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end else begin
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cpuBufAddr <= 1'b0;
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cpuBufAddr <= 0;
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end
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cpuBufSel <= ~cpuAddr[15]; // address bit 15 selects buffer
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if(cpuBufAddr && !ncpuUDS) cpuUWriteReq <= 1;
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else cpuUWriteReq <= 0;
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if(cpuBufAddr && !ncpuLDS) cpuLWriteReq <= 1;
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else cpuLWriteReq <= 0;
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if(!ncpuAS && !cpuRnW && !ncpuUDS
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&& cpuAddr[23:19] == 5'h1D
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&& cpuAddr[12:8] == 5'h1F) cpuVIAReq <= 1;
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// VIA is in address block $E8,0000 - $EF,FFFF
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// VIA register select pins (RS[3:0]) are wired to cpuAddr[12:9]
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// VIA Output Register A is selected when RS[3:0]==$F
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/*if(!ncpuAS && !cpuRnW && !ncpuUDS
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&& cpuAddr[23] && cpuAddr[22] // VIA Address Select
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&& cpuAddr[21] && !cpuAddr[20]
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&& cpuAddr[19]
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&& cpuAddr[12] && cpuAddr[11] // VIA ORA
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&& cpuAddr[10] && cpuAddr[9]
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) cpuVIAReq <= 1;
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else cpuVIAReq <= 0;*/
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// Mac ROM addresses Data Register A as vBase+vBufA:
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// $EF,E1FE + (512*15) = $EF,FFFE
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// shift right by one because no A0 and we get $77,FFFF
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// This bit is giving me hell, so let's expand it
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if(ncpuAS==0 && cpuRnW==0 && ncpuUDS==0
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&& cpuAddr == 22'h77FFFF) cpuVIAReq <= 1;
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else cpuVIAReq <= 0;
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end
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@ -376,20 +319,18 @@ always @(posedge pixClk or posedge ncpuAS) begin
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cpuLWriteSrv <= 0;
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cpuVIASrv <= 0;
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end else begin
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if(cpuUWriteReq && pState == P4) cpuUWriteSrv <= 1;
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if(cpuLWriteReq && pState == P6) cpuLWriteSrv <= 1;
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if(cpuVIAReq && pState == P8) cpuVIASrv <= 1;
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if(cpuUWriteReq && pState == S3) cpuUWriteSrv <= 1;
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if(cpuLWriteReq && pState == S5) cpuLWriteSrv <= 1;
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if(cpuVIAReq && pState == S7) cpuVIASrv <= 1;
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end
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end
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end
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// when servicing a CPU VIA request, read the CPU data bus to set the video
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// buffer selection bit. Main: 1, Alt: 0
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/*always @(posedge pixClk or negedge nReset) begin
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if(!nReset) vidBufSel <= 1;
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else if(pState == P8) begin
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vidBufSel <= ~cpuData[14];
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end
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end*/
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// store the video buffer selection bit
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always @(posedge pixClk or negedge nReset) begin
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if(!nReset) vidBufSel <= 0;
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// fine. no video buffer select. we use Main only.
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//else if(pState == S7) vidBufSel <= ~cpuData[14];
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end
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endmodule
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