diff --git a/cpusnoop.sv b/cpusnoop.sv
index 89bde9b..84409b5 100644
--- a/cpusnoop.sv
+++ b/cpusnoop.sv
@@ -24,7 +24,25 @@ module cpusnoop (
     output wire             nvramWE,    // VRAM Write strobe
     input logic [2:0]       ramSize     // CPU RAM size selection
 );
+
+    wire pendWriteLo;           // low byte write to VRAM pending
+    wire pendWriteHi;           // high byte write to VRAM pending
+    logic [13:0] addrCache;     // store address for cpu writes to framebuffer
+    logic [7:0] dataCacheLo;    // store data for cpu writes to low byte
+    logic [7:0] dataCacheHi;    // store data for cpu writes to high byte
+    wire cpuBufSel;             // is CPU accessing frame buffer?
+    logic [2:0] cycleState;     // state machine state
+
+    // define state machine states
+    parameter
+        S0  =   3'h0,
+        S1  =   3'h1,
+        S2  =   3'h2,
+        S3  =   3'h3,
+        S4  =   3'h4,
+        S5  =   3'h5;
     
+    // when cpu addresses the framebuffer, set our enable signal
     /* framebuffer starts $5900 below the top of RAM
      * ramSize is used to mask the cpuAddr bits [21:9] to select the amount
      * of memory installed in the computer. Not all possible ramSize selections
@@ -40,22 +58,143 @@ module cpusnoop (
      *    $1      $0fa700       $100000     1.0MB       Y   [256kB 256kB][256kB 256kB]
      *    $0      $07a700       $080000     0.5MB       Y   [256kB 256kB][ ---   --- ]
      */
-
-    wire pendWriteLo;           // low byte write to VRAM pending
-    wire pendWriteHi;           // high byte write to VRAM pending
-    logic [13:0] addrCache;     // store address for cpu writes to framebuffer
-    logic [7:0] dataCacheLo;    // store data for cpu writes to low byte
-    logic [7:0] dataCacheHi;    // store data for cpu writes to high byte
-    wire cpuBufSel;             // is CPU accessing frame buffer?
-
-    // when cpu addresses the framebuffer, set our enable signal
     always_comb begin
+        // remember cpuAddr is shifted right by one since 68000 does not output A0
         if(ramSize == cpuAddr[20:18] && cpuAddr[22:21] == 2'b00 && cpuAddr[17:14] == 4'b1111) begin
             cpuBufSel <= 1'b1;
         end else begin
             cpuBufSel <= 1'b0;
         end
     end
+    
+    // CPU Write to VRAM state machine
+    always @(negedge pixClock or negedge nReset) begin
+        if(!nReset) begin
+            cycleState <= S0;
+            pendWriteHi <= 0;
+            pendWriteLo <= 0;
+            addrCache <= 0;
+            dataCacheHi <= 0;
+            dataCacheLo <= 0;
+        end else begin
+            case (cycleState)
+                S0 : begin
+                    // idle state, wait for valid address and ncpuAS asserted
+                    if(ncpuAS == 0 && cpuBufSel == 1 && cpuRnW == 0) begin
+                        cycleState <= S1;
+                    end else begin
+                        cycleState <= S0;
+                    end
+                end
+                S1 : begin
+                    // wait for either ncpuUDS or ncpuLDS to assert
+                    // if ncpuAS negates first, then abort back to S0
+                    if(ncpuAS == 1) begin
+                        // cpu aborted cycle
+                        cycleState <= S0;
+                    end else if(ncpuUDS == 0 || ncpuLDS == 0) begin
+                        if (ncpuUDS == 0) begin
+                            pendWriteHi <= 1;
+                            dataCacheHi <= cpuData[15:8];
+                        end
+                        if (ncpuLDS == 0) begin
+                            pendWriteLo <= 1;
+                            dataCacheLo <= cpuData[7:0];
+                        end
+
+                        // Valid CPU-VRAM cycle, so subtract constant $1380 from the 
+                        // cpu address and store the result in addrCache register.
+                        // Constant $1380 corresponds to $2700 shifted right by 1.
+                        // Once the selection bits above are masked out, we're left
+                        // with buffer addresses starting at $2700
+                        // e.g. with 4MB of RAM, fram buffer starts at $3FA700
+                        //   buffer address: 0011 1111 1010 0111 0000 0000 = $3FA700
+                        //   vram addr mask: 0000 0000 0011 1111 1111 1111 - $003FFF
+                        //   vram address:   0000 0000 0010 0111 0000 0000 = $002700
+                        // Since CPU is 16-bit and does not provide A0, our cpuAddr
+                        // signals are shifted right by one, so we need to do the same
+                        // to our offset before subtracting it from cpuAddr
+                        //   offset:         0000 0000 0010 0111 0000 0000 = $002700
+                        //   shifted offset: 0000 0000 0001 0011 1000 0000 = $001380
+                        addrCache <= cpuAddr[13:0] - 14'h1380;
+
+                        cycleState <= S2;
+                    end else begin
+                        cycleState <= S1;
+                    end
+                end
+                S2 : begin
+                    // wait for sequence
+                    if(pendWriteHi == 1 && pendWriteLo == 1 && seq < 5) begin
+                        // we have enough time to write both before the next VRAM read
+                        cycleState <= S3;
+                    end else if(seq < 6) begin
+                        // we have enough time to write the one pending before next VRAM read
+                        if(pendWriteLo == 0) begin
+                            cycleState <= S4;
+                        end else begin
+                            cycleState <= S3;
+                        end
+                    end else begin
+                        // no time for a write sequence, wait
+                        cycleState <= S2;
+                    end
+                end
+                S3 : begin
+                    // write CPU low byte to VRAM
+                    if(pendWriteHi == 1) begin
+                        cycleState <= S4;
+                    end else begin
+                        cycleState <= S5;
+                    end
+                    pendWriteLo <= 0;
+                end
+                S4 : begin
+                    // write CPU high byte to VRAM
+                    cycleState <= S5;
+                    pendWriteHi <= 0;
+                end
+                S5 : begin
+                    // wait for CPU to negate both ncpuUDS and ncpuLDS
+                    if(ncpuUDS == 1 && ncpuLDS == 1) begin
+                        cycleState <= S0;
+                    end else begin
+                        cycleState <= S5;
+                    end
+                end
+                default: begin
+                    // how did we end up here? reset to S0
+                    cycleState <= S0;
+                end
+            endcase
+        end
+    end
+
+    always_comb begin
+        vramAddr[14:1] <= addrCache[13:0];
+        if(cycleState == S4) begin
+            vramAddr[0] <= 1;
+        end else begin
+            vramAddr[0] <= 0;
+        end
+
+        if(cycleState == S3 || cycleState == S4) begin
+            nvramWE <= 0;
+        end else begin
+            nvramWE <= 1;
+        end
+
+        if(cycleState == S3) begin
+            vramDataOut <= dataCacheLo;
+        end else if(cycleState == S4) begin
+            vramDataOut <= dataCacheHi;
+        end else begin
+            vramDataOut <= 0;
+        end
+    end
+
+/*
+    
 
     // when cpu addresses the framebuffer, save the address
     always @(negedge ncpuAS or negedge nReset) begin
@@ -64,7 +203,8 @@ module cpusnoop (
         end else begin
             // here we match our ramSize jumpers and constants to confirm
             // the CPU is accessing the primary frame buffer
-            if(cpuBufSel == 1'b1) begin
+            //if(cpuBufSel == 1'b1) begin
+            if(ramSize == cpuAddr[20:18] && cpuAddr[22:21] == 2'b00 && cpuAddr[17:14] == 4'b1111) begin
                 // We have a match, so subtract constant $1380 from the 
                 // cpu address and store the result in addrCache register.
                 // Constant $1380 corresponds to $2700 shifted right by 1.
@@ -107,7 +247,7 @@ module cpusnoop (
     end
 
     // set pending flags for cpu accesses & clear when that cycle comes back around
-    always @(negedge pixClock or negedge nReset) begin
+    /*always @(negedge pixClock or negedge nReset) begin
         if(nReset == 1'b0) begin
             pendWriteLo <= 1'b0;
             pendWriteHi <= 1'b0;
@@ -120,23 +260,24 @@ module cpusnoop (
                     pendWriteLo <= 1'b1;
                 end
             end else begin
-                if(seq == 3'h1) begin
+                if(seq == 1 || seq == 3 || seq == 5) begin
                     pendWriteLo <= 1'b0;
                 end
-                if(seq == 3'h2) begin
+                if(seq == 2 || seq == 4 || seq == 6) begin
                     pendWriteHi <= 1'b0;
                 end
             end
         end
-    end
+    end*/
+/*
 
     always_comb begin
         vramAddr[14:1] <= addrCache[13:0];
-        if(pendWriteLo == 1'b1 && seq == 3'h1) begin
+        if(pendWriteLo == 1'b1 && (seq == 1 || seq == 3 || seq == 5)) begin
             vramAddr[0] <= 1'b0;
             nvramWE <= 1'b0;
             vramDataOut <= dataCacheLo;
-        end else if(pendWriteHi == 1'b1 && seq == 3'h2) begin
+        end else if(pendWriteHi == 1'b1 && (seq == 2 || seq == 4 || seq == 6)) begin
             vramAddr[0] <= 1'b1;
             nvramWE <= 1'b0;
             vramDataOut <= dataCacheHi;
@@ -146,4 +287,5 @@ module cpusnoop (
             vramDataOut <= 8'h0;
         end
     end
+*/
 endmodule
\ No newline at end of file
diff --git a/primitives/primitives.sv b/primitives/primitives.sv
index 6336bb8..3c51e82 100644
--- a/primitives/primitives.sv
+++ b/primitives/primitives.sv
@@ -117,7 +117,7 @@ module vidShiftOut (
     input wire vidActive,
     input logic [2:0] seq,
     input logic [7:0] parIn,
-    output wire out,
+    output wire out
 );
     /* Shift register functioning similar to a 74597, with 8-bit input latch
      * and 8-bit PISO shift register output stage.
diff --git a/se-vga.sv b/se-vga.sv
index 4aa307b..acba970 100644
--- a/se-vga.sv
+++ b/se-vga.sv
@@ -35,6 +35,7 @@ wire hActive;
 wire hSEActive;
 wire vActive;
 wire vSEActive;
+wire nvramWEpre;
 
 logic [14:0] vidVramAddr;
 logic [14:0] cpuVramAddr;
@@ -83,13 +84,13 @@ cpusnoop cpusnp(
     .cpuClk(cpuClk),
     .vramAddr(cpuVramAddr),
     .vramDataOut(cpuVramData),
-    .nvramWE(nvramWE),
+    .nvramWE(nvramWEpre),
     .ramSize(ramSize)
 );
 
 always_comb begin
     // vramAddr muxing
-    if(nvramWE == 1'b0) begin
+    if(nvramWEpre == 1'b0) begin
         vramAddr <= cpuVramAddr;
     end else begin
         vramAddr <= vidVramAddr;
@@ -97,7 +98,7 @@ always_comb begin
 end
 
 always_comb begin
-    if(nvramWE == 1'b0) begin
+    if(nvramWEpre == 1'b0) begin
         vramData <= cpuVramData;
     end else begin
         vramData <= 8'bZZZZZZZZ;
@@ -105,4 +106,6 @@ always_comb begin
     vidVramData <= vramData;
 end
 
+assign nvramWE = nvramWEpre | pixClk;
+
 endmodule
\ No newline at end of file
diff --git a/sevga.vwf b/sevga.vwf
index 8901c80..156f87f 100644
--- a/sevga.vwf
+++ b/sevga.vwf
@@ -847,6 +847,356 @@ GROUP("cpuAddr")
 	MEMBERS = "cpuAddr[1]", "cpuAddr[2]", "cpuAddr[3]", "cpuAddr[4]", "cpuAddr[5]", "cpuAddr[6]", "cpuAddr[7]", "cpuAddr[8]", "cpuAddr[9]", "cpuAddr[10]", "cpuAddr[11]", "cpuAddr[12]", "cpuAddr[13]", "cpuAddr[14]", "cpuAddr[15]", "cpuAddr[16]", "cpuAddr[17]", "cpuAddr[18]", "cpuAddr[19]", "cpuAddr[20]", "cpuAddr[21]", "cpuAddr[22]", "cpuAddr[23]";
 }
 
+SIGNAL("cpusnoop:cpusnp|addrCache")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = BUS;
+	WIDTH = 14;
+	LSB_INDEX = 0;
+	DIRECTION = REGISTERED;
+	PARENT = "";
+}
+
+SIGNAL("cpusnoop:cpusnp|addrCache[13]")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = REGISTERED;
+	PARENT = "cpusnoop:cpusnp|addrCache";
+}
+
+SIGNAL("cpusnoop:cpusnp|addrCache[12]")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = REGISTERED;
+	PARENT = "cpusnoop:cpusnp|addrCache";
+}
+
+SIGNAL("cpusnoop:cpusnp|addrCache[11]")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = REGISTERED;
+	PARENT = "cpusnoop:cpusnp|addrCache";
+}
+
+SIGNAL("cpusnoop:cpusnp|addrCache[10]")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = REGISTERED;
+	PARENT = "cpusnoop:cpusnp|addrCache";
+}
+
+SIGNAL("cpusnoop:cpusnp|addrCache[9]")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = REGISTERED;
+	PARENT = "cpusnoop:cpusnp|addrCache";
+}
+
+SIGNAL("cpusnoop:cpusnp|addrCache[8]")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = REGISTERED;
+	PARENT = "cpusnoop:cpusnp|addrCache";
+}
+
+SIGNAL("cpusnoop:cpusnp|addrCache[7]")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = REGISTERED;
+	PARENT = "cpusnoop:cpusnp|addrCache";
+}
+
+SIGNAL("cpusnoop:cpusnp|addrCache[6]")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = REGISTERED;
+	PARENT = "cpusnoop:cpusnp|addrCache";
+}
+
+SIGNAL("cpusnoop:cpusnp|addrCache[5]")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = REGISTERED;
+	PARENT = "cpusnoop:cpusnp|addrCache";
+}
+
+SIGNAL("cpusnoop:cpusnp|addrCache[4]")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = REGISTERED;
+	PARENT = "cpusnoop:cpusnp|addrCache";
+}
+
+SIGNAL("cpusnoop:cpusnp|addrCache[3]")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = REGISTERED;
+	PARENT = "cpusnoop:cpusnp|addrCache";
+}
+
+SIGNAL("cpusnoop:cpusnp|addrCache[2]")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = REGISTERED;
+	PARENT = "cpusnoop:cpusnp|addrCache";
+}
+
+SIGNAL("cpusnoop:cpusnp|addrCache[1]")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = REGISTERED;
+	PARENT = "cpusnoop:cpusnp|addrCache";
+}
+
+SIGNAL("cpusnoop:cpusnp|addrCache[0]")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = REGISTERED;
+	PARENT = "cpusnoop:cpusnp|addrCache";
+}
+
+SIGNAL("cpusnoop:cpusnp|dataCacheHi")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = BUS;
+	WIDTH = 8;
+	LSB_INDEX = 0;
+	DIRECTION = REGISTERED;
+	PARENT = "";
+}
+
+SIGNAL("cpusnoop:cpusnp|dataCacheHi[7]")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = REGISTERED;
+	PARENT = "cpusnoop:cpusnp|dataCacheHi";
+}
+
+SIGNAL("cpusnoop:cpusnp|dataCacheHi[6]")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = REGISTERED;
+	PARENT = "cpusnoop:cpusnp|dataCacheHi";
+}
+
+SIGNAL("cpusnoop:cpusnp|dataCacheHi[5]")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = REGISTERED;
+	PARENT = "cpusnoop:cpusnp|dataCacheHi";
+}
+
+SIGNAL("cpusnoop:cpusnp|dataCacheHi[4]")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = REGISTERED;
+	PARENT = "cpusnoop:cpusnp|dataCacheHi";
+}
+
+SIGNAL("cpusnoop:cpusnp|dataCacheHi[3]")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = REGISTERED;
+	PARENT = "cpusnoop:cpusnp|dataCacheHi";
+}
+
+SIGNAL("cpusnoop:cpusnp|dataCacheHi[2]")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = REGISTERED;
+	PARENT = "cpusnoop:cpusnp|dataCacheHi";
+}
+
+SIGNAL("cpusnoop:cpusnp|dataCacheHi[1]")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = REGISTERED;
+	PARENT = "cpusnoop:cpusnp|dataCacheHi";
+}
+
+SIGNAL("cpusnoop:cpusnp|dataCacheHi[0]")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = REGISTERED;
+	PARENT = "cpusnoop:cpusnp|dataCacheHi";
+}
+
+SIGNAL("cpusnoop:cpusnp|dataCacheLo")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = BUS;
+	WIDTH = 8;
+	LSB_INDEX = 0;
+	DIRECTION = REGISTERED;
+	PARENT = "";
+}
+
+SIGNAL("cpusnoop:cpusnp|dataCacheLo[7]")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = REGISTERED;
+	PARENT = "cpusnoop:cpusnp|dataCacheLo";
+}
+
+SIGNAL("cpusnoop:cpusnp|dataCacheLo[6]")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = REGISTERED;
+	PARENT = "cpusnoop:cpusnp|dataCacheLo";
+}
+
+SIGNAL("cpusnoop:cpusnp|dataCacheLo[5]")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = REGISTERED;
+	PARENT = "cpusnoop:cpusnp|dataCacheLo";
+}
+
+SIGNAL("cpusnoop:cpusnp|dataCacheLo[4]")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = REGISTERED;
+	PARENT = "cpusnoop:cpusnp|dataCacheLo";
+}
+
+SIGNAL("cpusnoop:cpusnp|dataCacheLo[3]")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = REGISTERED;
+	PARENT = "cpusnoop:cpusnp|dataCacheLo";
+}
+
+SIGNAL("cpusnoop:cpusnp|dataCacheLo[2]")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = REGISTERED;
+	PARENT = "cpusnoop:cpusnp|dataCacheLo";
+}
+
+SIGNAL("cpusnoop:cpusnp|dataCacheLo[1]")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = REGISTERED;
+	PARENT = "cpusnoop:cpusnp|dataCacheLo";
+}
+
+SIGNAL("cpusnoop:cpusnp|dataCacheLo[0]")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = REGISTERED;
+	PARENT = "cpusnoop:cpusnp|dataCacheLo";
+}
+
+SIGNAL("cpusnoop:cpusnp|pendWriteHi")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = REGISTERED;
+	PARENT = "";
+}
+
+SIGNAL("cpusnoop:cpusnp|pendWriteLo")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = REGISTERED;
+	PARENT = "";
+}
+
 TRANSITION_LIST("cpuAddr[1]")
 {
 	NODE
@@ -861,7 +1211,9 @@ TRANSITION_LIST("cpuAddr[2]")
 	NODE
 	{
 		REPEAT = 1;
-		LEVEL 0 FOR 33000.0;
+		LEVEL 0 FOR 960.0;
+		LEVEL 1 FOR 320.0;
+		LEVEL 0 FOR 31720.0;
 	}
 }
 
@@ -888,7 +1240,11 @@ TRANSITION_LIST("cpuAddr[5]")
 	NODE
 	{
 		REPEAT = 1;
-		LEVEL 0 FOR 33000.0;
+		LEVEL 0 FOR 600.0;
+		LEVEL 1 FOR 320.0;
+		LEVEL 0 FOR 40.0;
+		LEVEL 1 FOR 320.0;
+		LEVEL 0 FOR 31720.0;
 	}
 }
 
@@ -915,7 +1271,11 @@ TRANSITION_LIST("cpuAddr[8]")
 	NODE
 	{
 		REPEAT = 1;
-		LEVEL 0 FOR 33000.0;
+		LEVEL 0 FOR 600.0;
+		LEVEL 1 FOR 320.0;
+		LEVEL 0 FOR 40.0;
+		LEVEL 1 FOR 320.0;
+		LEVEL 0 FOR 31720.0;
 	}
 }
 
@@ -924,7 +1284,11 @@ TRANSITION_LIST("cpuAddr[9]")
 	NODE
 	{
 		REPEAT = 1;
-		LEVEL 0 FOR 33000.0;
+		LEVEL 0 FOR 600.0;
+		LEVEL 1 FOR 320.0;
+		LEVEL 0 FOR 40.0;
+		LEVEL 1 FOR 320.0;
+		LEVEL 0 FOR 31720.0;
 	}
 }
 
@@ -933,7 +1297,11 @@ TRANSITION_LIST("cpuAddr[10]")
 	NODE
 	{
 		REPEAT = 1;
-		LEVEL 0 FOR 33000.0;
+		LEVEL 0 FOR 600.0;
+		LEVEL 1 FOR 320.0;
+		LEVEL 0 FOR 40.0;
+		LEVEL 1 FOR 320.0;
+		LEVEL 0 FOR 31720.0;
 	}
 }
 
@@ -960,7 +1328,11 @@ TRANSITION_LIST("cpuAddr[13]")
 	NODE
 	{
 		REPEAT = 1;
-		LEVEL 0 FOR 33000.0;
+		LEVEL 0 FOR 600.0;
+		LEVEL 1 FOR 320.0;
+		LEVEL 0 FOR 40.0;
+		LEVEL 1 FOR 320.0;
+		LEVEL 0 FOR 31720.0;
 	}
 }
 
@@ -978,7 +1350,11 @@ TRANSITION_LIST("cpuAddr[15]")
 	NODE
 	{
 		REPEAT = 1;
-		LEVEL 0 FOR 33000.0;
+		LEVEL 0 FOR 600.0;
+		LEVEL 1 FOR 320.0;
+		LEVEL 0 FOR 40.0;
+		LEVEL 1 FOR 320.0;
+		LEVEL 0 FOR 31720.0;
 	}
 }
 
@@ -987,7 +1363,11 @@ TRANSITION_LIST("cpuAddr[16]")
 	NODE
 	{
 		REPEAT = 1;
-		LEVEL 0 FOR 33000.0;
+		LEVEL 0 FOR 600.0;
+		LEVEL 1 FOR 320.0;
+		LEVEL 0 FOR 40.0;
+		LEVEL 1 FOR 320.0;
+		LEVEL 0 FOR 31720.0;
 	}
 }
 
@@ -996,7 +1376,11 @@ TRANSITION_LIST("cpuAddr[17]")
 	NODE
 	{
 		REPEAT = 1;
-		LEVEL 0 FOR 33000.0;
+		LEVEL 0 FOR 600.0;
+		LEVEL 1 FOR 320.0;
+		LEVEL 0 FOR 40.0;
+		LEVEL 1 FOR 320.0;
+		LEVEL 0 FOR 31720.0;
 	}
 }
 
@@ -1005,7 +1389,11 @@ TRANSITION_LIST("cpuAddr[18]")
 	NODE
 	{
 		REPEAT = 1;
-		LEVEL 0 FOR 33000.0;
+		LEVEL 0 FOR 600.0;
+		LEVEL 1 FOR 320.0;
+		LEVEL 0 FOR 40.0;
+		LEVEL 1 FOR 320.0;
+		LEVEL 0 FOR 31720.0;
 	}
 }
 
@@ -1014,7 +1402,11 @@ TRANSITION_LIST("cpuAddr[19]")
 	NODE
 	{
 		REPEAT = 1;
-		LEVEL 0 FOR 33000.0;
+		LEVEL 0 FOR 600.0;
+		LEVEL 1 FOR 320.0;
+		LEVEL 0 FOR 40.0;
+		LEVEL 1 FOR 320.0;
+		LEVEL 0 FOR 31720.0;
 	}
 }
 
@@ -1023,7 +1415,11 @@ TRANSITION_LIST("cpuAddr[20]")
 	NODE
 	{
 		REPEAT = 1;
-		LEVEL 0 FOR 33000.0;
+		LEVEL 0 FOR 600.0;
+		LEVEL 1 FOR 320.0;
+		LEVEL 0 FOR 40.0;
+		LEVEL 1 FOR 320.0;
+		LEVEL 0 FOR 31720.0;
 	}
 }
 
@@ -1032,7 +1428,11 @@ TRANSITION_LIST("cpuAddr[21]")
 	NODE
 	{
 		REPEAT = 1;
-		LEVEL 0 FOR 33000.0;
+		LEVEL 0 FOR 600.0;
+		LEVEL 1 FOR 320.0;
+		LEVEL 0 FOR 40.0;
+		LEVEL 1 FOR 320.0;
+		LEVEL 0 FOR 31720.0;
 	}
 }
 
@@ -1059,7 +1459,12 @@ TRANSITION_LIST("cpuClk")
 	NODE
 	{
 		REPEAT = 1;
-		LEVEL 0 FOR 33000.0;
+		NODE
+		{
+			REPEAT = 264;
+			LEVEL 0 FOR 62.5;
+			LEVEL 1 FOR 62.5;
+		}
 	}
 }
 
@@ -1068,7 +1473,11 @@ TRANSITION_LIST("cpuData[15]")
 	NODE
 	{
 		REPEAT = 1;
-		LEVEL 0 FOR 33000.0;
+		LEVEL 0 FOR 600.0;
+		LEVEL 1 FOR 320.0;
+		LEVEL 0 FOR 40.0;
+		LEVEL 1 FOR 320.0;
+		LEVEL 0 FOR 31720.0;
 	}
 }
 
@@ -1077,7 +1486,9 @@ TRANSITION_LIST("cpuData[14]")
 	NODE
 	{
 		REPEAT = 1;
-		LEVEL 0 FOR 33000.0;
+		LEVEL 0 FOR 960.0;
+		LEVEL 1 FOR 320.0;
+		LEVEL 0 FOR 31720.0;
 	}
 }
 
@@ -1086,7 +1497,9 @@ TRANSITION_LIST("cpuData[13]")
 	NODE
 	{
 		REPEAT = 1;
-		LEVEL 0 FOR 33000.0;
+		LEVEL 0 FOR 600.0;
+		LEVEL 1 FOR 320.0;
+		LEVEL 0 FOR 32080.0;
 	}
 }
 
@@ -1113,7 +1526,9 @@ TRANSITION_LIST("cpuData[10]")
 	NODE
 	{
 		REPEAT = 1;
-		LEVEL 0 FOR 33000.0;
+		LEVEL 0 FOR 600.0;
+		LEVEL 1 FOR 320.0;
+		LEVEL 0 FOR 32080.0;
 	}
 }
 
@@ -1122,7 +1537,9 @@ TRANSITION_LIST("cpuData[9]")
 	NODE
 	{
 		REPEAT = 1;
-		LEVEL 0 FOR 33000.0;
+		LEVEL 0 FOR 960.0;
+		LEVEL 1 FOR 320.0;
+		LEVEL 0 FOR 31720.0;
 	}
 }
 
@@ -1131,7 +1548,11 @@ TRANSITION_LIST("cpuData[8]")
 	NODE
 	{
 		REPEAT = 1;
-		LEVEL 0 FOR 33000.0;
+		LEVEL 0 FOR 600.0;
+		LEVEL 1 FOR 320.0;
+		LEVEL 0 FOR 40.0;
+		LEVEL 1 FOR 320.0;
+		LEVEL 0 FOR 31720.0;
 	}
 }
 
@@ -1140,7 +1561,11 @@ TRANSITION_LIST("cpuData[7]")
 	NODE
 	{
 		REPEAT = 1;
-		LEVEL 0 FOR 33000.0;
+		LEVEL 0 FOR 600.0;
+		LEVEL 1 FOR 320.0;
+		LEVEL 0 FOR 40.0;
+		LEVEL 1 FOR 320.0;
+		LEVEL 0 FOR 31720.0;
 	}
 }
 
@@ -1149,7 +1574,9 @@ TRANSITION_LIST("cpuData[6]")
 	NODE
 	{
 		REPEAT = 1;
-		LEVEL 0 FOR 33000.0;
+		LEVEL 0 FOR 600.0;
+		LEVEL 1 FOR 320.0;
+		LEVEL 0 FOR 32080.0;
 	}
 }
 
@@ -1158,7 +1585,9 @@ TRANSITION_LIST("cpuData[5]")
 	NODE
 	{
 		REPEAT = 1;
-		LEVEL 0 FOR 33000.0;
+		LEVEL 0 FOR 600.0;
+		LEVEL 1 FOR 320.0;
+		LEVEL 0 FOR 32080.0;
 	}
 }
 
@@ -1167,7 +1596,9 @@ TRANSITION_LIST("cpuData[4]")
 	NODE
 	{
 		REPEAT = 1;
-		LEVEL 0 FOR 33000.0;
+		LEVEL 0 FOR 960.0;
+		LEVEL 1 FOR 320.0;
+		LEVEL 0 FOR 31720.0;
 	}
 }
 
@@ -1185,7 +1616,11 @@ TRANSITION_LIST("cpuData[2]")
 	NODE
 	{
 		REPEAT = 1;
-		LEVEL 0 FOR 33000.0;
+		LEVEL 0 FOR 600.0;
+		LEVEL 1 FOR 320.0;
+		LEVEL 0 FOR 40.0;
+		LEVEL 1 FOR 320.0;
+		LEVEL 0 FOR 31720.0;
 	}
 }
 
@@ -1194,7 +1629,11 @@ TRANSITION_LIST("cpuData[1]")
 	NODE
 	{
 		REPEAT = 1;
-		LEVEL 0 FOR 33000.0;
+		LEVEL 0 FOR 600.0;
+		LEVEL 1 FOR 320.0;
+		LEVEL 0 FOR 40.0;
+		LEVEL 1 FOR 320.0;
+		LEVEL 0 FOR 31720.0;
 	}
 }
 
@@ -1203,7 +1642,9 @@ TRANSITION_LIST("cpuData[0]")
 	NODE
 	{
 		REPEAT = 1;
-		LEVEL 0 FOR 33000.0;
+		LEVEL 0 FOR 600.0;
+		LEVEL 1 FOR 320.0;
+		LEVEL 0 FOR 32080.0;
 	}
 }
 
@@ -1212,7 +1653,11 @@ TRANSITION_LIST("cpuRnW")
 	NODE
 	{
 		REPEAT = 1;
-		LEVEL 0 FOR 33000.0;
+		LEVEL 1 FOR 600.0;
+		LEVEL 0 FOR 320.0;
+		LEVEL 1 FOR 40.0;
+		LEVEL 0 FOR 320.0;
+		LEVEL 1 FOR 31720.0;
 	}
 }
 
@@ -1232,7 +1677,11 @@ TRANSITION_LIST("ncpuAS")
 	NODE
 	{
 		REPEAT = 1;
-		LEVEL 0 FOR 33000.0;
+		LEVEL 1 FOR 610.0;
+		LEVEL 0 FOR 310.0;
+		LEVEL 1 FOR 60.0;
+		LEVEL 0 FOR 300.0;
+		LEVEL 1 FOR 31720.0;
 	}
 }
 
@@ -1241,7 +1690,11 @@ TRANSITION_LIST("ncpuLDS")
 	NODE
 	{
 		REPEAT = 1;
-		LEVEL 0 FOR 33000.0;
+		LEVEL 1 FOR 760.0;
+		LEVEL 0 FOR 160.0;
+		LEVEL 1 FOR 200.0;
+		LEVEL 0 FOR 160.0;
+		LEVEL 1 FOR 31720.0;
 	}
 }
 
@@ -1250,7 +1703,9 @@ TRANSITION_LIST("ncpuUDS")
 	NODE
 	{
 		REPEAT = 1;
-		LEVEL 0 FOR 33000.0;
+		LEVEL 1 FOR 760.0;
+		LEVEL 0 FOR 160.0;
+		LEVEL 1 FOR 32080.0;
 	}
 }
 
@@ -1309,7 +1764,7 @@ TRANSITION_LIST("ramSize[2]")
 	NODE
 	{
 		REPEAT = 1;
-		LEVEL 0 FOR 33000.0;
+		LEVEL 1 FOR 33000.0;
 	}
 }
 
@@ -1318,7 +1773,7 @@ TRANSITION_LIST("ramSize[1]")
 	NODE
 	{
 		REPEAT = 1;
-		LEVEL 0 FOR 33000.0;
+		LEVEL 1 FOR 33000.0;
 	}
 }
 
@@ -1327,7 +1782,7 @@ TRANSITION_LIST("ramSize[0]")
 	NODE
 	{
 		REPEAT = 1;
-		LEVEL 0 FOR 33000.0;
+		LEVEL 1 FOR 33000.0;
 	}
 }
 
@@ -1595,6 +2050,294 @@ TRANSITION_LIST("vramData[0]")
 	}
 }
 
+TRANSITION_LIST("cpusnoop:cpusnp|addrCache[13]")
+{
+	NODE
+	{
+		REPEAT = 1;
+		LEVEL U FOR 33000.0;
+	}
+}
+
+TRANSITION_LIST("cpusnoop:cpusnp|addrCache[12]")
+{
+	NODE
+	{
+		REPEAT = 1;
+		LEVEL U FOR 33000.0;
+	}
+}
+
+TRANSITION_LIST("cpusnoop:cpusnp|addrCache[11]")
+{
+	NODE
+	{
+		REPEAT = 1;
+		LEVEL U FOR 33000.0;
+	}
+}
+
+TRANSITION_LIST("cpusnoop:cpusnp|addrCache[10]")
+{
+	NODE
+	{
+		REPEAT = 1;
+		LEVEL U FOR 33000.0;
+	}
+}
+
+TRANSITION_LIST("cpusnoop:cpusnp|addrCache[9]")
+{
+	NODE
+	{
+		REPEAT = 1;
+		LEVEL U FOR 33000.0;
+	}
+}
+
+TRANSITION_LIST("cpusnoop:cpusnp|addrCache[8]")
+{
+	NODE
+	{
+		REPEAT = 1;
+		LEVEL U FOR 33000.0;
+	}
+}
+
+TRANSITION_LIST("cpusnoop:cpusnp|addrCache[7]")
+{
+	NODE
+	{
+		REPEAT = 1;
+		LEVEL U FOR 33000.0;
+	}
+}
+
+TRANSITION_LIST("cpusnoop:cpusnp|addrCache[6]")
+{
+	NODE
+	{
+		REPEAT = 1;
+		LEVEL U FOR 33000.0;
+	}
+}
+
+TRANSITION_LIST("cpusnoop:cpusnp|addrCache[5]")
+{
+	NODE
+	{
+		REPEAT = 1;
+		LEVEL U FOR 33000.0;
+	}
+}
+
+TRANSITION_LIST("cpusnoop:cpusnp|addrCache[4]")
+{
+	NODE
+	{
+		REPEAT = 1;
+		LEVEL U FOR 33000.0;
+	}
+}
+
+TRANSITION_LIST("cpusnoop:cpusnp|addrCache[3]")
+{
+	NODE
+	{
+		REPEAT = 1;
+		LEVEL U FOR 33000.0;
+	}
+}
+
+TRANSITION_LIST("cpusnoop:cpusnp|addrCache[2]")
+{
+	NODE
+	{
+		REPEAT = 1;
+		LEVEL U FOR 33000.0;
+	}
+}
+
+TRANSITION_LIST("cpusnoop:cpusnp|addrCache[1]")
+{
+	NODE
+	{
+		REPEAT = 1;
+		LEVEL U FOR 33000.0;
+	}
+}
+
+TRANSITION_LIST("cpusnoop:cpusnp|addrCache[0]")
+{
+	NODE
+	{
+		REPEAT = 1;
+		LEVEL U FOR 33000.0;
+	}
+}
+
+TRANSITION_LIST("cpusnoop:cpusnp|dataCacheHi[7]")
+{
+	NODE
+	{
+		REPEAT = 1;
+		LEVEL U FOR 33000.0;
+	}
+}
+
+TRANSITION_LIST("cpusnoop:cpusnp|dataCacheHi[6]")
+{
+	NODE
+	{
+		REPEAT = 1;
+		LEVEL U FOR 33000.0;
+	}
+}
+
+TRANSITION_LIST("cpusnoop:cpusnp|dataCacheHi[5]")
+{
+	NODE
+	{
+		REPEAT = 1;
+		LEVEL U FOR 33000.0;
+	}
+}
+
+TRANSITION_LIST("cpusnoop:cpusnp|dataCacheHi[4]")
+{
+	NODE
+	{
+		REPEAT = 1;
+		LEVEL U FOR 33000.0;
+	}
+}
+
+TRANSITION_LIST("cpusnoop:cpusnp|dataCacheHi[3]")
+{
+	NODE
+	{
+		REPEAT = 1;
+		LEVEL U FOR 33000.0;
+	}
+}
+
+TRANSITION_LIST("cpusnoop:cpusnp|dataCacheHi[2]")
+{
+	NODE
+	{
+		REPEAT = 1;
+		LEVEL U FOR 33000.0;
+	}
+}
+
+TRANSITION_LIST("cpusnoop:cpusnp|dataCacheHi[1]")
+{
+	NODE
+	{
+		REPEAT = 1;
+		LEVEL U FOR 33000.0;
+	}
+}
+
+TRANSITION_LIST("cpusnoop:cpusnp|dataCacheHi[0]")
+{
+	NODE
+	{
+		REPEAT = 1;
+		LEVEL U FOR 33000.0;
+	}
+}
+
+TRANSITION_LIST("cpusnoop:cpusnp|dataCacheLo[7]")
+{
+	NODE
+	{
+		REPEAT = 1;
+		LEVEL U FOR 33000.0;
+	}
+}
+
+TRANSITION_LIST("cpusnoop:cpusnp|dataCacheLo[6]")
+{
+	NODE
+	{
+		REPEAT = 1;
+		LEVEL U FOR 33000.0;
+	}
+}
+
+TRANSITION_LIST("cpusnoop:cpusnp|dataCacheLo[5]")
+{
+	NODE
+	{
+		REPEAT = 1;
+		LEVEL U FOR 33000.0;
+	}
+}
+
+TRANSITION_LIST("cpusnoop:cpusnp|dataCacheLo[4]")
+{
+	NODE
+	{
+		REPEAT = 1;
+		LEVEL U FOR 33000.0;
+	}
+}
+
+TRANSITION_LIST("cpusnoop:cpusnp|dataCacheLo[3]")
+{
+	NODE
+	{
+		REPEAT = 1;
+		LEVEL U FOR 33000.0;
+	}
+}
+
+TRANSITION_LIST("cpusnoop:cpusnp|dataCacheLo[2]")
+{
+	NODE
+	{
+		REPEAT = 1;
+		LEVEL U FOR 33000.0;
+	}
+}
+
+TRANSITION_LIST("cpusnoop:cpusnp|dataCacheLo[1]")
+{
+	NODE
+	{
+		REPEAT = 1;
+		LEVEL U FOR 33000.0;
+	}
+}
+
+TRANSITION_LIST("cpusnoop:cpusnp|dataCacheLo[0]")
+{
+	NODE
+	{
+		REPEAT = 1;
+		LEVEL U FOR 33000.0;
+	}
+}
+
+TRANSITION_LIST("cpusnoop:cpusnp|pendWriteHi")
+{
+	NODE
+	{
+		REPEAT = 1;
+		LEVEL U FOR 33000.0;
+	}
+}
+
+TRANSITION_LIST("cpusnoop:cpusnp|pendWriteLo")
+{
+	NODE
+	{
+		REPEAT = 1;
+		LEVEL U FOR 33000.0;
+	}
+}
+
 DISPLAY_LINE
 {
 	CHANNEL = "cpuAddr";
@@ -1607,7 +2350,7 @@ DISPLAY_LINE
 
 DISPLAY_LINE
 {
-	CHANNEL = "cpuAddr[1]";
+	CHANNEL = "cpuAddr[23]";
 	EXPAND_STATUS = COLLAPSED;
 	RADIX = Hexadecimal;
 	TREE_INDEX = 1;
@@ -1617,7 +2360,7 @@ DISPLAY_LINE
 
 DISPLAY_LINE
 {
-	CHANNEL = "cpuAddr[2]";
+	CHANNEL = "cpuAddr[22]";
 	EXPAND_STATUS = COLLAPSED;
 	RADIX = Hexadecimal;
 	TREE_INDEX = 2;
@@ -1627,7 +2370,7 @@ DISPLAY_LINE
 
 DISPLAY_LINE
 {
-	CHANNEL = "cpuAddr[3]";
+	CHANNEL = "cpuAddr[21]";
 	EXPAND_STATUS = COLLAPSED;
 	RADIX = Hexadecimal;
 	TREE_INDEX = 3;
@@ -1637,7 +2380,7 @@ DISPLAY_LINE
 
 DISPLAY_LINE
 {
-	CHANNEL = "cpuAddr[4]";
+	CHANNEL = "cpuAddr[20]";
 	EXPAND_STATUS = COLLAPSED;
 	RADIX = Hexadecimal;
 	TREE_INDEX = 4;
@@ -1647,7 +2390,7 @@ DISPLAY_LINE
 
 DISPLAY_LINE
 {
-	CHANNEL = "cpuAddr[5]";
+	CHANNEL = "cpuAddr[19]";
 	EXPAND_STATUS = COLLAPSED;
 	RADIX = Hexadecimal;
 	TREE_INDEX = 5;
@@ -1657,7 +2400,7 @@ DISPLAY_LINE
 
 DISPLAY_LINE
 {
-	CHANNEL = "cpuAddr[6]";
+	CHANNEL = "cpuAddr[18]";
 	EXPAND_STATUS = COLLAPSED;
 	RADIX = Hexadecimal;
 	TREE_INDEX = 6;
@@ -1667,7 +2410,7 @@ DISPLAY_LINE
 
 DISPLAY_LINE
 {
-	CHANNEL = "cpuAddr[7]";
+	CHANNEL = "cpuAddr[17]";
 	EXPAND_STATUS = COLLAPSED;
 	RADIX = Hexadecimal;
 	TREE_INDEX = 7;
@@ -1677,7 +2420,7 @@ DISPLAY_LINE
 
 DISPLAY_LINE
 {
-	CHANNEL = "cpuAddr[8]";
+	CHANNEL = "cpuAddr[16]";
 	EXPAND_STATUS = COLLAPSED;
 	RADIX = Hexadecimal;
 	TREE_INDEX = 8;
@@ -1687,7 +2430,7 @@ DISPLAY_LINE
 
 DISPLAY_LINE
 {
-	CHANNEL = "cpuAddr[9]";
+	CHANNEL = "cpuAddr[15]";
 	EXPAND_STATUS = COLLAPSED;
 	RADIX = Hexadecimal;
 	TREE_INDEX = 9;
@@ -1697,7 +2440,7 @@ DISPLAY_LINE
 
 DISPLAY_LINE
 {
-	CHANNEL = "cpuAddr[10]";
+	CHANNEL = "cpuAddr[14]";
 	EXPAND_STATUS = COLLAPSED;
 	RADIX = Hexadecimal;
 	TREE_INDEX = 10;
@@ -1707,7 +2450,7 @@ DISPLAY_LINE
 
 DISPLAY_LINE
 {
-	CHANNEL = "cpuAddr[11]";
+	CHANNEL = "cpuAddr[13]";
 	EXPAND_STATUS = COLLAPSED;
 	RADIX = Hexadecimal;
 	TREE_INDEX = 11;
@@ -1727,7 +2470,7 @@ DISPLAY_LINE
 
 DISPLAY_LINE
 {
-	CHANNEL = "cpuAddr[13]";
+	CHANNEL = "cpuAddr[11]";
 	EXPAND_STATUS = COLLAPSED;
 	RADIX = Hexadecimal;
 	TREE_INDEX = 13;
@@ -1737,7 +2480,7 @@ DISPLAY_LINE
 
 DISPLAY_LINE
 {
-	CHANNEL = "cpuAddr[14]";
+	CHANNEL = "cpuAddr[10]";
 	EXPAND_STATUS = COLLAPSED;
 	RADIX = Hexadecimal;
 	TREE_INDEX = 14;
@@ -1747,7 +2490,7 @@ DISPLAY_LINE
 
 DISPLAY_LINE
 {
-	CHANNEL = "cpuAddr[15]";
+	CHANNEL = "cpuAddr[9]";
 	EXPAND_STATUS = COLLAPSED;
 	RADIX = Hexadecimal;
 	TREE_INDEX = 15;
@@ -1757,7 +2500,7 @@ DISPLAY_LINE
 
 DISPLAY_LINE
 {
-	CHANNEL = "cpuAddr[16]";
+	CHANNEL = "cpuAddr[8]";
 	EXPAND_STATUS = COLLAPSED;
 	RADIX = Hexadecimal;
 	TREE_INDEX = 16;
@@ -1767,7 +2510,7 @@ DISPLAY_LINE
 
 DISPLAY_LINE
 {
-	CHANNEL = "cpuAddr[17]";
+	CHANNEL = "cpuAddr[7]";
 	EXPAND_STATUS = COLLAPSED;
 	RADIX = Hexadecimal;
 	TREE_INDEX = 17;
@@ -1777,7 +2520,7 @@ DISPLAY_LINE
 
 DISPLAY_LINE
 {
-	CHANNEL = "cpuAddr[18]";
+	CHANNEL = "cpuAddr[6]";
 	EXPAND_STATUS = COLLAPSED;
 	RADIX = Hexadecimal;
 	TREE_INDEX = 18;
@@ -1787,7 +2530,7 @@ DISPLAY_LINE
 
 DISPLAY_LINE
 {
-	CHANNEL = "cpuAddr[19]";
+	CHANNEL = "cpuAddr[5]";
 	EXPAND_STATUS = COLLAPSED;
 	RADIX = Hexadecimal;
 	TREE_INDEX = 19;
@@ -1797,7 +2540,7 @@ DISPLAY_LINE
 
 DISPLAY_LINE
 {
-	CHANNEL = "cpuAddr[20]";
+	CHANNEL = "cpuAddr[4]";
 	EXPAND_STATUS = COLLAPSED;
 	RADIX = Hexadecimal;
 	TREE_INDEX = 20;
@@ -1807,7 +2550,7 @@ DISPLAY_LINE
 
 DISPLAY_LINE
 {
-	CHANNEL = "cpuAddr[21]";
+	CHANNEL = "cpuAddr[3]";
 	EXPAND_STATUS = COLLAPSED;
 	RADIX = Hexadecimal;
 	TREE_INDEX = 21;
@@ -1817,7 +2560,7 @@ DISPLAY_LINE
 
 DISPLAY_LINE
 {
-	CHANNEL = "cpuAddr[22]";
+	CHANNEL = "cpuAddr[2]";
 	EXPAND_STATUS = COLLAPSED;
 	RADIX = Hexadecimal;
 	TREE_INDEX = 22;
@@ -1827,7 +2570,7 @@ DISPLAY_LINE
 
 DISPLAY_LINE
 {
-	CHANNEL = "cpuAddr[23]";
+	CHANNEL = "cpuAddr[1]";
 	EXPAND_STATUS = COLLAPSED;
 	RADIX = Hexadecimal;
 	TREE_INDEX = 23;
@@ -2403,6 +3146,354 @@ DISPLAY_LINE
 	PARENT = 73;
 }
 
+DISPLAY_LINE
+{
+	CHANNEL = "cpusnoop:cpusnp|addrCache";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Hexadecimal;
+	TREE_INDEX = 82;
+	TREE_LEVEL = 0;
+	CHILDREN = 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "cpusnoop:cpusnp|addrCache[13]";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Hexadecimal;
+	TREE_INDEX = 83;
+	TREE_LEVEL = 1;
+	PARENT = 82;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "cpusnoop:cpusnp|addrCache[12]";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Hexadecimal;
+	TREE_INDEX = 84;
+	TREE_LEVEL = 1;
+	PARENT = 82;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "cpusnoop:cpusnp|addrCache[11]";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Hexadecimal;
+	TREE_INDEX = 85;
+	TREE_LEVEL = 1;
+	PARENT = 82;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "cpusnoop:cpusnp|addrCache[10]";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Hexadecimal;
+	TREE_INDEX = 86;
+	TREE_LEVEL = 1;
+	PARENT = 82;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "cpusnoop:cpusnp|addrCache[9]";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Hexadecimal;
+	TREE_INDEX = 87;
+	TREE_LEVEL = 1;
+	PARENT = 82;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "cpusnoop:cpusnp|addrCache[8]";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Hexadecimal;
+	TREE_INDEX = 88;
+	TREE_LEVEL = 1;
+	PARENT = 82;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "cpusnoop:cpusnp|addrCache[7]";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Hexadecimal;
+	TREE_INDEX = 89;
+	TREE_LEVEL = 1;
+	PARENT = 82;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "cpusnoop:cpusnp|addrCache[6]";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Hexadecimal;
+	TREE_INDEX = 90;
+	TREE_LEVEL = 1;
+	PARENT = 82;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "cpusnoop:cpusnp|addrCache[5]";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Hexadecimal;
+	TREE_INDEX = 91;
+	TREE_LEVEL = 1;
+	PARENT = 82;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "cpusnoop:cpusnp|addrCache[4]";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Hexadecimal;
+	TREE_INDEX = 92;
+	TREE_LEVEL = 1;
+	PARENT = 82;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "cpusnoop:cpusnp|addrCache[3]";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Hexadecimal;
+	TREE_INDEX = 93;
+	TREE_LEVEL = 1;
+	PARENT = 82;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "cpusnoop:cpusnp|addrCache[2]";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Hexadecimal;
+	TREE_INDEX = 94;
+	TREE_LEVEL = 1;
+	PARENT = 82;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "cpusnoop:cpusnp|addrCache[1]";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Hexadecimal;
+	TREE_INDEX = 95;
+	TREE_LEVEL = 1;
+	PARENT = 82;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "cpusnoop:cpusnp|addrCache[0]";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Hexadecimal;
+	TREE_INDEX = 96;
+	TREE_LEVEL = 1;
+	PARENT = 82;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "cpusnoop:cpusnp|dataCacheHi";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Hexadecimal;
+	TREE_INDEX = 97;
+	TREE_LEVEL = 0;
+	CHILDREN = 98, 99, 100, 101, 102, 103, 104, 105;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "cpusnoop:cpusnp|dataCacheHi[7]";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Hexadecimal;
+	TREE_INDEX = 98;
+	TREE_LEVEL = 1;
+	PARENT = 97;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "cpusnoop:cpusnp|dataCacheHi[6]";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Hexadecimal;
+	TREE_INDEX = 99;
+	TREE_LEVEL = 1;
+	PARENT = 97;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "cpusnoop:cpusnp|dataCacheHi[5]";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Hexadecimal;
+	TREE_INDEX = 100;
+	TREE_LEVEL = 1;
+	PARENT = 97;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "cpusnoop:cpusnp|dataCacheHi[4]";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Hexadecimal;
+	TREE_INDEX = 101;
+	TREE_LEVEL = 1;
+	PARENT = 97;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "cpusnoop:cpusnp|dataCacheHi[3]";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Hexadecimal;
+	TREE_INDEX = 102;
+	TREE_LEVEL = 1;
+	PARENT = 97;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "cpusnoop:cpusnp|dataCacheHi[2]";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Hexadecimal;
+	TREE_INDEX = 103;
+	TREE_LEVEL = 1;
+	PARENT = 97;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "cpusnoop:cpusnp|dataCacheHi[1]";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Hexadecimal;
+	TREE_INDEX = 104;
+	TREE_LEVEL = 1;
+	PARENT = 97;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "cpusnoop:cpusnp|dataCacheHi[0]";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Hexadecimal;
+	TREE_INDEX = 105;
+	TREE_LEVEL = 1;
+	PARENT = 97;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "cpusnoop:cpusnp|dataCacheLo";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Hexadecimal;
+	TREE_INDEX = 106;
+	TREE_LEVEL = 0;
+	CHILDREN = 107, 108, 109, 110, 111, 112, 113, 114;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "cpusnoop:cpusnp|dataCacheLo[7]";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Hexadecimal;
+	TREE_INDEX = 107;
+	TREE_LEVEL = 1;
+	PARENT = 106;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "cpusnoop:cpusnp|dataCacheLo[6]";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Hexadecimal;
+	TREE_INDEX = 108;
+	TREE_LEVEL = 1;
+	PARENT = 106;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "cpusnoop:cpusnp|dataCacheLo[5]";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Hexadecimal;
+	TREE_INDEX = 109;
+	TREE_LEVEL = 1;
+	PARENT = 106;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "cpusnoop:cpusnp|dataCacheLo[4]";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Hexadecimal;
+	TREE_INDEX = 110;
+	TREE_LEVEL = 1;
+	PARENT = 106;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "cpusnoop:cpusnp|dataCacheLo[3]";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Hexadecimal;
+	TREE_INDEX = 111;
+	TREE_LEVEL = 1;
+	PARENT = 106;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "cpusnoop:cpusnp|dataCacheLo[2]";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Hexadecimal;
+	TREE_INDEX = 112;
+	TREE_LEVEL = 1;
+	PARENT = 106;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "cpusnoop:cpusnp|dataCacheLo[1]";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Hexadecimal;
+	TREE_INDEX = 113;
+	TREE_LEVEL = 1;
+	PARENT = 106;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "cpusnoop:cpusnp|dataCacheLo[0]";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Hexadecimal;
+	TREE_INDEX = 114;
+	TREE_LEVEL = 1;
+	PARENT = 106;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "cpusnoop:cpusnp|pendWriteHi";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Binary;
+	TREE_INDEX = 115;
+	TREE_LEVEL = 0;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "cpusnoop:cpusnp|pendWriteLo";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Binary;
+	TREE_INDEX = 116;
+	TREE_LEVEL = 0;
+}
+
 TIME_BAR
 {
 	TIME = 0;
diff --git a/vgaout.sv b/vgaout.sv
index a28efe0..644fee5 100644
--- a/vgaout.sv
+++ b/vgaout.sv
@@ -22,7 +22,7 @@ module vgaout (
     output wire         vidOut
 );
 
-reg [7:0] rVid;
+//reg [7:0] rVid;
 wire vidMuxOut;
 wire vidActive; // combined active video signal
 
@@ -66,7 +66,7 @@ end
 */
 
 // latch incoming vram data on rising clock and sequence 7
-always @(posedge pixClock or negedge nReset) begin
+/*always @(posedge pixClock or negedge nReset) begin
     if(nReset == 1'b0) begin
         rVid <= 8'h0;
     end else begin
@@ -74,7 +74,7 @@ always @(posedge pixClock or negedge nReset) begin
             rVid <= vramData;
         end
     end
-end
+end*/
 
 always_comb begin
     // combined video active signal