From 89040b43b40b72687f2a6e2387f147718f0dbe25 Mon Sep 17 00:00:00 2001 From: techav <76832805+techav-homebrew@users.noreply.github.com> Date: Sun, 11 Apr 2021 23:46:29 -0500 Subject: [PATCH] First compile --- cpusnoop.sv | 83 +- primitives/primitives.sv | 39 +- se-vga.sv | 42 +- sevga.vwf | 2411 ++++++++++++++++++++++++++++++++++++++ vgacount.sv | 27 +- vgagen.sv | 7 +- vgaout.sv | 12 +- 7 files changed, 2551 insertions(+), 70 deletions(-) create mode 100644 sevga.vwf diff --git a/cpusnoop.sv b/cpusnoop.sv index e1181c7..89bde9b 100644 --- a/cpusnoop.sv +++ b/cpusnoop.sv @@ -11,34 +11,75 @@ module cpusnoop ( input wire nReset, // System Reset signal input wire pixClock, // 25.175MHz Pixel Clock - input logic [2:0] sequence, // Sequence count (low 3 bits of hCount) - input logic [23:1] cpuAddr, // CPU Address bus + input logic [2:0] seq, // Sequence count (low 3 bits of hCount) + input logic [22:0] cpuAddr, // CPU Address bus input logic [15:0] cpuData, // CPU Data bus input wire ncpuAS, // CPU Address Strobe signal input wire ncpuUDS, // CPU Upper Data Strobe signal input wire ncpuLDS, // CPU Lower Data Strobe signal input wire cpuRnW, // CPU Read/Write select signal input wire cpuClk, // CPU Clock - output logic [12:0] vramAddr, // VRAM Address Bus - inout logic [7:0] vramData, // VRAM Data Bus + output logic [14:0] vramAddr, // VRAM Address Bus + output logic [7:0] vramDataOut,// VRAM Data Bus Output output wire nvramWE, // VRAM Write strobe + input logic [2:0] ramSize // CPU RAM size selection ); - // framebuffer address (with 4MB RAM installed): 0x3FA700 - 0x3FFFFF + /* framebuffer starts $5900 below the top of RAM + * ramSize is used to mask the cpuAddr bits [21:9] to select the amount + * of memory installed in the computer. Not all possible ramSize selections + * are valid memory sizes when using 30-pin SIMMs in the Mac SE. + * They may be possible using PDS RAM expansion cards. + * ramSize bufferStart ramTop+1 ramSize Valid? Installed SIMMs + * $7 $3fa700 $400000 4.0MB Y [ 1MB 1MB ][ 1MB 1MB ] + * $6 $37a700 $380000 3.5MB N + * $5 $2fa700 $300000 3.0MB N + * $4 $27a700 $280000 2.5MB Y [ 1MB 1MB ][256kB 256kB] + * $3 $1fa700 $200000 2.0MB Y [ 1MB 1MB ][ --- --- ] + * $2 $17a700 $180000 1.5MB N + * $1 $0fa700 $100000 1.0MB Y [256kB 256kB][256kB 256kB] + * $0 $07a700 $080000 0.5MB Y [256kB 256kB][ --- --- ] + */ wire pendWriteLo; // low byte write to VRAM pending wire pendWriteHi; // high byte write to VRAM pending - logic [12:1] addrCache; // store address for cpu writes to framebuffer + logic [13:0] addrCache; // store address for cpu writes to framebuffer logic [7:0] dataCacheLo; // store data for cpu writes to low byte logic [7:0] dataCacheHi; // store data for cpu writes to high byte + wire cpuBufSel; // is CPU accessing frame buffer? + + // when cpu addresses the framebuffer, set our enable signal + always_comb begin + if(ramSize == cpuAddr[20:18] && cpuAddr[22:21] == 2'b00 && cpuAddr[17:14] == 4'b1111) begin + cpuBufSel <= 1'b1; + end else begin + cpuBufSel <= 1'b0; + end + end // when cpu addresses the framebuffer, save the address always @(negedge ncpuAS or negedge nReset) begin if(nReset == 1'b0) begin - addrCache <= 16'h0; + addrCache <= 0; end else begin - if(cpuAddr >= 24'h3FA700 && cpuAddr < 24'h400000) begin - addrCache[12:0] <= cpuAddr - 16'hA700; + // here we match our ramSize jumpers and constants to confirm + // the CPU is accessing the primary frame buffer + if(cpuBufSel == 1'b1) begin + // We have a match, so subtract constant $1380 from the + // cpu address and store the result in addrCache register. + // Constant $1380 corresponds to $2700 shifted right by 1. + // Once the selection bits above are masked out, we're left + // with buffer addresses starting with $2700 + // e.g. with 4MB of RAM, fram buffer starts at $3FA700 + // buffer address: 0011 1111 1010 0111 0000 0000 = $3FA700 + // vram addr mask: 0000 0000 0011 1111 1111 1111 - $003FFF + // vram address: 0000 0000 0010 0111 0000 0000 = $002700 + // Since CPU is 16-bit and does not provide A0, our cpuAddr + // signals are shifted right by one, so we need to do the same + // to our offset before subtracting it from cpuAddr + // offset: 0000 0000 0010 0111 0000 0000 = $002700 + // shifted offset: 0000 0000 0001 0011 1000 0000 = $001380 + addrCache <= cpuAddr[13:0] - 14'h1380; end end end @@ -48,18 +89,18 @@ module cpusnoop ( if(nReset == 1'b0) begin dataCacheHi <= 8'h0; end else begin - if(cpuAddr >= 24'h3FA700 && cpuAddr < 24'h400000 && cpuRnW == 1'b0) begin + if(cpuBufSel == 1'b1 && cpuRnW == 1'b0) begin dataCacheHi <= cpuData[15:8]; end end end // when cpu addresses the framebuffer, save low byte - always @(negedge ncpuUDS or negedge nReset) begin + always @(negedge ncpuLDS or negedge nReset) begin if(nReset == 1'b0) begin dataCacheLo <= 8'h0; end else begin - if(cpuAddr >= 24'h3FA700 && cpuAddr < 24'h400000 && cpuRnW == 1'b0) begin + if(cpuBufSel == 1'b1 && cpuRnW == 1'b0) begin dataCacheLo <= cpuData[7:0]; end end @@ -71,7 +112,7 @@ module cpusnoop ( pendWriteLo <= 1'b0; pendWriteHi <= 1'b0; end else begin - if(cpuAddr >= 24'h3FA700 && cpuAddr < 24'h400000 && cpuRnW == 1'b0) begin + if(cpuBufSel == 1'b1 && cpuRnW == 1'b0) begin if(ncpuUDS == 1'b0) begin pendWriteHi <= 1'b1; end @@ -79,10 +120,10 @@ module cpusnoop ( pendWriteLo <= 1'b1; end end else begin - if(sequence == 3'h1) begin + if(seq == 3'h1) begin pendWriteLo <= 1'b0; end - if(sequence == 3'h2) begin + if(seq == 3'h2) begin pendWriteHi <= 1'b0; end end @@ -90,19 +131,19 @@ module cpusnoop ( end always_comb begin - vramAddr[12:1] <= addrCache[12:1]; - if(pendWriteLo == 1'b1 && sequence == 3'h1) begin + vramAddr[14:1] <= addrCache[13:0]; + if(pendWriteLo == 1'b1 && seq == 3'h1) begin vramAddr[0] <= 1'b0; nvramWE <= 1'b0; - vramData <= dataCacheLo; - end else if(pendWriteHi == 1'b1 && sequence = 3'h2) begin + vramDataOut <= dataCacheLo; + end else if(pendWriteHi == 1'b1 && seq == 3'h2) begin vramAddr[0] <= 1'b1; nvramWE <= 1'b0; - vramData <= dataCacheHi; + vramDataOut <= dataCacheHi; end else begin vramAddr[0] <= 1'b0; nvramWE <= 1'b1; - vramData <= 8'bZ; + vramDataOut <= 8'h0; end end endmodule \ No newline at end of file diff --git a/primitives/primitives.sv b/primitives/primitives.sv index 769dc5d..e55b3d1 100644 --- a/primitives/primitives.sv +++ b/primitives/primitives.sv @@ -7,14 +7,17 @@ * Basic modules to be used elsewhere *****************************************************************************/ +`ifndef PRIMS + `define PRIMS + // basic d-flipflop -module dff ( +module myDff ( input wire nReset, input wire clk, input wire d, output reg q ); - always @(posedge clock or negedge nReset) begin + always @(posedge clk or negedge nReset) begin if(nReset == 1'b0) begin q <= 1'b0; end else begin @@ -45,7 +48,7 @@ module mux8x1 ( input logic[2:0] select, output wire out ); - assign out <= in[select]; + assign out = in[select]; endmodule // basic 8-to-1 mux with transparent output latch @@ -62,11 +65,13 @@ module mux8x1latch ( // transparent latch -- when clock is low, output will // follow the output of the mux. When clock is high, // output will hold its last value. - always @(clock or nReset or muxOut) begin + always @(clock or nReset or muxOut or out) begin if(nReset == 1'b0) begin - out <= 1'b0; + out = 1'b0; end else if(clock == 1'b0) begin - out <= muxOut; + out = muxOut; + end else begin + out = out; end end endmodule @@ -84,14 +89,16 @@ module piso8 ( logic [7:0] muxOuts; mux8 loader(muxIns[7:0],parIn[7:0],load,muxOuts[7:0]); - dff u0(nReset,clk,muxOuts[0],muxIns[1]); - dff u1(nReset,clk,muxOuts[1],muxIns[2]); - dff u2(nReset,clk,muxOuts[2],muxIns[3]); - dff u3(nReset,clk,muxOuts[3],muxIns[4]); - dff u4(nReset,clk,muxOuts[4],muxIns[5]); - dff u5(nReset,clk,muxOuts[5],muxIns[6]); - dff u6(nReset,clk,muxOuts[6],muxIns[7]); - dff u7(nReset,clk,muxOuts[7],muxIns[0]); + myDff u0(nReset,clk,muxOuts[0],muxIns[1]); + myDff u1(nReset,clk,muxOuts[1],muxIns[2]); + myDff u2(nReset,clk,muxOuts[2],muxIns[3]); + myDff u3(nReset,clk,muxOuts[3],muxIns[4]); + myDff u4(nReset,clk,muxOuts[4],muxIns[5]); + myDff u5(nReset,clk,muxOuts[5],muxIns[6]); + myDff u6(nReset,clk,muxOuts[6],muxIns[7]); + myDff u7(nReset,clk,muxOuts[7],muxIns[0]); - out <= muxIns[0]; -endmodule \ No newline at end of file + assign out = muxIns[0]; +endmodule + +`endif \ No newline at end of file diff --git a/se-vga.sv b/se-vga.sv index 2d87f51..4aa307b 100644 --- a/se-vga.sv +++ b/se-vga.sv @@ -7,14 +7,14 @@ * Pulls together all the smaller modules to form the SE-VGA adapter *****************************************************************************/ -module design sevga ( +module sevga ( input wire nReset, // System reset signal input wire pixClk, // 25.175MHz pixel clock output wire nhSync, // HSync signal output wire nvSync, // VSync signal output wire vidOut, // 1-bit Monochrome video signal - output logic [12:0] vramAddr, // VRAM Address bus + output logic [14:0] vramAddr, // VRAM Address bus inout logic [7:0] vramData, // VRAM Data bus output wire nvramOE, // VRAM Read strobe output wire nvramWE, // VRAM Write strobe @@ -25,19 +25,21 @@ module design sevga ( input wire ncpuUDS, // CPU Upper Data Strobe signal input wire ncpuLDS, // CPU Lower Data Strobe signal input wire cpuRnW, // CPU Read/Write select signal - input wire cpuClk // CPU Clock + //input wire cpuClk, // CPU Clock (probably not needed) + input logic [2:0] ramSize // Select installed RAM size ); logic [9:0] hCount; logic [9:0] vCount; wire hActive; wire hSEActive; +wire vActive; +wire vSEActive; -//logic [7:0] vidVramData; -logic [12:0] vidVramAddr; -//logic [7:0] cpuVramData; -logic [12:0] cpuVramAddr; - +logic [14:0] vidVramAddr; +logic [14:0] cpuVramAddr; +logic [7:0] vidVramData; +wire [7:0] cpuVramData; // link module that generates all our timing signals vgagen vgatiming( @@ -61,7 +63,7 @@ vgaout vidvram( .vCount(vCount), .hSEActive(hSEActive), .vSEActive(vSEActive), - .vramData(vramData), + .vramData(vidVramData), .vramAddr(vidVramAddr), .nvramOE(nvramOE), .vidOut(vidOut) @@ -71,7 +73,7 @@ vgaout vidvram( cpusnoop cpusnp( .nReset(nReset), .pixClock(pixClk), - .sequence(hCount[2:0]), + .seq(hCount[2:0]), .cpuAddr(cpuAddr), .cpuData(cpuData), .ncpuAS(ncpuAS), @@ -79,18 +81,28 @@ cpusnoop cpusnp( .ncpuLDS(ncpuLDS), .cpuRnW(cpuRnW), .cpuClk(cpuClk), - .vramAddr(vramAddr), - .vramData(cpuVramData), - .nvramWE(nvramWE) + .vramAddr(cpuVramAddr), + .vramDataOut(cpuVramData), + .nvramWE(nvramWE), + .ramSize(ramSize) ); always_comb begin // vramAddr muxing - if(.nvramWE == 1'b0) begin + if(nvramWE == 1'b0) begin vramAddr <= cpuVramAddr; end else begin - vramAddr <= vidVramData; + vramAddr <= vidVramAddr; end end +always_comb begin + if(nvramWE == 1'b0) begin + vramData <= cpuVramData; + end else begin + vramData <= 8'bZZZZZZZZ; + end + vidVramData <= vramData; +end + endmodule \ No newline at end of file diff --git a/sevga.vwf b/sevga.vwf new file mode 100644 index 0000000..8901c80 --- /dev/null +++ b/sevga.vwf @@ -0,0 +1,2411 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ + +/* +Copyright (C) 1991-2013 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ + +HEADER +{ + VERSION = 1; + TIME_UNIT = ns; + DATA_OFFSET = 0.0; + DATA_DURATION = 33000.0; + SIMULATION_TIME = 0.0; + GRID_PHASE = 0.0; + GRID_PERIOD = 10.0; + GRID_DUTY_CYCLE = 50; +} + +SIGNAL("cpuAddr[1]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("cpuAddr[2]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("cpuAddr[3]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("cpuAddr[4]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("cpuAddr[5]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("cpuAddr[6]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("cpuAddr[7]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("cpuAddr[8]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("cpuAddr[9]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("cpuAddr[10]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("cpuAddr[11]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("cpuAddr[12]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("cpuAddr[13]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("cpuAddr[14]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("cpuAddr[15]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("cpuAddr[16]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("cpuAddr[17]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("cpuAddr[18]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("cpuAddr[19]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("cpuAddr[20]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("cpuAddr[21]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("cpuAddr[22]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("cpuAddr[23]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("cpuClk") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("cpuData") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = BUS; + WIDTH = 16; + LSB_INDEX = 0; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("cpuData[15]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "cpuData"; +} + +SIGNAL("cpuData[14]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "cpuData"; +} + +SIGNAL("cpuData[13]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "cpuData"; +} + +SIGNAL("cpuData[12]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "cpuData"; +} + +SIGNAL("cpuData[11]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "cpuData"; +} + +SIGNAL("cpuData[10]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "cpuData"; +} + +SIGNAL("cpuData[9]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "cpuData"; +} + +SIGNAL("cpuData[8]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "cpuData"; +} + +SIGNAL("cpuData[7]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "cpuData"; +} + +SIGNAL("cpuData[6]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "cpuData"; +} + +SIGNAL("cpuData[5]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "cpuData"; +} + +SIGNAL("cpuData[4]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "cpuData"; +} + +SIGNAL("cpuData[3]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "cpuData"; +} + +SIGNAL("cpuData[2]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "cpuData"; +} + +SIGNAL("cpuData[1]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "cpuData"; +} + +SIGNAL("cpuData[0]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "cpuData"; +} + +SIGNAL("cpuRnW") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("nReset") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("ncpuAS") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("ncpuLDS") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("ncpuUDS") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("nhSync") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("nvSync") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("nvramOE") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("nvramWE") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("pixClk") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("ramSize") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = BUS; + WIDTH = 3; + LSB_INDEX = 0; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("ramSize[2]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "ramSize"; +} + +SIGNAL("ramSize[1]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "ramSize"; +} + +SIGNAL("ramSize[0]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "ramSize"; +} + +SIGNAL("vidOut") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("vramAddr") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = BUS; + WIDTH = 15; + LSB_INDEX = 0; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("vramAddr[14]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "vramAddr"; +} + +SIGNAL("vramAddr[13]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "vramAddr"; +} + +SIGNAL("vramAddr[12]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "vramAddr"; +} + +SIGNAL("vramAddr[11]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "vramAddr"; +} + +SIGNAL("vramAddr[10]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "vramAddr"; +} + +SIGNAL("vramAddr[9]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "vramAddr"; +} + +SIGNAL("vramAddr[8]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "vramAddr"; +} + +SIGNAL("vramAddr[7]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "vramAddr"; +} + +SIGNAL("vramAddr[6]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "vramAddr"; +} + +SIGNAL("vramAddr[5]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "vramAddr"; +} + +SIGNAL("vramAddr[4]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "vramAddr"; +} + +SIGNAL("vramAddr[3]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "vramAddr"; +} + +SIGNAL("vramAddr[2]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "vramAddr"; +} + +SIGNAL("vramAddr[1]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "vramAddr"; +} + +SIGNAL("vramAddr[0]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "vramAddr"; +} + +SIGNAL("vramData") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = BUS; + WIDTH = 8; + LSB_INDEX = 0; + DIRECTION = BIDIR; + PARENT = ""; +} + +SIGNAL("vramData[7]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = BIDIR; + PARENT = "vramData"; +} + +SIGNAL("vramData[6]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = BIDIR; + PARENT = "vramData"; +} + +SIGNAL("vramData[5]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = BIDIR; + PARENT = "vramData"; +} + +SIGNAL("vramData[4]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = BIDIR; + PARENT = "vramData"; +} + +SIGNAL("vramData[3]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = BIDIR; + PARENT = "vramData"; +} + +SIGNAL("vramData[2]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = BIDIR; + PARENT = "vramData"; +} + +SIGNAL("vramData[1]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = BIDIR; + PARENT = "vramData"; +} + +SIGNAL("vramData[0]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = BIDIR; + PARENT = "vramData"; +} + +GROUP("cpuAddr") +{ + MEMBERS = "cpuAddr[1]", "cpuAddr[2]", "cpuAddr[3]", "cpuAddr[4]", "cpuAddr[5]", "cpuAddr[6]", "cpuAddr[7]", "cpuAddr[8]", "cpuAddr[9]", "cpuAddr[10]", "cpuAddr[11]", "cpuAddr[12]", "cpuAddr[13]", "cpuAddr[14]", "cpuAddr[15]", "cpuAddr[16]", "cpuAddr[17]", "cpuAddr[18]", "cpuAddr[19]", "cpuAddr[20]", "cpuAddr[21]", "cpuAddr[22]", "cpuAddr[23]"; +} + +TRANSITION_LIST("cpuAddr[1]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 33000.0; + } +} + +TRANSITION_LIST("cpuAddr[2]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 33000.0; + } +} + +TRANSITION_LIST("cpuAddr[3]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 33000.0; + } +} + +TRANSITION_LIST("cpuAddr[4]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 33000.0; + } +} + +TRANSITION_LIST("cpuAddr[5]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 33000.0; + } +} + +TRANSITION_LIST("cpuAddr[6]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 33000.0; + } +} + +TRANSITION_LIST("cpuAddr[7]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 33000.0; + } +} + +TRANSITION_LIST("cpuAddr[8]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 33000.0; + } +} + +TRANSITION_LIST("cpuAddr[9]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 33000.0; + } +} + +TRANSITION_LIST("cpuAddr[10]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 33000.0; + } +} + +TRANSITION_LIST("cpuAddr[11]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 33000.0; + } +} + +TRANSITION_LIST("cpuAddr[12]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 33000.0; + } +} + +TRANSITION_LIST("cpuAddr[13]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 33000.0; + } +} + +TRANSITION_LIST("cpuAddr[14]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 33000.0; + } +} + +TRANSITION_LIST("cpuAddr[15]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 33000.0; + } +} + +TRANSITION_LIST("cpuAddr[16]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 33000.0; + } +} + +TRANSITION_LIST("cpuAddr[17]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 33000.0; + } +} + +TRANSITION_LIST("cpuAddr[18]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 33000.0; + } +} + +TRANSITION_LIST("cpuAddr[19]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 33000.0; + } +} + +TRANSITION_LIST("cpuAddr[20]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 33000.0; + } +} + +TRANSITION_LIST("cpuAddr[21]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 33000.0; + } +} + +TRANSITION_LIST("cpuAddr[22]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 33000.0; + } +} + +TRANSITION_LIST("cpuAddr[23]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 33000.0; + } +} + +TRANSITION_LIST("cpuClk") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 33000.0; + } +} + +TRANSITION_LIST("cpuData[15]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 33000.0; + } +} + +TRANSITION_LIST("cpuData[14]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 33000.0; + } +} + +TRANSITION_LIST("cpuData[13]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 33000.0; + } +} + +TRANSITION_LIST("cpuData[12]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 33000.0; + } +} + +TRANSITION_LIST("cpuData[11]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 33000.0; + } +} + +TRANSITION_LIST("cpuData[10]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 33000.0; + } +} + +TRANSITION_LIST("cpuData[9]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 33000.0; + } +} + +TRANSITION_LIST("cpuData[8]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 33000.0; + } +} + +TRANSITION_LIST("cpuData[7]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 33000.0; + } +} + +TRANSITION_LIST("cpuData[6]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 33000.0; + } +} + +TRANSITION_LIST("cpuData[5]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 33000.0; + } +} + +TRANSITION_LIST("cpuData[4]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 33000.0; + } +} + +TRANSITION_LIST("cpuData[3]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 33000.0; + } +} + +TRANSITION_LIST("cpuData[2]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 33000.0; + } +} + +TRANSITION_LIST("cpuData[1]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 33000.0; + } +} + +TRANSITION_LIST("cpuData[0]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 33000.0; + } +} + +TRANSITION_LIST("cpuRnW") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 33000.0; + } +} + +TRANSITION_LIST("nReset") +{ + NODE + { + REPEAT = 1; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 32970.0; + } +} + +TRANSITION_LIST("ncpuAS") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 33000.0; + } +} + +TRANSITION_LIST("ncpuLDS") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 33000.0; + } +} + +TRANSITION_LIST("ncpuUDS") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 33000.0; + } +} + +TRANSITION_LIST("nhSync") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 33000.0; + } +} + +TRANSITION_LIST("nvSync") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 33000.0; + } +} + +TRANSITION_LIST("nvramOE") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 33000.0; + } +} + +TRANSITION_LIST("nvramWE") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 33000.0; + } +} + +TRANSITION_LIST("pixClk") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 825; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 20.0; + } + } +} + +TRANSITION_LIST("ramSize[2]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 33000.0; + } +} + +TRANSITION_LIST("ramSize[1]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 33000.0; + } +} + +TRANSITION_LIST("ramSize[0]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 33000.0; + } +} + +TRANSITION_LIST("vidOut") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 33000.0; + } +} + +TRANSITION_LIST("vramAddr[14]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 33000.0; + } +} + +TRANSITION_LIST("vramAddr[13]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 33000.0; + } +} + +TRANSITION_LIST("vramAddr[12]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 33000.0; + } +} + +TRANSITION_LIST("vramAddr[11]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 33000.0; + } +} + +TRANSITION_LIST("vramAddr[10]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 33000.0; + } +} + +TRANSITION_LIST("vramAddr[9]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 33000.0; + } +} + +TRANSITION_LIST("vramAddr[8]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 33000.0; + } +} + +TRANSITION_LIST("vramAddr[7]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 33000.0; + } +} + +TRANSITION_LIST("vramAddr[6]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 33000.0; + } +} + +TRANSITION_LIST("vramAddr[5]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 33000.0; + } +} + +TRANSITION_LIST("vramAddr[4]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 33000.0; + } +} + +TRANSITION_LIST("vramAddr[3]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 33000.0; + } +} + +TRANSITION_LIST("vramAddr[2]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 33000.0; + } +} + +TRANSITION_LIST("vramAddr[1]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 33000.0; + } +} + +TRANSITION_LIST("vramAddr[0]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 33000.0; + } +} + +TRANSITION_LIST("vramData[7]") +{ + NODE + { + REPEAT = 1; + LEVEL Z FOR 280.0; + LEVEL 1 FOR 80.0; + LEVEL Z FOR 240.0; + LEVEL 0 FOR 80.0; + LEVEL Z FOR 240.0; + LEVEL 0 FOR 80.0; + LEVEL Z FOR 32000.0; + } +} + +TRANSITION_LIST("vramData[6]") +{ + NODE + { + REPEAT = 1; + LEVEL Z FOR 280.0; + LEVEL 0 FOR 80.0; + LEVEL Z FOR 240.0; + LEVEL 1 FOR 80.0; + LEVEL Z FOR 240.0; + LEVEL 0 FOR 80.0; + LEVEL Z FOR 32000.0; + } +} + +TRANSITION_LIST("vramData[5]") +{ + NODE + { + REPEAT = 1; + LEVEL Z FOR 280.0; + LEVEL 1 FOR 80.0; + LEVEL Z FOR 240.0; + LEVEL 0 FOR 80.0; + LEVEL Z FOR 240.0; + LEVEL 1 FOR 80.0; + LEVEL Z FOR 32000.0; + } +} + +TRANSITION_LIST("vramData[4]") +{ + NODE + { + REPEAT = 1; + LEVEL Z FOR 280.0; + LEVEL 0 FOR 80.0; + LEVEL Z FOR 240.0; + LEVEL 1 FOR 80.0; + LEVEL Z FOR 240.0; + LEVEL 1 FOR 80.0; + LEVEL Z FOR 32000.0; + } +} + +TRANSITION_LIST("vramData[3]") +{ + NODE + { + REPEAT = 1; + LEVEL Z FOR 280.0; + LEVEL 1 FOR 80.0; + LEVEL Z FOR 240.0; + LEVEL 0 FOR 80.0; + LEVEL Z FOR 240.0; + LEVEL 1 FOR 80.0; + LEVEL Z FOR 32000.0; + } +} + +TRANSITION_LIST("vramData[2]") +{ + NODE + { + REPEAT = 1; + LEVEL Z FOR 280.0; + LEVEL 0 FOR 80.0; + LEVEL Z FOR 240.0; + LEVEL 1 FOR 80.0; + LEVEL Z FOR 240.0; + LEVEL 1 FOR 80.0; + LEVEL Z FOR 32000.0; + } +} + +TRANSITION_LIST("vramData[1]") +{ + NODE + { + REPEAT = 1; + LEVEL Z FOR 280.0; + LEVEL 1 FOR 80.0; + LEVEL Z FOR 240.0; + LEVEL 0 FOR 80.0; + LEVEL Z FOR 240.0; + LEVEL 0 FOR 80.0; + LEVEL Z FOR 32000.0; + } +} + +TRANSITION_LIST("vramData[0]") +{ + NODE + { + REPEAT = 1; + LEVEL Z FOR 280.0; + LEVEL 0 FOR 80.0; + LEVEL Z FOR 240.0; + LEVEL 1 FOR 80.0; + LEVEL Z FOR 240.0; + LEVEL 0 FOR 80.0; + LEVEL Z FOR 32000.0; + } +} + +DISPLAY_LINE +{ + CHANNEL = "cpuAddr"; + EXPAND_STATUS = COLLAPSED; + RADIX = Hexadecimal; + TREE_INDEX = 0; + TREE_LEVEL = 0; + CHILDREN = 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23; +} + +DISPLAY_LINE +{ + CHANNEL = "cpuAddr[1]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Hexadecimal; + TREE_INDEX = 1; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "cpuAddr[2]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Hexadecimal; + TREE_INDEX = 2; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "cpuAddr[3]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Hexadecimal; + TREE_INDEX = 3; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "cpuAddr[4]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Hexadecimal; + TREE_INDEX = 4; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "cpuAddr[5]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Hexadecimal; + TREE_INDEX = 5; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "cpuAddr[6]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Hexadecimal; + TREE_INDEX = 6; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "cpuAddr[7]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Hexadecimal; + TREE_INDEX = 7; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "cpuAddr[8]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Hexadecimal; + TREE_INDEX = 8; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "cpuAddr[9]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Hexadecimal; + TREE_INDEX = 9; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "cpuAddr[10]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Hexadecimal; + TREE_INDEX = 10; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "cpuAddr[11]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Hexadecimal; + TREE_INDEX = 11; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "cpuAddr[12]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Hexadecimal; + TREE_INDEX = 12; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "cpuAddr[13]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Hexadecimal; + TREE_INDEX = 13; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "cpuAddr[14]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Hexadecimal; + TREE_INDEX = 14; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "cpuAddr[15]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Hexadecimal; + TREE_INDEX = 15; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "cpuAddr[16]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Hexadecimal; + TREE_INDEX = 16; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "cpuAddr[17]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Hexadecimal; + TREE_INDEX = 17; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "cpuAddr[18]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Hexadecimal; + TREE_INDEX = 18; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "cpuAddr[19]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Hexadecimal; + TREE_INDEX = 19; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "cpuAddr[20]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Hexadecimal; + TREE_INDEX = 20; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "cpuAddr[21]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Hexadecimal; + TREE_INDEX = 21; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "cpuAddr[22]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Hexadecimal; + TREE_INDEX = 22; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "cpuAddr[23]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Hexadecimal; + TREE_INDEX = 23; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "cpuClk"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 24; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "cpuData"; + EXPAND_STATUS = COLLAPSED; + RADIX = Hexadecimal; + TREE_INDEX = 25; + TREE_LEVEL = 0; + CHILDREN = 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41; +} + +DISPLAY_LINE +{ + CHANNEL = "cpuData[15]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Hexadecimal; + TREE_INDEX = 26; + TREE_LEVEL = 1; + PARENT = 25; +} + +DISPLAY_LINE +{ + CHANNEL = "cpuData[14]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Hexadecimal; + TREE_INDEX = 27; + TREE_LEVEL = 1; + PARENT = 25; +} + +DISPLAY_LINE +{ + CHANNEL = "cpuData[13]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Hexadecimal; + TREE_INDEX = 28; + TREE_LEVEL = 1; + PARENT = 25; +} + +DISPLAY_LINE +{ + CHANNEL = "cpuData[12]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Hexadecimal; + TREE_INDEX = 29; + TREE_LEVEL = 1; + PARENT = 25; +} + +DISPLAY_LINE +{ + CHANNEL = "cpuData[11]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Hexadecimal; + TREE_INDEX = 30; + TREE_LEVEL = 1; + PARENT = 25; +} + +DISPLAY_LINE +{ + CHANNEL = "cpuData[10]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Hexadecimal; + TREE_INDEX = 31; + TREE_LEVEL = 1; + PARENT = 25; +} + +DISPLAY_LINE +{ + CHANNEL = "cpuData[9]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Hexadecimal; + TREE_INDEX = 32; + TREE_LEVEL = 1; + PARENT = 25; +} + +DISPLAY_LINE +{ + CHANNEL = "cpuData[8]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Hexadecimal; + TREE_INDEX = 33; + TREE_LEVEL = 1; + PARENT = 25; +} + +DISPLAY_LINE +{ + CHANNEL = "cpuData[7]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Hexadecimal; + TREE_INDEX = 34; + TREE_LEVEL = 1; + PARENT = 25; +} + +DISPLAY_LINE +{ + CHANNEL = "cpuData[6]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Hexadecimal; + TREE_INDEX = 35; + TREE_LEVEL = 1; + PARENT = 25; +} + +DISPLAY_LINE +{ + CHANNEL = "cpuData[5]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Hexadecimal; + TREE_INDEX = 36; + TREE_LEVEL = 1; + PARENT = 25; +} + +DISPLAY_LINE +{ + CHANNEL = "cpuData[4]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Hexadecimal; + TREE_INDEX = 37; + TREE_LEVEL = 1; + PARENT = 25; +} + +DISPLAY_LINE +{ + CHANNEL = "cpuData[3]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Hexadecimal; + TREE_INDEX = 38; + TREE_LEVEL = 1; + PARENT = 25; +} + +DISPLAY_LINE +{ + CHANNEL = "cpuData[2]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Hexadecimal; + TREE_INDEX = 39; + TREE_LEVEL = 1; + PARENT = 25; +} + +DISPLAY_LINE +{ + CHANNEL = "cpuData[1]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Hexadecimal; + TREE_INDEX = 40; + TREE_LEVEL = 1; + PARENT = 25; +} + +DISPLAY_LINE +{ + CHANNEL = "cpuData[0]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Hexadecimal; + TREE_INDEX = 41; + TREE_LEVEL = 1; + PARENT = 25; +} + +DISPLAY_LINE +{ + CHANNEL = "cpuRnW"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 42; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "nReset"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 43; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "ncpuAS"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 44; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "ncpuLDS"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 45; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "ncpuUDS"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 46; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "nhSync"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 47; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "nvSync"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 48; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "nvramOE"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 49; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "nvramWE"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 50; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "pixClk"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 51; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "ramSize"; + EXPAND_STATUS = COLLAPSED; + RADIX = Octal; + TREE_INDEX = 52; + TREE_LEVEL = 0; + CHILDREN = 53, 54, 55; +} + +DISPLAY_LINE +{ + CHANNEL = "ramSize[2]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Octal; + TREE_INDEX = 53; + TREE_LEVEL = 1; + PARENT = 52; +} + +DISPLAY_LINE +{ + CHANNEL = "ramSize[1]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Octal; + TREE_INDEX = 54; + TREE_LEVEL = 1; + PARENT = 52; +} + +DISPLAY_LINE +{ + CHANNEL = "ramSize[0]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Octal; + TREE_INDEX = 55; + TREE_LEVEL = 1; + PARENT = 52; +} + +DISPLAY_LINE +{ + CHANNEL = "vidOut"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 56; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "vramAddr"; + EXPAND_STATUS = COLLAPSED; + RADIX = Hexadecimal; + TREE_INDEX = 57; + TREE_LEVEL = 0; + CHILDREN = 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72; +} + +DISPLAY_LINE +{ + CHANNEL = "vramAddr[14]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Hexadecimal; + TREE_INDEX = 58; + TREE_LEVEL = 1; + PARENT = 57; +} + +DISPLAY_LINE +{ + CHANNEL = "vramAddr[13]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Hexadecimal; + TREE_INDEX = 59; + TREE_LEVEL = 1; + PARENT = 57; +} + +DISPLAY_LINE +{ + CHANNEL = "vramAddr[12]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Hexadecimal; + TREE_INDEX = 60; + TREE_LEVEL = 1; + PARENT = 57; +} + +DISPLAY_LINE +{ + CHANNEL = "vramAddr[11]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Hexadecimal; + TREE_INDEX = 61; + TREE_LEVEL = 1; + PARENT = 57; +} + +DISPLAY_LINE +{ + CHANNEL = "vramAddr[10]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Hexadecimal; + TREE_INDEX = 62; + TREE_LEVEL = 1; + PARENT = 57; +} + +DISPLAY_LINE +{ + CHANNEL = "vramAddr[9]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Hexadecimal; + TREE_INDEX = 63; + TREE_LEVEL = 1; + PARENT = 57; +} + +DISPLAY_LINE +{ + CHANNEL = "vramAddr[8]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Hexadecimal; + TREE_INDEX = 64; + TREE_LEVEL = 1; + PARENT = 57; +} + +DISPLAY_LINE +{ + CHANNEL = "vramAddr[7]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Hexadecimal; + TREE_INDEX = 65; + TREE_LEVEL = 1; + PARENT = 57; +} + +DISPLAY_LINE +{ + CHANNEL = "vramAddr[6]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Hexadecimal; + TREE_INDEX = 66; + TREE_LEVEL = 1; + PARENT = 57; +} + +DISPLAY_LINE +{ + CHANNEL = "vramAddr[5]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Hexadecimal; + TREE_INDEX = 67; + TREE_LEVEL = 1; + PARENT = 57; +} + +DISPLAY_LINE +{ + CHANNEL = "vramAddr[4]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Hexadecimal; + TREE_INDEX = 68; + TREE_LEVEL = 1; + PARENT = 57; +} + +DISPLAY_LINE +{ + CHANNEL = "vramAddr[3]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Hexadecimal; + TREE_INDEX = 69; + TREE_LEVEL = 1; + PARENT = 57; +} + +DISPLAY_LINE +{ + CHANNEL = "vramAddr[2]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Hexadecimal; + TREE_INDEX = 70; + TREE_LEVEL = 1; + PARENT = 57; +} + +DISPLAY_LINE +{ + CHANNEL = "vramAddr[1]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Hexadecimal; + TREE_INDEX = 71; + TREE_LEVEL = 1; + PARENT = 57; +} + +DISPLAY_LINE +{ + CHANNEL = "vramAddr[0]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Hexadecimal; + TREE_INDEX = 72; + TREE_LEVEL = 1; + PARENT = 57; +} + +DISPLAY_LINE +{ + CHANNEL = "vramData"; + EXPAND_STATUS = COLLAPSED; + RADIX = Hexadecimal; + TREE_INDEX = 73; + TREE_LEVEL = 0; + CHILDREN = 74, 75, 76, 77, 78, 79, 80, 81; +} + +DISPLAY_LINE +{ + CHANNEL = "vramData[7]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Hexadecimal; + TREE_INDEX = 74; + TREE_LEVEL = 1; + PARENT = 73; +} + +DISPLAY_LINE +{ + CHANNEL = "vramData[6]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Hexadecimal; + TREE_INDEX = 75; + TREE_LEVEL = 1; + PARENT = 73; +} + +DISPLAY_LINE +{ + CHANNEL = "vramData[5]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Hexadecimal; + TREE_INDEX = 76; + TREE_LEVEL = 1; + PARENT = 73; +} + +DISPLAY_LINE +{ + CHANNEL = "vramData[4]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Hexadecimal; + TREE_INDEX = 77; + TREE_LEVEL = 1; + PARENT = 73; +} + +DISPLAY_LINE +{ + CHANNEL = "vramData[3]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Hexadecimal; + TREE_INDEX = 78; + TREE_LEVEL = 1; + PARENT = 73; +} + +DISPLAY_LINE +{ + CHANNEL = "vramData[2]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Hexadecimal; + TREE_INDEX = 79; + TREE_LEVEL = 1; + PARENT = 73; +} + +DISPLAY_LINE +{ + CHANNEL = "vramData[1]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Hexadecimal; + TREE_INDEX = 80; + TREE_LEVEL = 1; + PARENT = 73; +} + +DISPLAY_LINE +{ + CHANNEL = "vramData[0]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Hexadecimal; + TREE_INDEX = 81; + TREE_LEVEL = 1; + PARENT = 73; +} + +TIME_BAR +{ + TIME = 0; + MASTER = TRUE; +} +; diff --git a/vgacount.sv b/vgacount.sv index 9d120c4..3028b3c 100644 --- a/vgacount.sv +++ b/vgacount.sv @@ -7,10 +7,13 @@ * Low-level VGA signal counter *****************************************************************************/ +`ifndef VGACOUNT + `define VGACOUNT + module vgacount ( input wire nReset, // system reset signal input wire clock, // counter increment clock - output logic [9:0] count, // count output + output logic [9:0] count, // count output output wire nSync, // sync pulse output wire activeVid, // active video signal output wire activeSE // secondary active video signal (SE) @@ -45,23 +48,25 @@ always_comb begin count <= counter; // Sync pulse - if(hCount >= SYNCBEGIN && hCount < SYNCEND) begin - nhSync <= 1'b0; + if(count >= SYNCBEGIN && count < SYNCEND) begin + nSync <= 1'b0; end else begin - nhSync <= 1'b1; + nSync <= 1'b1; end - if(hCount >= ACTBEGIN && hCount < ACTEND) begin - hActive <= 1'b0; + if(count >= ACTBEGIN && count < ACTEND) begin + activeVid <= 1'b0; end else begin - hActive <= 1'b1; + activeVid <= 1'b1; end - if(hCount >= SEACTBEGIN) begin - hSEActive <= 1'b0; + if(count >= SEACTBEGIN) begin + activeSE <= 1'b0; end else begin - hSEActive <= 1'b1; + activeSE <= 1'b1; end end -endmodule \ No newline at end of file +endmodule + +`endif \ No newline at end of file diff --git a/vgagen.sv b/vgagen.sv index 7ae371a..86bb490 100644 --- a/vgagen.sv +++ b/vgagen.sv @@ -7,6 +7,9 @@ * Generates VGA timing signals & counters *****************************************************************************/ +`ifndef VGAGEN + `define VGAGEN + `include "vgacount.sv" module vgagen ( @@ -25,4 +28,6 @@ module vgagen ( vgacount #(800,592,688,576,736,512) hoz(nReset,pixClk,hCount,nhSync,hActive,hSEActive); vgacount #(525,421,423,411,456,342) ver(nReset,nhSync,vCount,nvSync,vActive,vSEActive); -endmodule \ No newline at end of file +endmodule + +`endif \ No newline at end of file diff --git a/vgaout.sv b/vgaout.sv index 4a37009..1392c96 100644 --- a/vgaout.sv +++ b/vgaout.sv @@ -7,7 +7,7 @@ * Fetches video data from VRAM and shifts out *****************************************************************************/ -`include "primitives.sv" +`include "primitives/primitives.sv" module vgaout ( input wire pixClock, @@ -16,8 +16,8 @@ module vgaout ( input logic [9:0] vCount, input wire hSEActive, input wire vSEActive, - inout logic [7:0] vramData, - output logic [12:0] vramAddr, + input logic [7:0] vramData, + output logic [14:0] vramAddr, output wire nvramOE, output wire vidOut ); @@ -50,7 +50,7 @@ always @(posedge pixClock or negedge nReset) begin if(nReset == 1'b0) begin rVid <= 8'h0; end else begin - if(hCount[2:0] == 3'b7) begin + if(hCount[2:0] == 3'h7) begin rVid <= vramData; end end @@ -72,7 +72,7 @@ always_comb begin end // vram read signal - if(vidActive == 1'b1 && hCount[2:0] == 3'b7) begin + if(vidActive == 1'b1 && hCount[2:0] == 3'h7) begin nvramOE <= 1'b0; end else begin nvramOE <= 1'b1; @@ -80,7 +80,7 @@ always_comb begin // vram address signals // these will be mux'd with cpu addresses externally - vramAddr[12:6] <= vCount[6:0]; + vramAddr[14:6] <= vCount[8:0]; vramAddr[5:0] <= hCount[8:3]; end