Starting new cpu snoop

se-xga.sv

@@ -42,17 +42,17 @@ logic [9:0] vCount;     // 0..805
 // horizontal counter
 always @(negedge pixClk or negedge nReset) begin
     if(!nReset) hCount <= 0;
-    else begin
-        if(hCount < 1343) hCount <= hCount + 1;
+    else if(!pixClk) begin
+        if(hCount < 1343) hCount <= hCount + 11'd1;
         else hCount <= 0;
     end
 end
 
 // vertical counter
-always @(negedge pixClk or negedge nReset) begin
+always @(negedge nhSync or negedge nReset) begin
     if(!nReset) vCount <= 0;
-    else begin
-        if(vCount < 805) vCount <= vCount + 1;
+    else if(!pixClk) begin
+        if(vCount < 805) vCount <= vCount + 10'd1;
         else vCount <= 0;
     end
 end
@@ -75,7 +75,7 @@ wire hActive, vActive;      // active video signals. vidout black when negated
 wire vidActive;             // active when both hActive and vActive asserted
 wire hLoad;                 // load pixel data from vram when asserted
 
-assign vidActive = hActive & vidActive;
+assign vidActive = hActive & vActive;
 
 always_comb begin
     if(hCount >= 1 && hCount < 1025) hActive <= 1;
@@ -97,6 +97,7 @@ end
 logic [8:0] vidData;        // the video data we are displaying
 wire  [2:0] vidSeq;         // sequence counter, derived from hCount
 wire tick, tock;            // even/odd pulses of pixel clock divided by 2
+wire [14:0] readAddr;              // VRAM read address
 
 assign vidSeq = hCount[3:1];
 assign tick = !hCount[0];
@@ -104,8 +105,8 @@ assign tock = hCount[0];
 
 always @(negedge pixClk or negedge nReset) begin
     if(!nReset) vidData <= 0;
-    else
-        if(tock && hLoad && vidSeq == 0) begin
+    else if(!pixClk) begin
+        if(tock && hLoad && vidSeq == 3'd0) begin
             // store the VRAM data in vidData[8:1]
             //vidData[0] <= vidData[1]; // this should actually have already been done
             vidData[8:1] <= vramData;
@@ -123,8 +124,15 @@ always_comb begin
     else vidOut <= 0;
 
     // vram read signal can be asserted here
-    if(vidActive && vidSeq == 0) nvramOE <= 0;
+    if(vidActive && vidSeq == 3'd0) nvramOE <= 0;
     else nvramOE <= 1;
+
+    // we'll be interleaving VRAM accesses, so the highest address bit will be
+    // used to select between Main & Aux video buffers.
+    // hCount[4] will be used to select between SRAM chips
+    readAddr[14] <= vidBufSel;
+    readAddr[13:5] <= vCount[9:1];
+    readAddr[4:0] <= hCount[9:5];
 end
 
 
@@ -140,6 +148,20 @@ end
 // vramCE[x] should be asserted when vidSeq == 0
 // vramOE should be asserted when vidSeq == 0 && vidActive
 // vramWE should be asserted on tock pulses of write sequences
+wire [14:0] writeAddr;
+reg vidBufSel;
+wire nvramCE0cpu, nvramCE1cpu;
+
+
+reg nvramWEpre;
+
+always @(negedge pixClk or negedge nReset) begin
+    if(nReset) begin
+        nvramWEpre <= 1;
+    end else if(!pixClk && vidSeq != 0 && (!ncpuLDS || !ncpuUDS) && tock) begin
+        
+    end
+end
 
 /*
 // link module that snoops cpu writes
@@ -176,12 +198,31 @@ cpusnoop cpusnp(
     .ncpuLDS(ncpuLDS),
     .cpuRnW(cpuRnW),
     .cpuClk(cpuClk),
-    .vramAddr(),
+    .vramAddr(writeAddr),
     .vramDataOut(),
     .nvramWE(),
-    .nvramCE0(),
-    .nvramCE1(),
+    .nvramCE0(nvramCE0cpu),
+    .nvramCE1(nvramCE1cpu),
     .vidBufSelOut(),
     .ramSize(ramSize)
 );
-*/
+*/
+
+always_comb begin
+    if(nvramOE == 0) vramAddr <= readAddr;
+    else if(nvramWE == 0) vramAddr <= writeAddr;
+    else vramAddr <= 0;
+
+    if(nvramOE == 0) begin
+        nvramCE0 <= hCount[4];
+        nvramCE1 <= ~hCount[4];
+    end else if(nvramWE == 0) begin
+        nvramCE0 <= nvramCE0cpu;
+        nvramCE1 <= nvramCE1cpu;
+    end else begin
+        nvramCE0 <= 1;
+        nvramCE1 <= 1;
+    end
+end
+
+endmodule