96 lines
2.7 KiB
Systemverilog
96 lines
2.7 KiB
Systemverilog
/******************************************************************************
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* SE-VGA
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* Top-level module
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* techav
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* 2021-04-06
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******************************************************************************
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* Pulls together all the smaller modules to form the SE-VGA adapter
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*****************************************************************************/
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module design sevga (
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input wire nReset, // System reset signal
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input wire pixClk, // 25.175MHz pixel clock
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output wire nhSync, // HSync signal
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output wire nvSync, // VSync signal
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output wire vidOut, // 1-bit Monochrome video signal
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output logic [12:0] vramAddr, // VRAM Address bus
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inout logic [7:0] vramData, // VRAM Data bus
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output wire nvramOE, // VRAM Read strobe
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output wire nvramWE, // VRAM Write strobe
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input logic [23:1] cpuAddr, // CPU Address bus
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input logic [15:0] cpuData, // CPU Data bus
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input wire ncpuAS, // CPU Address Strobe signal
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input wire ncpuUDS, // CPU Upper Data Strobe signal
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input wire ncpuLDS, // CPU Lower Data Strobe signal
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input wire cpuRnW, // CPU Read/Write select signal
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input wire cpuClk // CPU Clock
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);
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logic [9:0] hCount;
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logic [9:0] vCount;
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wire hActive;
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wire hSEActive;
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//logic [7:0] vidVramData;
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logic [12:0] vidVramAddr;
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//logic [7:0] cpuVramData;
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logic [12:0] cpuVramAddr;
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// link module that generates all our timing signals
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vgagen vgatiming(
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.nReset(nReset),
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.pixClk(pixClk),
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.hCount(hCount),
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.hActive(hActive),
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.hSEActive(hSEActive),
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.nhSync(nhSync),
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.vCount(vCount),
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.vActive(vActive),
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.vSEActive(vSEActive),
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.nvSync(nvSync)
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);
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// link module that fetches & outputs video data
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vgaout vidvram(
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.pixClock(pixClk),
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.nReset(nReset),
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.hCount(hCount),
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.vCount(vCount),
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.hSEActive(hSEActive),
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.vSEActive(vSEActive),
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.vramData(vramData),
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.vramAddr(vidVramAddr),
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.nvramOE(nvramOE),
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.vidOut(vidOut)
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);
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// link module that handles cpu writes
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cpusnoop cpusnp(
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.nReset(nReset),
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.pixClock(pixClk),
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.sequence(hCount[2:0]),
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.cpuAddr(cpuAddr),
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.cpuData(cpuData),
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.ncpuAS(ncpuAS),
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.ncpuUDS(ncpuUDS),
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.ncpuLDS(ncpuLDS),
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.cpuRnW(cpuRnW),
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.cpuClk(cpuClk),
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.vramAddr(vramAddr),
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.vramData(cpuVramData),
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.nvramWE(nvramWE)
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);
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always_comb begin
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// vramAddr muxing
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if(.nvramWE == 1'b0) begin
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vramAddr <= cpuVramAddr;
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end else begin
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vramAddr <= vidVramData;
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end
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end
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endmodule |