80 lines
2.0 KiB
Systemverilog
80 lines
2.0 KiB
Systemverilog
/******************************************************************************
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* SE-VGA
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* VGA video output
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* techav
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* 2021-04-06
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******************************************************************************
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* Fetches video data from VRAM and shifts out
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*****************************************************************************/
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`include "vgashiftout.sv"
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module vgaout (
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input wire pixClock,
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input wire nReset,
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input logic [9:0] hCount,
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input logic [9:0] vCount,
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input wire hSEActive,
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input wire vSEActive,
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input logic [7:0] vramData,
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output logic [14:0] vramAddr,
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output wire nvramOE,
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output wire vidOut
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);
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//reg [7:0] rVid;
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wire vidMuxOut;
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wire vidActive; // combined active video signal
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//wire vgaShiftEn; // Enable pixel shift out
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wire vgaShiftL1; // Load VRAM data into register
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wire vgaShiftL2; // Load VRAM data into shifter
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vgaShiftOut vOut(
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.nReset(nReset),
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.clk(pixClock),
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.shiftEn(vidActive),
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.nLoad1(vgaShiftL1),
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.nLoad2(vgaShiftL2),
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.parIn(vramData),
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.out(vidMuxOut)
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);
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always_comb begin
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// load VRAM data into register
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if(hCount[2:0] == 0) vgaShiftL1 <= !pixClock;
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else vgaShiftL1 <= 1;
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// load VRAM data into shifter
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if(hCount[2:0] == 0) vgaShiftL2 <= !pixClock;
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else if(hCount[2:0] == 1) vgaShiftL2 <= pixClock;
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else vgaShiftL2 <= 1;
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// combined video active signal
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if(hSEActive == 1'b1 && vSEActive == 1'b1) begin
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vidActive <= 1'b1;
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end else begin
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vidActive <= 1'b0;
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end
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// video data output
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if(vidActive == 1'b1) begin
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vidOut <= vidMuxOut;
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end else begin
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vidOut <= 1'b0;
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end
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// vram read signal
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if(vidActive == 1'b1 && hCount[2:0] == 0) begin
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nvramOE <= 1'b0;
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end else begin
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nvramOE <= 1'b1;
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end
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// vram address signals
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// these will be mux'd with cpu addresses externally
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vramAddr[14:6] <= vCount[8:0];
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vramAddr[5:0] <= hCount[8:3];
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end
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endmodule |