104 lines
3.1 KiB
Systemverilog
104 lines
3.1 KiB
Systemverilog
/******************************************************************************
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* SE-VGA
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* VGA Shift Out
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* techav
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* 2021-04-06
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******************************************************************************
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* 2-stage shift register for storing & shifting out pixel data
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*****************************************************************************/
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`ifndef VGASHIFTOUT
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`define VGASHIFTOUT
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module vgaShiftOut (
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input wire nReset,
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input wire clk,
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input wire shiftEn,
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input wire nLoad1,
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input wire nLoad2,
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input logic [7:0] parIn,
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output wire out
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);
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reg [7:0] inReg;
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reg [7:0] outReg;
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always @(posedge clk or negedge nReset) begin
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if(!nReset) inReg <= 0;
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else if(!nLoad1) inReg <= parIn;
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end
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always @(negedge clk or negedge nReset) begin
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if(!nReset) outReg <= 0;
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else begin
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if(!nLoad2) outReg <= inReg;
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else if(shiftEn) begin
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outReg[7] <= outReg[6];
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outReg[6] <= outReg[5];
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outReg[5] <= outReg[4];
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outReg[4] <= outReg[3];
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outReg[3] <= outReg[2];
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outReg[2] <= outReg[1];
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outReg[1] <= outReg[0];
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outReg[0] <= 0;
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end
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end
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end
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assign out = outReg[7];
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endmodule
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// module vgaShiftOut (
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// input wire nReset,
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// input wire clk,
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// input wire vidActive,
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// input logic [2:0] seq,
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// input logic [7:0] parIn,
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// output wire out
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// );
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// /* Shift register functioning similar to a 74597, with 8-bit input latch
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// * and 8-bit PISO shift register output stage.
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// * In sequence 0 new data is loaded from VRAM into the input stage, and in
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// * sequence 1 the input stage is copied to the output stage to be shifted.
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// */
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// reg [7:0] inReg;
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// reg [7:0] outReg;
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// // to meet VRAM timing requirements, data from VRAM has to be clocked into
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// // our input register on the rising edge of the pixel clock
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// always @(posedge clk or negedge nReset) begin
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// if(nReset == 0) begin
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// inReg <= 0;
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// end else begin
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// if(seq == 0) begin
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// inReg <= parIn;
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// end
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// end
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// end
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// // pixels are shifted out on the falling edge of the pixel clock
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// always @(negedge clk or negedge nReset) begin
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// if(nReset == 1'b0) begin
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// //inReg <= 0;
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// outReg <= 0;
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// end else begin
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// if(vidActive == 1'b1) begin
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// if(seq == 0) begin
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// outReg <= inReg;
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// end else begin
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// outReg[7] <= outReg[6];
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// outReg[6] <= outReg[5];
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// outReg[5] <= outReg[4];
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// outReg[4] <= outReg[3];
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// outReg[3] <= outReg[2];
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// outReg[2] <= outReg[1];
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// outReg[1] <= outReg[0];
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// outReg[0] <= 1'b0;
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// end
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// end
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// end
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// end
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// assign out = outReg[7];
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// endmodule
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`endif |