157 lines
3.7 KiB
Systemverilog
157 lines
3.7 KiB
Systemverilog
/******************************************************************************
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* SE-VGA
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* Primitives
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* techav
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* 2021-04-06
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******************************************************************************
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* Basic modules to be used elsewhere
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*****************************************************************************/
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`ifndef PRIMS
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`define PRIMS
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/*
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// basic d-flipflop
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module myDff (
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input wire nReset,
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input wire clk,
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input wire d,
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output reg q
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);
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always @(posedge clk or negedge nReset) begin
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if(nReset == 1'b0) begin
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q <= 1'b0;
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end else begin
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q <= d;
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end
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end
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endmodule
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*/
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/*
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// basic 8-bit mux
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module mux8 (
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input logic [7:0] inA,
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input logic [7:0] inB,
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input wire select,
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output logic [7:0] out
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);
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always_comb begin
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if(select == 1'b0) begin
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out <= inA;
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end else begin
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out <= inB;
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end
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end
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endmodule
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*/
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/*
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// basic 8-to-1 mux
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module mux8x1 (
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input logic[7:0] in,
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input logic[2:0] select,
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output wire out
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);
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assign out = in[select];
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endmodule
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*/
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/*
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// basic 8-to-1 mux with transparent output latch
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module mux8x1latch (
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input logic[7:0] in,
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input logic[2:0] select,
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input wire clock,
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input wire nReset,
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output reg out
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);
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wire muxOut;
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mux8x1 mux (in,select,muxOut);
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// transparent latch -- when clock is low, output will
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// follow the output of the mux. When clock is high,
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// output will hold its last value.
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always @(clock or nReset or muxOut or out) begin
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if(nReset == 1'b0) begin
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out = 1'b0;
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end else if(clock == 1'b0) begin
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out = muxOut;
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end else begin
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out = out;
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end
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end
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endmodule
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*/
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/*
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// basic 8-bit PISO shift register
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module piso8 (
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input wire nReset,
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input wire clk,
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input wire load,
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input logic [7:0] parIn,
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output wire out
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);
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logic [7:0] muxIns;
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logic [7:0] muxOuts;
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mux8 loader(muxIns[7:0],parIn[7:0],load,muxOuts[7:0]);
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myDff u0(nReset,clk,muxOuts[0],muxIns[1]);
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myDff u1(nReset,clk,muxOuts[1],muxIns[2]);
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myDff u2(nReset,clk,muxOuts[2],muxIns[3]);
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myDff u3(nReset,clk,muxOuts[3],muxIns[4]);
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myDff u4(nReset,clk,muxOuts[4],muxIns[5]);
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myDff u5(nReset,clk,muxOuts[5],muxIns[6]);
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myDff u6(nReset,clk,muxOuts[6],muxIns[7]);
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myDff u7(nReset,clk,muxOuts[7],muxIns[0]);
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assign out = muxIns[0];
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endmodule
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*/
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module vidShiftOut (
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input wire nReset,
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input wire clk,
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input wire vidActive,
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input logic [2:0] seq,
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input logic [7:0] parIn,
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output wire out
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);
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/* Shift register functioning similar to a 74597, with 8-bit input latch
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* and 8-bit PISO shift register output stage.
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* In sequence 7 new data is loaded from VRAM into the input stage, and in
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* sequence 0 the input stage is copied to the output stage to be shifted.
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*/
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reg [7:0] inReg;
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reg [7:0] outReg;
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always @(negedge clk or negedge nReset) begin
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if(nReset == 1'b0) begin
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inReg <= 0;
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outReg <= 0;
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end else begin
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if(vidActive == 1'b1) begin
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if(seq == 0) begin
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outReg <= inReg;
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end else begin
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outReg[7] <= outReg[6];
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outReg[6] <= outReg[5];
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outReg[5] <= outReg[4];
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outReg[4] <= outReg[3];
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outReg[3] <= outReg[2];
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outReg[2] <= outReg[1];
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outReg[1] <= outReg[0];
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outReg[0] <= 1'b0;
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end
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if(seq == 7) begin
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inReg <= parIn;
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end
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end
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end
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end
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assign out = outReg[7];
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endmodule
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`endif |