342 lines
13 KiB
Systemverilog
342 lines
13 KiB
Systemverilog
/******************************************************************************
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* SE-VGA
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* Top-level module
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* techav
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* 2021-10-12
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******************************************************************************
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* This is ... mostly working. It has some write glitches and a vertical line
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* five pixels from the left side of the screen.
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*****************************************************************************/
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module sevga (
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input wire nReset, // System reset signal
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input wire pixClk, // 65MHz pixel clock
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output wire nhSync, // HSync signal
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output wire nvSync, // VSync signal
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output wire vidOut, // 1-bit Monochrome video signal
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output logic [14:0] vramAddr, // VRAM Address bus
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inout logic [7:0] vramData, // VRAM Data bus
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output wire nvramOE, // VRAM Read strobe
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output wire nvramWE, // VRAM Write strobe
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output wire nvramCE0, // VRAM Main chip select signal
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output wire nvramCE1, // VRAM Alt chip select signal
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input logic [23:1] cpuAddr, // CPU Address bus
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input logic [15:0] cpuData, // CPU Data bus
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input wire ncpuAS, // CPU Address Strobe signal
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input wire ncpuUDS, // CPU Upper Data Strobe signal
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input wire ncpuLDS, // CPU Lower Data Strobe signal
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input wire cpuRnW, // CPU Read/Write select signal
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input logic [2:0] ramSize // Select installed RAM size
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);
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/******************************************************************************
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* Initial Video Signal Timing
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* The following four functions establish the basic XGA signal timing and
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* assert the horizontal and vertical sync signals as appropriate.
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* These functions are the minimum required for a signal presence detect test.
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*****************************************************************************/
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logic [10:0] hCount; // 0..1343
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logic [9:0] vCount; // 0..805
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wire nhSyncInner;
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// Primary video sync counters -- Now more synchronous!
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always @(negedge pixClk) begin
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if(hCount < 11'd1343) hCount <= hCount + 11'd1;
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else begin
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hCount <= 11'd0;
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if(vCount < 10'd805) vCount <= vCount + 10'd1;
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else vCount <= 10'd0;
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end
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end
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// horizontal and vertical sync signals
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always_comb begin
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//if(hCount >= 11'd1048 && hCount < 11'd1184) nhSyncInner <= 0;
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if(hCount >= 11'd1052 && hCount < 11'd1187) nhSyncInner <= 0;
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else nhSyncInner <= 1;
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nhSync <= nhSyncInner;
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if(vCount >= 10'd729 && vCount < 10'd735) nvSync <= 0;
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else nvSync <= 1;
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end
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/******************************************************************************
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* Useful signals
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* Here we break out a few useful signals, derived from the timing above, that
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* will help us elsewhere.
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*****************************************************************************/
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wire hActive, vActive; // active video signals. vidout black when negated
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wire vidActive; // active when both hActive and vActive asserted
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wire hLoad; // load pixel data from vram when asserted
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assign vidActive = hActive & vActive;
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always_comb begin
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if(hCount >= 3 && hCount < 1027) hActive <= 1;
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else hActive <= 0;
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if(vCount >= 0 && vCount < 684) vActive <= 1;
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else vActive <= 0;
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if(hCount >= 0 && hCount < 1024 && vActive) hLoad <= 1;
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else hLoad <= 0;
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end
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/******************************************************************************
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* Primary State Machine
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* This is the primary state machine which runs the entire system, handling
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* VRAM reads, VRAM writes, VIA writes, and idle states
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*****************************************************************************/
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// used to align primary state machine with horizontal counter
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wire [3:0] vSeq = hCount[3:0];
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// define state machine states (Gray code)
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parameter
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S0 = 4'b0000, // VRAM Read 0
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S1 = 4'b0001, // VRAM Read 1
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S2 = 4'b0011, // Idle
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S3 = 4'b0010, // VRAM Write Upper 0
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S4 = 4'b0110, // VRAM Write Upper 1
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S5 = 4'b0111, // VRAM Write Lower 0
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S6 = 4'b0101, // VRAM Write Lower 1
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S7 = 4'b0100, // VIA Write
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S8 = 4'b1100, // VSync (to be added later)
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S9 = 4'b1101, // undefined
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S10 = 4'b1111, // undefined
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S11 = 4'b1110, // undefined
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S12 = 4'b1010, // undefined
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S13 = 4'b1011, // undefined
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S14 = 4'b1001, // undefined
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S15 = 4'b1000; // undefined
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logic [3:0] pState;
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// And here is the much simplified primary state machine
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always @(negedge pixClk or negedge nReset) begin
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if(!nReset) pState <= S2; // resync on reset by jumping to idle state
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else begin
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case(pState)
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S0: pState <= S1; // first VRAM read state, always move to S1
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S3: pState <= S4; // first UDS write state, always move to S4
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S5: pState <= S6; // first LDS write state, always move to S6
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/*S7: begin
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pState <= S2;
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end*/
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S2: begin
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// here is where everything actually happens.
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if(vSeq == 4'hF) pState <= S0; // time for a read state
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else if(cpuUWriteReq && !cpuUWriteSrv && vSeq < 4'hD) pState <= S3;
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else if(cpuLWriteReq && !cpuLWriteSrv && vSeq < 4'hD) pState <= S5;
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else if(cpuVIAReq && !cpuVIASrv && vSeq < 4'hE) pState <= S7;
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else pState <= S2;
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end
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default: pState <= S2; // everyone ends up at S2 (idle)
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endcase
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end
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end
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// primary VRAM signal combination, based on the primary state machine
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always_comb begin
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// VRAM Read Strobe
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if((pState == S0 || pState == S1) && hLoad) nvramOE <= 0;
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else nvramOE <= 1;
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// VRAM Write Strobe
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if(pState == S3 || pState == S5) nvramWE <= 0;
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else nvramWE <= 1;
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// VRAM Chip Enable Signals
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case(pState)
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S0, S1: begin
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if(hLoad) begin
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nvramCE0 <= ~vidBufSel;
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nvramCE1 <= vidBufSel;
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end else begin
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nvramCE0 <= 1;
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nvramCE1 <= 1;
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end
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end
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S3, S4, S5, S6: begin
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nvramCE0 <= ~cpuBufSel;
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nvramCE1 <= cpuBufSel;
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end
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default: begin
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nvramCE0 <= 1;
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nvramCE1 <= 1;
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end
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endcase
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// VRAM Address Bus
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case(pState)
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S0, S1: begin
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// address bus for read cycles
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if(hLoad) begin
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vramAddr[14:6] <= vCount[9:1];
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vramAddr[5:0] <= hCount[9:4];
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end else begin
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vramAddr <= 0;
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end
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end
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S3, S4: begin
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// address bus for upper write cycles
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vramAddr[14:1] <= cpuAddrShift;
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vramAddr[0] <= 0;
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end
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S5, S6: begin
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// address bus for lower write cycles
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vramAddr[14:1] <= cpuAddrShift;
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vramAddr[0] <= 1;
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end
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default: begin
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// address bus for idle cycles
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vramAddr <= 0;
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end
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endcase
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// VRAM Data bus
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case(pState)
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S3, S4 : vramData <= cpuData[15:8];
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S5, S6 : vramData <= cpuData[7:0];
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default: vramData <= 8'hZ;
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endcase
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end
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/******************************************************************************
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* Video Output Sequencing
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* Here is the primary video output shift register sequencing.
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* With these functions in place, it should be possible to strap the VRAM data
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* signals and see the strapped pattern output on screen.
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*****************************************************************************/
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logic [8:0] vidData; // the video data we are displaying
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// output shift register
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always @(posedge pixClk) begin
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if(pState == S1 && hLoad) begin
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// store VRAM data in shift register
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vidData[7:0] <= vramData;
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end else if(!hCount[0] && vidActive) begin
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// shift out video data
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vidData[8:1] <= vidData[7:0];
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vidData[0] <= 1;
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end
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end
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// final video output
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always_comb begin
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if(vidActive) vidOut <= ~vidData[8];
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else vidOut <= 0;
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end
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/******************************************************************************
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* CPU Bus Snooping
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* Watch the CPU bus for writes to the video buffer regions of memory and write
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* that data to VRAM. VRAM write cycles can occur during vidSeq 1 through 7.
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* High-order bytes are passed to VRAM on tick states and low-order bytes are
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* passed to VRAM on tock states. After the VRAM writes are complete, state
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* machine waits for the CPU cycle to end before returning to idle.
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*****************************************************************************/
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/* Main framebuffer starts $5900 below the top of RAM, alt frame buffer is
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* $8000 below the main frame buffer
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* ramSize is used to mask the CPU Address bits [21:19] to select the amount
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* of memory installed in the computer. Not all possible ramSize selections
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* are valid memory sizes when using 30-pin SIMMs in the Mac SE.
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* They may be possible using PDS RAM expansion cards.
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* ramSize mainBuffer altBuffer ramTop+1 ramSize Valid? Installed SIMMs
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* $7 $3fa700 $3f2700 $400000 4.0MB Y [ 1MB 1MB ][ 1MB 1MB ]
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* $6 $37a700 $372700 $380000 3.5MB N
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* $5 $2fa700 $2f2700 $300000 3.0MB N
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* $4 $27a700 $272700 $280000 2.5MB Y [ 1MB 1MB ][256kB 256kB]
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* $3 $1fa700 $1f2700 $200000 2.0MB Y [ 1MB 1MB ][ --- --- ]
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* $2 $17a700 $172700 $180000 1.5MB N
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* $1 $0fa700 $0f2700 $100000 1.0MB Y [256kB 256kB][256kB 256kB]
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* $0 $07a700 $072700 $080000 0.5MB Y [256kB 256kB][ --- --- ]
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*/
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// keep track of pending CPU write requests and whether they have been serviced
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wire cpuUWriteReq, cpuLWriteReq, cpuVIAReq;
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reg cpuUWriteSrv, cpuLWriteSrv, cpuVIASrv;
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wire cpuBufSel;
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wire cpuBufAddr;
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reg vidBufSel;
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wire [13:0] cpuAddrShift = cpuAddr[14:1] - 14'h1380;
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wire cpuBufRange;
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// these are some helpful signals that shortcut the CPU buffer & VIA addresses
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always_comb begin
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/*if(cpuAddr[14:1] >= 14'h1380
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&& cpuAddr[14:1] < 14'h3E40) cpuBufRange <= 1;
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else cpuBufRange <= 0;*/
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cpuBufRange <= (cpuAddr[14:1] >= 14'h1380) & (cpuAddr[14:1] < 14'h3E40);
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if(!ncpuAS && !cpuRnW
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&& !cpuAddr[23] && !cpuAddr[22] // first two bits always 0
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&& !(cpuAddr[21] ^ ramSize[2]) // compare with RAM Size bits
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&& !(cpuAddr[20] ^ ramSize[1])
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&& !(cpuAddr[19] ^ ramSize[0])
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&& cpuAddr[18] && cpuAddr[17] // next three bits always 1
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&& cpuAddr[16] // skip 15, it selects buffers
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&& cpuBufRange // only select buffer addresses
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) begin
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cpuBufAddr <= 1;
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end else begin
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cpuBufAddr <= 0;
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end
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cpuBufSel <= ~cpuAddr[15]; // address bit 15 selects buffer
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if(cpuBufAddr && !ncpuUDS) cpuUWriteReq <= 1;
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else cpuUWriteReq <= 0;
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if(cpuBufAddr && !ncpuLDS) cpuLWriteReq <= 1;
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else cpuLWriteReq <= 0;
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// VIA is in address block $E8,0000 - $EF,FFFF
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// VIA register select pins (RS[3:0]) are wired to cpuAddr[12:9]
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// VIA Output Register A is selected when RS[3:0]==$F
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/*if(!ncpuAS && !cpuRnW && !ncpuUDS
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&& cpuAddr[23] && cpuAddr[22] // VIA Address Select
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&& cpuAddr[21] && !cpuAddr[20]
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&& cpuAddr[19]
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&& cpuAddr[12] && cpuAddr[11] // VIA ORA
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&& cpuAddr[10] && cpuAddr[9]
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) cpuVIAReq <= 1;
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else cpuVIAReq <= 0;*/
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// Mac ROM addresses Data Register A as vBase+vBufA:
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// $EF,E1FE + (512*15) = $EF,FFFE
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// shift right by one because no A0 and we get $77,FFFF
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// This bit is giving me hell, so let's expand it
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if(ncpuAS==0 && cpuRnW==0 && ncpuUDS==0
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&& cpuAddr == 22'h77FFFF) cpuVIAReq <= 1;
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else cpuVIAReq <= 0;
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end
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// if there's an active CPU request and we've reached the state for servicing
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// that CPU request, then set a flag to mark that we have serviced it
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always @(posedge pixClk or posedge ncpuAS) begin
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if(ncpuAS) begin
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cpuUWriteSrv <= 0;
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cpuLWriteSrv <= 0;
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cpuVIASrv <= 0;
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end else begin
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if(ncpuAS) begin
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cpuUWriteSrv <= 0;
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cpuLWriteSrv <= 0;
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cpuVIASrv <= 0;
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end else begin
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if(cpuUWriteReq && pState == S3) cpuUWriteSrv <= 1;
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if(cpuLWriteReq && pState == S5) cpuLWriteSrv <= 1;
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if(cpuVIAReq && pState == S7) cpuVIASrv <= 1;
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end
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end
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end
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// store the video buffer selection bit
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always @(posedge pixClk or negedge nReset) begin
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if(!nReset) vidBufSel <= 0;
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// fine. no video buffer select. we use Main only.
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//else if(pState == S7) vidBufSel <= ~cpuData[14];
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end
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endmodule |