108 lines
4.0 KiB
Systemverilog
108 lines
4.0 KiB
Systemverilog
/******************************************************************************
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* SE-VGA
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* CPU Bus Snoop
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* techav
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* 2021-04-06
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******************************************************************************
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* Watches for writes to frame buffer memory addresses and copies that data
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* into VRAM
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*****************************************************************************/
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module cpusnoop (
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input wire nReset, // System Reset signal
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input wire pixClock, // 25.175MHz Pixel Clock
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input logic [2:0] sequence, // Sequence count (low 3 bits of hCount)
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input logic [23:1] cpuAddr, // CPU Address bus
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input logic [15:0] cpuData, // CPU Data bus
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input wire ncpuAS, // CPU Address Strobe signal
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input wire ncpuUDS, // CPU Upper Data Strobe signal
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input wire ncpuLDS, // CPU Lower Data Strobe signal
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input wire cpuRnW, // CPU Read/Write select signal
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input wire cpuClk, // CPU Clock
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output logic [12:0] vramAddr, // VRAM Address Bus
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inout logic [7:0] vramData, // VRAM Data Bus
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output wire nvramWE, // VRAM Write strobe
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);
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// framebuffer address (with 4MB RAM installed): 0x3FA700 - 0x3FFFFF
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wire pendWriteLo; // low byte write to VRAM pending
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wire pendWriteHi; // high byte write to VRAM pending
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logic [12:1] addrCache; // store address for cpu writes to framebuffer
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logic [7:0] dataCacheLo; // store data for cpu writes to low byte
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logic [7:0] dataCacheHi; // store data for cpu writes to high byte
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// when cpu addresses the framebuffer, save the address
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always @(negedge ncpuAS or negedge nReset) begin
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if(nReset == 1'b0) begin
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addrCache <= 16'h0;
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end else begin
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if(cpuAddr >= 24'h3FA700 && cpuAddr < 24'h400000) begin
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addrCache[12:0] <= cpuAddr - 16'hA700;
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end
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end
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end
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// when cpu addresses the framebuffer, save high byte
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always @(negedge ncpuUDS or negedge nReset) begin
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if(nReset == 1'b0) begin
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dataCacheHi <= 8'h0;
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end else begin
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if(cpuAddr >= 24'h3FA700 && cpuAddr < 24'h400000 && cpuRnW == 1'b0) begin
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dataCacheHi <= cpuData[15:8];
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end
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end
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end
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// when cpu addresses the framebuffer, save low byte
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always @(negedge ncpuUDS or negedge nReset) begin
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if(nReset == 1'b0) begin
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dataCacheLo <= 8'h0;
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end else begin
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if(cpuAddr >= 24'h3FA700 && cpuAddr < 24'h400000 && cpuRnW == 1'b0) begin
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dataCacheLo <= cpuData[7:0];
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end
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end
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end
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// set pending flags for cpu accesses & clear when that cycle comes back around
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always @(negedge pixClock or negedge nReset) begin
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if(nReset == 1'b0) begin
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pendWriteLo <= 1'b0;
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pendWriteHi <= 1'b0;
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end else begin
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if(cpuAddr >= 24'h3FA700 && cpuAddr < 24'h400000 && cpuRnW == 1'b0) begin
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if(ncpuUDS == 1'b0) begin
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pendWriteHi <= 1'b1;
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end
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if(ncpuLDS == 1'b0) begin
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pendWriteLo <= 1'b1;
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end
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end else begin
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if(sequence == 3'h1) begin
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pendWriteLo <= 1'b0;
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end
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if(sequence == 3'h2) begin
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pendWriteHi <= 1'b0;
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end
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end
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end
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end
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always_comb begin
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vramAddr[12:1] <= addrCache[12:1];
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if(pendWriteLo == 1'b1 && sequence == 3'h1) begin
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vramAddr[0] <= 1'b0;
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nvramWE <= 1'b0;
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vramData <= dataCacheLo;
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end else if(pendWriteHi == 1'b1 && sequence = 3'h2) begin
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vramAddr[0] <= 1'b1;
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nvramWE <= 1'b0;
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vramData <= dataCacheHi;
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end else begin
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vramAddr[0] <= 1'b0;
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nvramWE <= 1'b1;
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vramData <= 8'bZ;
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end
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end
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endmodule |