67 lines
1.7 KiB
Systemverilog
67 lines
1.7 KiB
Systemverilog
/******************************************************************************
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* SE-VGA
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* VGA signal counter
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* techav
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* 2021-04-06
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******************************************************************************
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* Low-level VGA signal counter
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*****************************************************************************/
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module vgacount (
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input wire nReset, // system reset signal
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input wire clock, // counter increment clock
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output logic [9:0] count, // count output
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output wire nSync, // sync pulse
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output wire activeVid, // active video signal
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output wire activeSE // secondary active video signal (SE)
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);
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parameter COUNTMAX=800,
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SYNCBEGIN=592,
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SYNCEND=688,
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ACTBEGIN=576,
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ACTEND=736,
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SEACTBEGIN=512;
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logic [9:0] counter;
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// primary counter
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always @(negedge clock or negedge nReset) begin
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if(nReset == 1'b0) begin
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counter <= 10'h0;
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end else begin
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if (counter < COUNTMAX) begin
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counter <= counter + 10'h1;
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end else begin
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counter <= 10'h0;
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end
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end
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end
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// combinatorial logic derived from the counters
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always_comb begin
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// output the count signals
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count <= counter;
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// Sync pulse
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if(hCount >= SYNCBEGIN && hCount < SYNCEND) begin
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nhSync <= 1'b0;
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end else begin
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nhSync <= 1'b1;
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end
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if(hCount >= ACTBEGIN && hCount < ACTEND) begin
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hActive <= 1'b0;
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end else begin
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hActive <= 1'b1;
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end
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if(hCount >= SEACTBEGIN) begin
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hSEActive <= 1'b0;
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end else begin
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hSEActive <= 1'b1;
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end
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end
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endmodule |