70 lines
1.7 KiB
Systemverilog
70 lines
1.7 KiB
Systemverilog
/******************************************************************************
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* SE-VGA
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* VGA video output
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* techav
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* 2021-04-06
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******************************************************************************
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* Fetches video data from VRAM and shifts out
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*****************************************************************************/
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`include "primitives.sv"
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module vgaout (
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input wire pixClock,
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input wire nReset,
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input logic [9:0] hCount,
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input logic [9:0] vCount,
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input wire hSEActive,
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input wire vSEActive,
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inout logic [7:0] vramData,
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output logic [12:0] vramAddr,
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output wire nvramOE,
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output wire vidOut
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);
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reg [7:0] rVid;
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wire vidMuxOut;
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wire vidActive; // combined active video signal
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mux8x1 vidOutMux(rVid[7:0],hCount[2:0],vidMuxOut);
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// latch incoming vram data on rising clock and sequence 7
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always @(posedge pixClock or negedge nReset) begin
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if(nReset == 1'b0) begin
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rVid <= 8'h0;
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end else begin
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if(hCount[2:0] == 3'b7) begin
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rVid <= vramData;
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end
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end
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end
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always_comb begin
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// combined video active signal
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if(hSEActive == 1'b1 && vSEActive == 1'b1) begin
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vidActive <= 1'b1;
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end else begin
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vidActive <= 1'b0;
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end
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// video data output
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if(vidActive == 1'b1) begin
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vidOut <= vidMuxOut;
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end else begin
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vidOut <= 1'b0;
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end
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// vram read signal
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if(vidActive == 1'b1 && hCount[2:0] == 3'b7) begin
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nvramOE <= 1'b0;
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end else begin
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nvramOE <= 1'b1;
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end
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// vram address signals
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// these will be mux'd with cpu addresses externally
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vramAddr[12:6] <= vCount[6:0];
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vramAddr[5:0] <= hCount[8:3];
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end
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endmodule |