115 lines
3.1 KiB
Systemverilog
115 lines
3.1 KiB
Systemverilog
/******************************************************************************
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* SE-VGA
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* VGA video output
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* techav
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* 2021-04-06
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******************************************************************************
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* Fetches video data from VRAM and shifts out
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*****************************************************************************/
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`include "primitives/primitives.sv"
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module vgaout (
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input wire pixClock,
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input wire nReset,
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input logic [9:0] hCount,
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input logic [9:0] vCount,
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input wire hSEActive,
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input wire vSEActive,
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input logic [7:0] vramData,
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output logic [14:0] vramAddr,
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output wire nvramOE,
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output wire vidOut
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);
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//reg [7:0] rVid;
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wire vidMuxOut;
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wire vidActive; // combined active video signal
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vidShiftOut vOut(
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.nReset(nReset),
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.clk(pixClock),
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.vidActive(vidActive),
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.seq(hCount[2:0]),
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.parIn(vramData),
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.out(vidMuxOut)
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);
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/*module vidShiftOut (
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input wire nReset,
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input wire clk,
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input logic [2:0] seq,
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input logic [7:0] parIn,
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output wire out,
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);*/
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/*
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wire vidMuxClk; // latch mux output just before updating rVid
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// select bits 0..7 from the vram data in rVid, and latch if
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// vidMuxClk goes high
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mux8x1latch vidOutMux(rVid,hCount[2:0],vidMuxClk,nReset,vidMuxOut);
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// vidMuxClk should be low during sequence 0..6, and high for 7
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// this may lead to a race condition trying to change the mux
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// before the output is latched. The alternative is to latch on
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// the rising edge of pixClock during sequence 7, but then we may
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// have a race condition with the data coming in from VRAM.
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// What we really need is a half clock delay :-/
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always_comb begin
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if(hCount[2:0] == 3'd7) begin
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vidMuxClk <= 1'b1;
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end else begin
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vidMuxClk <= 1'b0;
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end
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end
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*/
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// latch incoming vram data on rising clock and sequence 7
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/*always @(posedge pixClock or negedge nReset) begin
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if(nReset == 1'b0) begin
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rVid <= 8'h0;
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end else begin
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if(hCount[2:0] == 3'h7) begin
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rVid <= vramData;
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end
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end
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end*/
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always_comb begin
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// combined video active signal
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if(hSEActive == 1'b1 && vSEActive == 1'b1) begin
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vidActive <= 1'b1;
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end else if(hCount == 799 && vCount == 524) begin
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// this is the exception to ensure the first byte of video is loaded
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// just before the new frame starts
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vidActive <= 1'b1;
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end else if(vSEActive == 1'b1 && hCount == 10'd799) begin
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// this is the exception to ensure the first byte of video is loaded
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// just before a new line starts
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vidActive <= 1'b1;
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end else begin
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vidActive <= 1'b0;
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end
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// video data output
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if(vidActive == 1'b1) begin
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vidOut <= vidMuxOut;
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end else begin
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vidOut <= 1'b0;
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end
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// vram read signal
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if(vidActive == 1'b1 && hCount[2:0] == 3'h7) begin
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nvramOE <= 1'b0;
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end else begin
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nvramOE <= 1'b1;
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end
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// vram address signals
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// these will be mux'd with cpu addresses externally
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vramAddr[14:6] <= vCount[8:0];
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vramAddr[5:0] <= hCount[8:3];
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end
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endmodule |