2412 lines
32 KiB
Plaintext
2412 lines
32 KiB
Plaintext
/*
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WARNING: Do NOT edit the input and output ports in this file in a text
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editor if you plan to continue editing the block that represents it in
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the Block Editor! File corruption is VERY likely to occur.
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*/
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/*
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Copyright (C) 1991-2013 Altera Corporation
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Your use of Altera Corporation's design tools, logic functions
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and other software and tools, and its AMPP partner logic
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functions, and any output files from any of the foregoing
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(including device programming or simulation files), and any
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associated documentation or information are expressly subject
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to the terms and conditions of the Altera Program License
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Subscription Agreement, Altera MegaCore Function License
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Agreement, or other applicable license agreement, including,
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without limitation, that your use is for the sole purpose of
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programming logic devices manufactured by Altera and sold by
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Altera or its authorized distributors. Please refer to the
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applicable agreement for further details.
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*/
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HEADER
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{
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VERSION = 1;
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TIME_UNIT = ns;
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DATA_OFFSET = 0.0;
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DATA_DURATION = 33000.0;
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SIMULATION_TIME = 0.0;
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GRID_PHASE = 0.0;
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GRID_PERIOD = 10.0;
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GRID_DUTY_CYCLE = 50;
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}
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SIGNAL("cpuAddr[1]")
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{
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VALUE_TYPE = NINE_LEVEL_BIT;
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SIGNAL_TYPE = SINGLE_BIT;
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WIDTH = 1;
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LSB_INDEX = -1;
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DIRECTION = INPUT;
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PARENT = "";
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}
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SIGNAL("cpuAddr[2]")
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{
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VALUE_TYPE = NINE_LEVEL_BIT;
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SIGNAL_TYPE = SINGLE_BIT;
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WIDTH = 1;
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LSB_INDEX = -1;
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DIRECTION = INPUT;
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PARENT = "";
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}
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SIGNAL("cpuAddr[3]")
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{
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VALUE_TYPE = NINE_LEVEL_BIT;
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SIGNAL_TYPE = SINGLE_BIT;
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WIDTH = 1;
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LSB_INDEX = -1;
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DIRECTION = INPUT;
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PARENT = "";
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}
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SIGNAL("cpuAddr[4]")
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{
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VALUE_TYPE = NINE_LEVEL_BIT;
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SIGNAL_TYPE = SINGLE_BIT;
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WIDTH = 1;
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LSB_INDEX = -1;
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DIRECTION = INPUT;
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PARENT = "";
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}
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SIGNAL("cpuAddr[5]")
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{
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VALUE_TYPE = NINE_LEVEL_BIT;
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SIGNAL_TYPE = SINGLE_BIT;
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WIDTH = 1;
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LSB_INDEX = -1;
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DIRECTION = INPUT;
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PARENT = "";
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}
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SIGNAL("cpuAddr[6]")
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{
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VALUE_TYPE = NINE_LEVEL_BIT;
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SIGNAL_TYPE = SINGLE_BIT;
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WIDTH = 1;
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LSB_INDEX = -1;
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DIRECTION = INPUT;
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PARENT = "";
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}
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SIGNAL("cpuAddr[7]")
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{
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VALUE_TYPE = NINE_LEVEL_BIT;
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SIGNAL_TYPE = SINGLE_BIT;
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WIDTH = 1;
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LSB_INDEX = -1;
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DIRECTION = INPUT;
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PARENT = "";
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}
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SIGNAL("cpuAddr[8]")
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{
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VALUE_TYPE = NINE_LEVEL_BIT;
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SIGNAL_TYPE = SINGLE_BIT;
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WIDTH = 1;
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LSB_INDEX = -1;
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DIRECTION = INPUT;
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PARENT = "";
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}
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SIGNAL("cpuAddr[9]")
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{
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VALUE_TYPE = NINE_LEVEL_BIT;
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SIGNAL_TYPE = SINGLE_BIT;
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WIDTH = 1;
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LSB_INDEX = -1;
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DIRECTION = INPUT;
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PARENT = "";
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}
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SIGNAL("cpuAddr[10]")
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{
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VALUE_TYPE = NINE_LEVEL_BIT;
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SIGNAL_TYPE = SINGLE_BIT;
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WIDTH = 1;
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LSB_INDEX = -1;
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DIRECTION = INPUT;
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PARENT = "";
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}
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SIGNAL("cpuAddr[11]")
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{
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VALUE_TYPE = NINE_LEVEL_BIT;
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SIGNAL_TYPE = SINGLE_BIT;
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WIDTH = 1;
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LSB_INDEX = -1;
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DIRECTION = INPUT;
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PARENT = "";
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}
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SIGNAL("cpuAddr[12]")
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{
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VALUE_TYPE = NINE_LEVEL_BIT;
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SIGNAL_TYPE = SINGLE_BIT;
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WIDTH = 1;
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LSB_INDEX = -1;
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DIRECTION = INPUT;
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PARENT = "";
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}
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SIGNAL("cpuAddr[13]")
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{
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VALUE_TYPE = NINE_LEVEL_BIT;
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SIGNAL_TYPE = SINGLE_BIT;
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WIDTH = 1;
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LSB_INDEX = -1;
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DIRECTION = INPUT;
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PARENT = "";
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}
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SIGNAL("cpuAddr[14]")
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{
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VALUE_TYPE = NINE_LEVEL_BIT;
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SIGNAL_TYPE = SINGLE_BIT;
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WIDTH = 1;
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LSB_INDEX = -1;
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DIRECTION = INPUT;
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PARENT = "";
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}
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SIGNAL("cpuAddr[15]")
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{
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VALUE_TYPE = NINE_LEVEL_BIT;
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SIGNAL_TYPE = SINGLE_BIT;
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WIDTH = 1;
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LSB_INDEX = -1;
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DIRECTION = INPUT;
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PARENT = "";
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}
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SIGNAL("cpuAddr[16]")
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{
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VALUE_TYPE = NINE_LEVEL_BIT;
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SIGNAL_TYPE = SINGLE_BIT;
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WIDTH = 1;
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LSB_INDEX = -1;
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DIRECTION = INPUT;
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PARENT = "";
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}
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SIGNAL("cpuAddr[17]")
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{
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VALUE_TYPE = NINE_LEVEL_BIT;
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SIGNAL_TYPE = SINGLE_BIT;
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WIDTH = 1;
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LSB_INDEX = -1;
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DIRECTION = INPUT;
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PARENT = "";
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}
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SIGNAL("cpuAddr[18]")
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{
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VALUE_TYPE = NINE_LEVEL_BIT;
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SIGNAL_TYPE = SINGLE_BIT;
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WIDTH = 1;
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LSB_INDEX = -1;
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DIRECTION = INPUT;
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PARENT = "";
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}
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SIGNAL("cpuAddr[19]")
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{
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VALUE_TYPE = NINE_LEVEL_BIT;
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SIGNAL_TYPE = SINGLE_BIT;
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WIDTH = 1;
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LSB_INDEX = -1;
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DIRECTION = INPUT;
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PARENT = "";
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}
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SIGNAL("cpuAddr[20]")
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{
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VALUE_TYPE = NINE_LEVEL_BIT;
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SIGNAL_TYPE = SINGLE_BIT;
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WIDTH = 1;
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LSB_INDEX = -1;
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DIRECTION = INPUT;
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PARENT = "";
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}
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SIGNAL("cpuAddr[21]")
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{
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VALUE_TYPE = NINE_LEVEL_BIT;
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SIGNAL_TYPE = SINGLE_BIT;
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WIDTH = 1;
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LSB_INDEX = -1;
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DIRECTION = INPUT;
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PARENT = "";
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}
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SIGNAL("cpuAddr[22]")
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{
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VALUE_TYPE = NINE_LEVEL_BIT;
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SIGNAL_TYPE = SINGLE_BIT;
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WIDTH = 1;
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LSB_INDEX = -1;
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DIRECTION = INPUT;
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PARENT = "";
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}
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SIGNAL("cpuAddr[23]")
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{
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VALUE_TYPE = NINE_LEVEL_BIT;
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SIGNAL_TYPE = SINGLE_BIT;
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WIDTH = 1;
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LSB_INDEX = -1;
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DIRECTION = INPUT;
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PARENT = "";
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}
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SIGNAL("cpuClk")
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{
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VALUE_TYPE = NINE_LEVEL_BIT;
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SIGNAL_TYPE = SINGLE_BIT;
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WIDTH = 1;
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LSB_INDEX = -1;
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DIRECTION = INPUT;
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PARENT = "";
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}
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SIGNAL("cpuData")
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{
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VALUE_TYPE = NINE_LEVEL_BIT;
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SIGNAL_TYPE = BUS;
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WIDTH = 16;
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LSB_INDEX = 0;
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DIRECTION = INPUT;
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PARENT = "";
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}
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SIGNAL("cpuData[15]")
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{
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VALUE_TYPE = NINE_LEVEL_BIT;
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SIGNAL_TYPE = SINGLE_BIT;
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WIDTH = 1;
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LSB_INDEX = -1;
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DIRECTION = INPUT;
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PARENT = "cpuData";
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}
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SIGNAL("cpuData[14]")
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{
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VALUE_TYPE = NINE_LEVEL_BIT;
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SIGNAL_TYPE = SINGLE_BIT;
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WIDTH = 1;
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LSB_INDEX = -1;
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DIRECTION = INPUT;
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PARENT = "cpuData";
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}
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SIGNAL("cpuData[13]")
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{
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VALUE_TYPE = NINE_LEVEL_BIT;
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SIGNAL_TYPE = SINGLE_BIT;
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WIDTH = 1;
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LSB_INDEX = -1;
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DIRECTION = INPUT;
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PARENT = "cpuData";
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}
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SIGNAL("cpuData[12]")
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{
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VALUE_TYPE = NINE_LEVEL_BIT;
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SIGNAL_TYPE = SINGLE_BIT;
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WIDTH = 1;
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LSB_INDEX = -1;
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DIRECTION = INPUT;
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PARENT = "cpuData";
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}
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SIGNAL("cpuData[11]")
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{
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VALUE_TYPE = NINE_LEVEL_BIT;
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SIGNAL_TYPE = SINGLE_BIT;
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WIDTH = 1;
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LSB_INDEX = -1;
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DIRECTION = INPUT;
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PARENT = "cpuData";
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}
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SIGNAL("cpuData[10]")
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{
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VALUE_TYPE = NINE_LEVEL_BIT;
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SIGNAL_TYPE = SINGLE_BIT;
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WIDTH = 1;
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LSB_INDEX = -1;
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DIRECTION = INPUT;
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PARENT = "cpuData";
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}
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SIGNAL("cpuData[9]")
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{
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VALUE_TYPE = NINE_LEVEL_BIT;
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SIGNAL_TYPE = SINGLE_BIT;
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WIDTH = 1;
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LSB_INDEX = -1;
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DIRECTION = INPUT;
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PARENT = "cpuData";
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}
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SIGNAL("cpuData[8]")
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{
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VALUE_TYPE = NINE_LEVEL_BIT;
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SIGNAL_TYPE = SINGLE_BIT;
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WIDTH = 1;
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LSB_INDEX = -1;
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DIRECTION = INPUT;
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PARENT = "cpuData";
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}
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SIGNAL("cpuData[7]")
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{
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VALUE_TYPE = NINE_LEVEL_BIT;
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SIGNAL_TYPE = SINGLE_BIT;
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WIDTH = 1;
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LSB_INDEX = -1;
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DIRECTION = INPUT;
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PARENT = "cpuData";
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}
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SIGNAL("cpuData[6]")
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{
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VALUE_TYPE = NINE_LEVEL_BIT;
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SIGNAL_TYPE = SINGLE_BIT;
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WIDTH = 1;
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LSB_INDEX = -1;
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DIRECTION = INPUT;
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PARENT = "cpuData";
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}
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SIGNAL("cpuData[5]")
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{
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VALUE_TYPE = NINE_LEVEL_BIT;
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SIGNAL_TYPE = SINGLE_BIT;
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WIDTH = 1;
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LSB_INDEX = -1;
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DIRECTION = INPUT;
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PARENT = "cpuData";
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}
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SIGNAL("cpuData[4]")
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{
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VALUE_TYPE = NINE_LEVEL_BIT;
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SIGNAL_TYPE = SINGLE_BIT;
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WIDTH = 1;
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LSB_INDEX = -1;
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DIRECTION = INPUT;
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PARENT = "cpuData";
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}
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SIGNAL("cpuData[3]")
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{
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VALUE_TYPE = NINE_LEVEL_BIT;
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SIGNAL_TYPE = SINGLE_BIT;
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WIDTH = 1;
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LSB_INDEX = -1;
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DIRECTION = INPUT;
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PARENT = "cpuData";
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}
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SIGNAL("cpuData[2]")
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{
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VALUE_TYPE = NINE_LEVEL_BIT;
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SIGNAL_TYPE = SINGLE_BIT;
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WIDTH = 1;
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LSB_INDEX = -1;
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DIRECTION = INPUT;
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PARENT = "cpuData";
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}
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SIGNAL("cpuData[1]")
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{
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VALUE_TYPE = NINE_LEVEL_BIT;
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SIGNAL_TYPE = SINGLE_BIT;
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WIDTH = 1;
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LSB_INDEX = -1;
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DIRECTION = INPUT;
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PARENT = "cpuData";
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}
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SIGNAL("cpuData[0]")
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{
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VALUE_TYPE = NINE_LEVEL_BIT;
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SIGNAL_TYPE = SINGLE_BIT;
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WIDTH = 1;
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LSB_INDEX = -1;
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DIRECTION = INPUT;
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PARENT = "cpuData";
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}
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SIGNAL("cpuRnW")
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{
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VALUE_TYPE = NINE_LEVEL_BIT;
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SIGNAL_TYPE = SINGLE_BIT;
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WIDTH = 1;
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LSB_INDEX = -1;
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DIRECTION = INPUT;
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PARENT = "";
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}
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SIGNAL("nReset")
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{
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VALUE_TYPE = NINE_LEVEL_BIT;
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SIGNAL_TYPE = SINGLE_BIT;
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WIDTH = 1;
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LSB_INDEX = -1;
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DIRECTION = INPUT;
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PARENT = "";
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}
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SIGNAL("ncpuAS")
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{
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VALUE_TYPE = NINE_LEVEL_BIT;
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SIGNAL_TYPE = SINGLE_BIT;
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WIDTH = 1;
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LSB_INDEX = -1;
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DIRECTION = INPUT;
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PARENT = "";
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}
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SIGNAL("ncpuLDS")
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{
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VALUE_TYPE = NINE_LEVEL_BIT;
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SIGNAL_TYPE = SINGLE_BIT;
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WIDTH = 1;
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LSB_INDEX = -1;
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DIRECTION = INPUT;
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PARENT = "";
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}
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|
|
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SIGNAL("ncpuUDS")
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{
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VALUE_TYPE = NINE_LEVEL_BIT;
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SIGNAL_TYPE = SINGLE_BIT;
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WIDTH = 1;
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LSB_INDEX = -1;
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DIRECTION = INPUT;
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|
PARENT = "";
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}
|
|
|
|
SIGNAL("nhSync")
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|
{
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VALUE_TYPE = NINE_LEVEL_BIT;
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SIGNAL_TYPE = SINGLE_BIT;
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WIDTH = 1;
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LSB_INDEX = -1;
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DIRECTION = OUTPUT;
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PARENT = "";
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}
|
|
|
|
SIGNAL("nvSync")
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|
{
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|
VALUE_TYPE = NINE_LEVEL_BIT;
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SIGNAL_TYPE = SINGLE_BIT;
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WIDTH = 1;
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LSB_INDEX = -1;
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|
DIRECTION = OUTPUT;
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|
PARENT = "";
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|
}
|
|
|
|
SIGNAL("nvramOE")
|
|
{
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|
VALUE_TYPE = NINE_LEVEL_BIT;
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|
SIGNAL_TYPE = SINGLE_BIT;
|
|
WIDTH = 1;
|
|
LSB_INDEX = -1;
|
|
DIRECTION = OUTPUT;
|
|
PARENT = "";
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|
}
|
|
|
|
SIGNAL("nvramWE")
|
|
{
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|
VALUE_TYPE = NINE_LEVEL_BIT;
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|
SIGNAL_TYPE = SINGLE_BIT;
|
|
WIDTH = 1;
|
|
LSB_INDEX = -1;
|
|
DIRECTION = OUTPUT;
|
|
PARENT = "";
|
|
}
|
|
|
|
SIGNAL("pixClk")
|
|
{
|
|
VALUE_TYPE = NINE_LEVEL_BIT;
|
|
SIGNAL_TYPE = SINGLE_BIT;
|
|
WIDTH = 1;
|
|
LSB_INDEX = -1;
|
|
DIRECTION = INPUT;
|
|
PARENT = "";
|
|
}
|
|
|
|
SIGNAL("ramSize")
|
|
{
|
|
VALUE_TYPE = NINE_LEVEL_BIT;
|
|
SIGNAL_TYPE = BUS;
|
|
WIDTH = 3;
|
|
LSB_INDEX = 0;
|
|
DIRECTION = INPUT;
|
|
PARENT = "";
|
|
}
|
|
|
|
SIGNAL("ramSize[2]")
|
|
{
|
|
VALUE_TYPE = NINE_LEVEL_BIT;
|
|
SIGNAL_TYPE = SINGLE_BIT;
|
|
WIDTH = 1;
|
|
LSB_INDEX = -1;
|
|
DIRECTION = INPUT;
|
|
PARENT = "ramSize";
|
|
}
|
|
|
|
SIGNAL("ramSize[1]")
|
|
{
|
|
VALUE_TYPE = NINE_LEVEL_BIT;
|
|
SIGNAL_TYPE = SINGLE_BIT;
|
|
WIDTH = 1;
|
|
LSB_INDEX = -1;
|
|
DIRECTION = INPUT;
|
|
PARENT = "ramSize";
|
|
}
|
|
|
|
SIGNAL("ramSize[0]")
|
|
{
|
|
VALUE_TYPE = NINE_LEVEL_BIT;
|
|
SIGNAL_TYPE = SINGLE_BIT;
|
|
WIDTH = 1;
|
|
LSB_INDEX = -1;
|
|
DIRECTION = INPUT;
|
|
PARENT = "ramSize";
|
|
}
|
|
|
|
SIGNAL("vidOut")
|
|
{
|
|
VALUE_TYPE = NINE_LEVEL_BIT;
|
|
SIGNAL_TYPE = SINGLE_BIT;
|
|
WIDTH = 1;
|
|
LSB_INDEX = -1;
|
|
DIRECTION = OUTPUT;
|
|
PARENT = "";
|
|
}
|
|
|
|
SIGNAL("vramAddr")
|
|
{
|
|
VALUE_TYPE = NINE_LEVEL_BIT;
|
|
SIGNAL_TYPE = BUS;
|
|
WIDTH = 15;
|
|
LSB_INDEX = 0;
|
|
DIRECTION = OUTPUT;
|
|
PARENT = "";
|
|
}
|
|
|
|
SIGNAL("vramAddr[14]")
|
|
{
|
|
VALUE_TYPE = NINE_LEVEL_BIT;
|
|
SIGNAL_TYPE = SINGLE_BIT;
|
|
WIDTH = 1;
|
|
LSB_INDEX = -1;
|
|
DIRECTION = OUTPUT;
|
|
PARENT = "vramAddr";
|
|
}
|
|
|
|
SIGNAL("vramAddr[13]")
|
|
{
|
|
VALUE_TYPE = NINE_LEVEL_BIT;
|
|
SIGNAL_TYPE = SINGLE_BIT;
|
|
WIDTH = 1;
|
|
LSB_INDEX = -1;
|
|
DIRECTION = OUTPUT;
|
|
PARENT = "vramAddr";
|
|
}
|
|
|
|
SIGNAL("vramAddr[12]")
|
|
{
|
|
VALUE_TYPE = NINE_LEVEL_BIT;
|
|
SIGNAL_TYPE = SINGLE_BIT;
|
|
WIDTH = 1;
|
|
LSB_INDEX = -1;
|
|
DIRECTION = OUTPUT;
|
|
PARENT = "vramAddr";
|
|
}
|
|
|
|
SIGNAL("vramAddr[11]")
|
|
{
|
|
VALUE_TYPE = NINE_LEVEL_BIT;
|
|
SIGNAL_TYPE = SINGLE_BIT;
|
|
WIDTH = 1;
|
|
LSB_INDEX = -1;
|
|
DIRECTION = OUTPUT;
|
|
PARENT = "vramAddr";
|
|
}
|
|
|
|
SIGNAL("vramAddr[10]")
|
|
{
|
|
VALUE_TYPE = NINE_LEVEL_BIT;
|
|
SIGNAL_TYPE = SINGLE_BIT;
|
|
WIDTH = 1;
|
|
LSB_INDEX = -1;
|
|
DIRECTION = OUTPUT;
|
|
PARENT = "vramAddr";
|
|
}
|
|
|
|
SIGNAL("vramAddr[9]")
|
|
{
|
|
VALUE_TYPE = NINE_LEVEL_BIT;
|
|
SIGNAL_TYPE = SINGLE_BIT;
|
|
WIDTH = 1;
|
|
LSB_INDEX = -1;
|
|
DIRECTION = OUTPUT;
|
|
PARENT = "vramAddr";
|
|
}
|
|
|
|
SIGNAL("vramAddr[8]")
|
|
{
|
|
VALUE_TYPE = NINE_LEVEL_BIT;
|
|
SIGNAL_TYPE = SINGLE_BIT;
|
|
WIDTH = 1;
|
|
LSB_INDEX = -1;
|
|
DIRECTION = OUTPUT;
|
|
PARENT = "vramAddr";
|
|
}
|
|
|
|
SIGNAL("vramAddr[7]")
|
|
{
|
|
VALUE_TYPE = NINE_LEVEL_BIT;
|
|
SIGNAL_TYPE = SINGLE_BIT;
|
|
WIDTH = 1;
|
|
LSB_INDEX = -1;
|
|
DIRECTION = OUTPUT;
|
|
PARENT = "vramAddr";
|
|
}
|
|
|
|
SIGNAL("vramAddr[6]")
|
|
{
|
|
VALUE_TYPE = NINE_LEVEL_BIT;
|
|
SIGNAL_TYPE = SINGLE_BIT;
|
|
WIDTH = 1;
|
|
LSB_INDEX = -1;
|
|
DIRECTION = OUTPUT;
|
|
PARENT = "vramAddr";
|
|
}
|
|
|
|
SIGNAL("vramAddr[5]")
|
|
{
|
|
VALUE_TYPE = NINE_LEVEL_BIT;
|
|
SIGNAL_TYPE = SINGLE_BIT;
|
|
WIDTH = 1;
|
|
LSB_INDEX = -1;
|
|
DIRECTION = OUTPUT;
|
|
PARENT = "vramAddr";
|
|
}
|
|
|
|
SIGNAL("vramAddr[4]")
|
|
{
|
|
VALUE_TYPE = NINE_LEVEL_BIT;
|
|
SIGNAL_TYPE = SINGLE_BIT;
|
|
WIDTH = 1;
|
|
LSB_INDEX = -1;
|
|
DIRECTION = OUTPUT;
|
|
PARENT = "vramAddr";
|
|
}
|
|
|
|
SIGNAL("vramAddr[3]")
|
|
{
|
|
VALUE_TYPE = NINE_LEVEL_BIT;
|
|
SIGNAL_TYPE = SINGLE_BIT;
|
|
WIDTH = 1;
|
|
LSB_INDEX = -1;
|
|
DIRECTION = OUTPUT;
|
|
PARENT = "vramAddr";
|
|
}
|
|
|
|
SIGNAL("vramAddr[2]")
|
|
{
|
|
VALUE_TYPE = NINE_LEVEL_BIT;
|
|
SIGNAL_TYPE = SINGLE_BIT;
|
|
WIDTH = 1;
|
|
LSB_INDEX = -1;
|
|
DIRECTION = OUTPUT;
|
|
PARENT = "vramAddr";
|
|
}
|
|
|
|
SIGNAL("vramAddr[1]")
|
|
{
|
|
VALUE_TYPE = NINE_LEVEL_BIT;
|
|
SIGNAL_TYPE = SINGLE_BIT;
|
|
WIDTH = 1;
|
|
LSB_INDEX = -1;
|
|
DIRECTION = OUTPUT;
|
|
PARENT = "vramAddr";
|
|
}
|
|
|
|
SIGNAL("vramAddr[0]")
|
|
{
|
|
VALUE_TYPE = NINE_LEVEL_BIT;
|
|
SIGNAL_TYPE = SINGLE_BIT;
|
|
WIDTH = 1;
|
|
LSB_INDEX = -1;
|
|
DIRECTION = OUTPUT;
|
|
PARENT = "vramAddr";
|
|
}
|
|
|
|
SIGNAL("vramData")
|
|
{
|
|
VALUE_TYPE = NINE_LEVEL_BIT;
|
|
SIGNAL_TYPE = BUS;
|
|
WIDTH = 8;
|
|
LSB_INDEX = 0;
|
|
DIRECTION = BIDIR;
|
|
PARENT = "";
|
|
}
|
|
|
|
SIGNAL("vramData[7]")
|
|
{
|
|
VALUE_TYPE = NINE_LEVEL_BIT;
|
|
SIGNAL_TYPE = SINGLE_BIT;
|
|
WIDTH = 1;
|
|
LSB_INDEX = -1;
|
|
DIRECTION = BIDIR;
|
|
PARENT = "vramData";
|
|
}
|
|
|
|
SIGNAL("vramData[6]")
|
|
{
|
|
VALUE_TYPE = NINE_LEVEL_BIT;
|
|
SIGNAL_TYPE = SINGLE_BIT;
|
|
WIDTH = 1;
|
|
LSB_INDEX = -1;
|
|
DIRECTION = BIDIR;
|
|
PARENT = "vramData";
|
|
}
|
|
|
|
SIGNAL("vramData[5]")
|
|
{
|
|
VALUE_TYPE = NINE_LEVEL_BIT;
|
|
SIGNAL_TYPE = SINGLE_BIT;
|
|
WIDTH = 1;
|
|
LSB_INDEX = -1;
|
|
DIRECTION = BIDIR;
|
|
PARENT = "vramData";
|
|
}
|
|
|
|
SIGNAL("vramData[4]")
|
|
{
|
|
VALUE_TYPE = NINE_LEVEL_BIT;
|
|
SIGNAL_TYPE = SINGLE_BIT;
|
|
WIDTH = 1;
|
|
LSB_INDEX = -1;
|
|
DIRECTION = BIDIR;
|
|
PARENT = "vramData";
|
|
}
|
|
|
|
SIGNAL("vramData[3]")
|
|
{
|
|
VALUE_TYPE = NINE_LEVEL_BIT;
|
|
SIGNAL_TYPE = SINGLE_BIT;
|
|
WIDTH = 1;
|
|
LSB_INDEX = -1;
|
|
DIRECTION = BIDIR;
|
|
PARENT = "vramData";
|
|
}
|
|
|
|
SIGNAL("vramData[2]")
|
|
{
|
|
VALUE_TYPE = NINE_LEVEL_BIT;
|
|
SIGNAL_TYPE = SINGLE_BIT;
|
|
WIDTH = 1;
|
|
LSB_INDEX = -1;
|
|
DIRECTION = BIDIR;
|
|
PARENT = "vramData";
|
|
}
|
|
|
|
SIGNAL("vramData[1]")
|
|
{
|
|
VALUE_TYPE = NINE_LEVEL_BIT;
|
|
SIGNAL_TYPE = SINGLE_BIT;
|
|
WIDTH = 1;
|
|
LSB_INDEX = -1;
|
|
DIRECTION = BIDIR;
|
|
PARENT = "vramData";
|
|
}
|
|
|
|
SIGNAL("vramData[0]")
|
|
{
|
|
VALUE_TYPE = NINE_LEVEL_BIT;
|
|
SIGNAL_TYPE = SINGLE_BIT;
|
|
WIDTH = 1;
|
|
LSB_INDEX = -1;
|
|
DIRECTION = BIDIR;
|
|
PARENT = "vramData";
|
|
}
|
|
|
|
GROUP("cpuAddr")
|
|
{
|
|
MEMBERS = "cpuAddr[1]", "cpuAddr[2]", "cpuAddr[3]", "cpuAddr[4]", "cpuAddr[5]", "cpuAddr[6]", "cpuAddr[7]", "cpuAddr[8]", "cpuAddr[9]", "cpuAddr[10]", "cpuAddr[11]", "cpuAddr[12]", "cpuAddr[13]", "cpuAddr[14]", "cpuAddr[15]", "cpuAddr[16]", "cpuAddr[17]", "cpuAddr[18]", "cpuAddr[19]", "cpuAddr[20]", "cpuAddr[21]", "cpuAddr[22]", "cpuAddr[23]";
|
|
}
|
|
|
|
TRANSITION_LIST("cpuAddr[1]")
|
|
{
|
|
NODE
|
|
{
|
|
REPEAT = 1;
|
|
LEVEL 0 FOR 33000.0;
|
|
}
|
|
}
|
|
|
|
TRANSITION_LIST("cpuAddr[2]")
|
|
{
|
|
NODE
|
|
{
|
|
REPEAT = 1;
|
|
LEVEL 0 FOR 33000.0;
|
|
}
|
|
}
|
|
|
|
TRANSITION_LIST("cpuAddr[3]")
|
|
{
|
|
NODE
|
|
{
|
|
REPEAT = 1;
|
|
LEVEL 0 FOR 33000.0;
|
|
}
|
|
}
|
|
|
|
TRANSITION_LIST("cpuAddr[4]")
|
|
{
|
|
NODE
|
|
{
|
|
REPEAT = 1;
|
|
LEVEL 0 FOR 33000.0;
|
|
}
|
|
}
|
|
|
|
TRANSITION_LIST("cpuAddr[5]")
|
|
{
|
|
NODE
|
|
{
|
|
REPEAT = 1;
|
|
LEVEL 0 FOR 33000.0;
|
|
}
|
|
}
|
|
|
|
TRANSITION_LIST("cpuAddr[6]")
|
|
{
|
|
NODE
|
|
{
|
|
REPEAT = 1;
|
|
LEVEL 0 FOR 33000.0;
|
|
}
|
|
}
|
|
|
|
TRANSITION_LIST("cpuAddr[7]")
|
|
{
|
|
NODE
|
|
{
|
|
REPEAT = 1;
|
|
LEVEL 0 FOR 33000.0;
|
|
}
|
|
}
|
|
|
|
TRANSITION_LIST("cpuAddr[8]")
|
|
{
|
|
NODE
|
|
{
|
|
REPEAT = 1;
|
|
LEVEL 0 FOR 33000.0;
|
|
}
|
|
}
|
|
|
|
TRANSITION_LIST("cpuAddr[9]")
|
|
{
|
|
NODE
|
|
{
|
|
REPEAT = 1;
|
|
LEVEL 0 FOR 33000.0;
|
|
}
|
|
}
|
|
|
|
TRANSITION_LIST("cpuAddr[10]")
|
|
{
|
|
NODE
|
|
{
|
|
REPEAT = 1;
|
|
LEVEL 0 FOR 33000.0;
|
|
}
|
|
}
|
|
|
|
TRANSITION_LIST("cpuAddr[11]")
|
|
{
|
|
NODE
|
|
{
|
|
REPEAT = 1;
|
|
LEVEL 0 FOR 33000.0;
|
|
}
|
|
}
|
|
|
|
TRANSITION_LIST("cpuAddr[12]")
|
|
{
|
|
NODE
|
|
{
|
|
REPEAT = 1;
|
|
LEVEL 0 FOR 33000.0;
|
|
}
|
|
}
|
|
|
|
TRANSITION_LIST("cpuAddr[13]")
|
|
{
|
|
NODE
|
|
{
|
|
REPEAT = 1;
|
|
LEVEL 0 FOR 33000.0;
|
|
}
|
|
}
|
|
|
|
TRANSITION_LIST("cpuAddr[14]")
|
|
{
|
|
NODE
|
|
{
|
|
REPEAT = 1;
|
|
LEVEL 0 FOR 33000.0;
|
|
}
|
|
}
|
|
|
|
TRANSITION_LIST("cpuAddr[15]")
|
|
{
|
|
NODE
|
|
{
|
|
REPEAT = 1;
|
|
LEVEL 0 FOR 33000.0;
|
|
}
|
|
}
|
|
|
|
TRANSITION_LIST("cpuAddr[16]")
|
|
{
|
|
NODE
|
|
{
|
|
REPEAT = 1;
|
|
LEVEL 0 FOR 33000.0;
|
|
}
|
|
}
|
|
|
|
TRANSITION_LIST("cpuAddr[17]")
|
|
{
|
|
NODE
|
|
{
|
|
REPEAT = 1;
|
|
LEVEL 0 FOR 33000.0;
|
|
}
|
|
}
|
|
|
|
TRANSITION_LIST("cpuAddr[18]")
|
|
{
|
|
NODE
|
|
{
|
|
REPEAT = 1;
|
|
LEVEL 0 FOR 33000.0;
|
|
}
|
|
}
|
|
|
|
TRANSITION_LIST("cpuAddr[19]")
|
|
{
|
|
NODE
|
|
{
|
|
REPEAT = 1;
|
|
LEVEL 0 FOR 33000.0;
|
|
}
|
|
}
|
|
|
|
TRANSITION_LIST("cpuAddr[20]")
|
|
{
|
|
NODE
|
|
{
|
|
REPEAT = 1;
|
|
LEVEL 0 FOR 33000.0;
|
|
}
|
|
}
|
|
|
|
TRANSITION_LIST("cpuAddr[21]")
|
|
{
|
|
NODE
|
|
{
|
|
REPEAT = 1;
|
|
LEVEL 0 FOR 33000.0;
|
|
}
|
|
}
|
|
|
|
TRANSITION_LIST("cpuAddr[22]")
|
|
{
|
|
NODE
|
|
{
|
|
REPEAT = 1;
|
|
LEVEL 0 FOR 33000.0;
|
|
}
|
|
}
|
|
|
|
TRANSITION_LIST("cpuAddr[23]")
|
|
{
|
|
NODE
|
|
{
|
|
REPEAT = 1;
|
|
LEVEL 0 FOR 33000.0;
|
|
}
|
|
}
|
|
|
|
TRANSITION_LIST("cpuClk")
|
|
{
|
|
NODE
|
|
{
|
|
REPEAT = 1;
|
|
LEVEL 0 FOR 33000.0;
|
|
}
|
|
}
|
|
|
|
TRANSITION_LIST("cpuData[15]")
|
|
{
|
|
NODE
|
|
{
|
|
REPEAT = 1;
|
|
LEVEL 0 FOR 33000.0;
|
|
}
|
|
}
|
|
|
|
TRANSITION_LIST("cpuData[14]")
|
|
{
|
|
NODE
|
|
{
|
|
REPEAT = 1;
|
|
LEVEL 0 FOR 33000.0;
|
|
}
|
|
}
|
|
|
|
TRANSITION_LIST("cpuData[13]")
|
|
{
|
|
NODE
|
|
{
|
|
REPEAT = 1;
|
|
LEVEL 0 FOR 33000.0;
|
|
}
|
|
}
|
|
|
|
TRANSITION_LIST("cpuData[12]")
|
|
{
|
|
NODE
|
|
{
|
|
REPEAT = 1;
|
|
LEVEL 0 FOR 33000.0;
|
|
}
|
|
}
|
|
|
|
TRANSITION_LIST("cpuData[11]")
|
|
{
|
|
NODE
|
|
{
|
|
REPEAT = 1;
|
|
LEVEL 0 FOR 33000.0;
|
|
}
|
|
}
|
|
|
|
TRANSITION_LIST("cpuData[10]")
|
|
{
|
|
NODE
|
|
{
|
|
REPEAT = 1;
|
|
LEVEL 0 FOR 33000.0;
|
|
}
|
|
}
|
|
|
|
TRANSITION_LIST("cpuData[9]")
|
|
{
|
|
NODE
|
|
{
|
|
REPEAT = 1;
|
|
LEVEL 0 FOR 33000.0;
|
|
}
|
|
}
|
|
|
|
TRANSITION_LIST("cpuData[8]")
|
|
{
|
|
NODE
|
|
{
|
|
REPEAT = 1;
|
|
LEVEL 0 FOR 33000.0;
|
|
}
|
|
}
|
|
|
|
TRANSITION_LIST("cpuData[7]")
|
|
{
|
|
NODE
|
|
{
|
|
REPEAT = 1;
|
|
LEVEL 0 FOR 33000.0;
|
|
}
|
|
}
|
|
|
|
TRANSITION_LIST("cpuData[6]")
|
|
{
|
|
NODE
|
|
{
|
|
REPEAT = 1;
|
|
LEVEL 0 FOR 33000.0;
|
|
}
|
|
}
|
|
|
|
TRANSITION_LIST("cpuData[5]")
|
|
{
|
|
NODE
|
|
{
|
|
REPEAT = 1;
|
|
LEVEL 0 FOR 33000.0;
|
|
}
|
|
}
|
|
|
|
TRANSITION_LIST("cpuData[4]")
|
|
{
|
|
NODE
|
|
{
|
|
REPEAT = 1;
|
|
LEVEL 0 FOR 33000.0;
|
|
}
|
|
}
|
|
|
|
TRANSITION_LIST("cpuData[3]")
|
|
{
|
|
NODE
|
|
{
|
|
REPEAT = 1;
|
|
LEVEL 0 FOR 33000.0;
|
|
}
|
|
}
|
|
|
|
TRANSITION_LIST("cpuData[2]")
|
|
{
|
|
NODE
|
|
{
|
|
REPEAT = 1;
|
|
LEVEL 0 FOR 33000.0;
|
|
}
|
|
}
|
|
|
|
TRANSITION_LIST("cpuData[1]")
|
|
{
|
|
NODE
|
|
{
|
|
REPEAT = 1;
|
|
LEVEL 0 FOR 33000.0;
|
|
}
|
|
}
|
|
|
|
TRANSITION_LIST("cpuData[0]")
|
|
{
|
|
NODE
|
|
{
|
|
REPEAT = 1;
|
|
LEVEL 0 FOR 33000.0;
|
|
}
|
|
}
|
|
|
|
TRANSITION_LIST("cpuRnW")
|
|
{
|
|
NODE
|
|
{
|
|
REPEAT = 1;
|
|
LEVEL 0 FOR 33000.0;
|
|
}
|
|
}
|
|
|
|
TRANSITION_LIST("nReset")
|
|
{
|
|
NODE
|
|
{
|
|
REPEAT = 1;
|
|
LEVEL 1 FOR 10.0;
|
|
LEVEL 0 FOR 20.0;
|
|
LEVEL 1 FOR 32970.0;
|
|
}
|
|
}
|
|
|
|
TRANSITION_LIST("ncpuAS")
|
|
{
|
|
NODE
|
|
{
|
|
REPEAT = 1;
|
|
LEVEL 0 FOR 33000.0;
|
|
}
|
|
}
|
|
|
|
TRANSITION_LIST("ncpuLDS")
|
|
{
|
|
NODE
|
|
{
|
|
REPEAT = 1;
|
|
LEVEL 0 FOR 33000.0;
|
|
}
|
|
}
|
|
|
|
TRANSITION_LIST("ncpuUDS")
|
|
{
|
|
NODE
|
|
{
|
|
REPEAT = 1;
|
|
LEVEL 0 FOR 33000.0;
|
|
}
|
|
}
|
|
|
|
TRANSITION_LIST("nhSync")
|
|
{
|
|
NODE
|
|
{
|
|
REPEAT = 1;
|
|
LEVEL X FOR 33000.0;
|
|
}
|
|
}
|
|
|
|
TRANSITION_LIST("nvSync")
|
|
{
|
|
NODE
|
|
{
|
|
REPEAT = 1;
|
|
LEVEL X FOR 33000.0;
|
|
}
|
|
}
|
|
|
|
TRANSITION_LIST("nvramOE")
|
|
{
|
|
NODE
|
|
{
|
|
REPEAT = 1;
|
|
LEVEL X FOR 33000.0;
|
|
}
|
|
}
|
|
|
|
TRANSITION_LIST("nvramWE")
|
|
{
|
|
NODE
|
|
{
|
|
REPEAT = 1;
|
|
LEVEL X FOR 33000.0;
|
|
}
|
|
}
|
|
|
|
TRANSITION_LIST("pixClk")
|
|
{
|
|
NODE
|
|
{
|
|
REPEAT = 1;
|
|
NODE
|
|
{
|
|
REPEAT = 825;
|
|
LEVEL 0 FOR 20.0;
|
|
LEVEL 1 FOR 20.0;
|
|
}
|
|
}
|
|
}
|
|
|
|
TRANSITION_LIST("ramSize[2]")
|
|
{
|
|
NODE
|
|
{
|
|
REPEAT = 1;
|
|
LEVEL 0 FOR 33000.0;
|
|
}
|
|
}
|
|
|
|
TRANSITION_LIST("ramSize[1]")
|
|
{
|
|
NODE
|
|
{
|
|
REPEAT = 1;
|
|
LEVEL 0 FOR 33000.0;
|
|
}
|
|
}
|
|
|
|
TRANSITION_LIST("ramSize[0]")
|
|
{
|
|
NODE
|
|
{
|
|
REPEAT = 1;
|
|
LEVEL 0 FOR 33000.0;
|
|
}
|
|
}
|
|
|
|
TRANSITION_LIST("vidOut")
|
|
{
|
|
NODE
|
|
{
|
|
REPEAT = 1;
|
|
LEVEL X FOR 33000.0;
|
|
}
|
|
}
|
|
|
|
TRANSITION_LIST("vramAddr[14]")
|
|
{
|
|
NODE
|
|
{
|
|
REPEAT = 1;
|
|
LEVEL X FOR 33000.0;
|
|
}
|
|
}
|
|
|
|
TRANSITION_LIST("vramAddr[13]")
|
|
{
|
|
NODE
|
|
{
|
|
REPEAT = 1;
|
|
LEVEL X FOR 33000.0;
|
|
}
|
|
}
|
|
|
|
TRANSITION_LIST("vramAddr[12]")
|
|
{
|
|
NODE
|
|
{
|
|
REPEAT = 1;
|
|
LEVEL X FOR 33000.0;
|
|
}
|
|
}
|
|
|
|
TRANSITION_LIST("vramAddr[11]")
|
|
{
|
|
NODE
|
|
{
|
|
REPEAT = 1;
|
|
LEVEL X FOR 33000.0;
|
|
}
|
|
}
|
|
|
|
TRANSITION_LIST("vramAddr[10]")
|
|
{
|
|
NODE
|
|
{
|
|
REPEAT = 1;
|
|
LEVEL X FOR 33000.0;
|
|
}
|
|
}
|
|
|
|
TRANSITION_LIST("vramAddr[9]")
|
|
{
|
|
NODE
|
|
{
|
|
REPEAT = 1;
|
|
LEVEL X FOR 33000.0;
|
|
}
|
|
}
|
|
|
|
TRANSITION_LIST("vramAddr[8]")
|
|
{
|
|
NODE
|
|
{
|
|
REPEAT = 1;
|
|
LEVEL X FOR 33000.0;
|
|
}
|
|
}
|
|
|
|
TRANSITION_LIST("vramAddr[7]")
|
|
{
|
|
NODE
|
|
{
|
|
REPEAT = 1;
|
|
LEVEL X FOR 33000.0;
|
|
}
|
|
}
|
|
|
|
TRANSITION_LIST("vramAddr[6]")
|
|
{
|
|
NODE
|
|
{
|
|
REPEAT = 1;
|
|
LEVEL X FOR 33000.0;
|
|
}
|
|
}
|
|
|
|
TRANSITION_LIST("vramAddr[5]")
|
|
{
|
|
NODE
|
|
{
|
|
REPEAT = 1;
|
|
LEVEL X FOR 33000.0;
|
|
}
|
|
}
|
|
|
|
TRANSITION_LIST("vramAddr[4]")
|
|
{
|
|
NODE
|
|
{
|
|
REPEAT = 1;
|
|
LEVEL X FOR 33000.0;
|
|
}
|
|
}
|
|
|
|
TRANSITION_LIST("vramAddr[3]")
|
|
{
|
|
NODE
|
|
{
|
|
REPEAT = 1;
|
|
LEVEL X FOR 33000.0;
|
|
}
|
|
}
|
|
|
|
TRANSITION_LIST("vramAddr[2]")
|
|
{
|
|
NODE
|
|
{
|
|
REPEAT = 1;
|
|
LEVEL X FOR 33000.0;
|
|
}
|
|
}
|
|
|
|
TRANSITION_LIST("vramAddr[1]")
|
|
{
|
|
NODE
|
|
{
|
|
REPEAT = 1;
|
|
LEVEL X FOR 33000.0;
|
|
}
|
|
}
|
|
|
|
TRANSITION_LIST("vramAddr[0]")
|
|
{
|
|
NODE
|
|
{
|
|
REPEAT = 1;
|
|
LEVEL X FOR 33000.0;
|
|
}
|
|
}
|
|
|
|
TRANSITION_LIST("vramData[7]")
|
|
{
|
|
NODE
|
|
{
|
|
REPEAT = 1;
|
|
LEVEL Z FOR 280.0;
|
|
LEVEL 1 FOR 80.0;
|
|
LEVEL Z FOR 240.0;
|
|
LEVEL 0 FOR 80.0;
|
|
LEVEL Z FOR 240.0;
|
|
LEVEL 0 FOR 80.0;
|
|
LEVEL Z FOR 32000.0;
|
|
}
|
|
}
|
|
|
|
TRANSITION_LIST("vramData[6]")
|
|
{
|
|
NODE
|
|
{
|
|
REPEAT = 1;
|
|
LEVEL Z FOR 280.0;
|
|
LEVEL 0 FOR 80.0;
|
|
LEVEL Z FOR 240.0;
|
|
LEVEL 1 FOR 80.0;
|
|
LEVEL Z FOR 240.0;
|
|
LEVEL 0 FOR 80.0;
|
|
LEVEL Z FOR 32000.0;
|
|
}
|
|
}
|
|
|
|
TRANSITION_LIST("vramData[5]")
|
|
{
|
|
NODE
|
|
{
|
|
REPEAT = 1;
|
|
LEVEL Z FOR 280.0;
|
|
LEVEL 1 FOR 80.0;
|
|
LEVEL Z FOR 240.0;
|
|
LEVEL 0 FOR 80.0;
|
|
LEVEL Z FOR 240.0;
|
|
LEVEL 1 FOR 80.0;
|
|
LEVEL Z FOR 32000.0;
|
|
}
|
|
}
|
|
|
|
TRANSITION_LIST("vramData[4]")
|
|
{
|
|
NODE
|
|
{
|
|
REPEAT = 1;
|
|
LEVEL Z FOR 280.0;
|
|
LEVEL 0 FOR 80.0;
|
|
LEVEL Z FOR 240.0;
|
|
LEVEL 1 FOR 80.0;
|
|
LEVEL Z FOR 240.0;
|
|
LEVEL 1 FOR 80.0;
|
|
LEVEL Z FOR 32000.0;
|
|
}
|
|
}
|
|
|
|
TRANSITION_LIST("vramData[3]")
|
|
{
|
|
NODE
|
|
{
|
|
REPEAT = 1;
|
|
LEVEL Z FOR 280.0;
|
|
LEVEL 1 FOR 80.0;
|
|
LEVEL Z FOR 240.0;
|
|
LEVEL 0 FOR 80.0;
|
|
LEVEL Z FOR 240.0;
|
|
LEVEL 1 FOR 80.0;
|
|
LEVEL Z FOR 32000.0;
|
|
}
|
|
}
|
|
|
|
TRANSITION_LIST("vramData[2]")
|
|
{
|
|
NODE
|
|
{
|
|
REPEAT = 1;
|
|
LEVEL Z FOR 280.0;
|
|
LEVEL 0 FOR 80.0;
|
|
LEVEL Z FOR 240.0;
|
|
LEVEL 1 FOR 80.0;
|
|
LEVEL Z FOR 240.0;
|
|
LEVEL 1 FOR 80.0;
|
|
LEVEL Z FOR 32000.0;
|
|
}
|
|
}
|
|
|
|
TRANSITION_LIST("vramData[1]")
|
|
{
|
|
NODE
|
|
{
|
|
REPEAT = 1;
|
|
LEVEL Z FOR 280.0;
|
|
LEVEL 1 FOR 80.0;
|
|
LEVEL Z FOR 240.0;
|
|
LEVEL 0 FOR 80.0;
|
|
LEVEL Z FOR 240.0;
|
|
LEVEL 0 FOR 80.0;
|
|
LEVEL Z FOR 32000.0;
|
|
}
|
|
}
|
|
|
|
TRANSITION_LIST("vramData[0]")
|
|
{
|
|
NODE
|
|
{
|
|
REPEAT = 1;
|
|
LEVEL Z FOR 280.0;
|
|
LEVEL 0 FOR 80.0;
|
|
LEVEL Z FOR 240.0;
|
|
LEVEL 1 FOR 80.0;
|
|
LEVEL Z FOR 240.0;
|
|
LEVEL 0 FOR 80.0;
|
|
LEVEL Z FOR 32000.0;
|
|
}
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "cpuAddr";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Hexadecimal;
|
|
TREE_INDEX = 0;
|
|
TREE_LEVEL = 0;
|
|
CHILDREN = 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "cpuAddr[1]";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Hexadecimal;
|
|
TREE_INDEX = 1;
|
|
TREE_LEVEL = 1;
|
|
PARENT = 0;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "cpuAddr[2]";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Hexadecimal;
|
|
TREE_INDEX = 2;
|
|
TREE_LEVEL = 1;
|
|
PARENT = 0;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "cpuAddr[3]";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Hexadecimal;
|
|
TREE_INDEX = 3;
|
|
TREE_LEVEL = 1;
|
|
PARENT = 0;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "cpuAddr[4]";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Hexadecimal;
|
|
TREE_INDEX = 4;
|
|
TREE_LEVEL = 1;
|
|
PARENT = 0;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "cpuAddr[5]";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Hexadecimal;
|
|
TREE_INDEX = 5;
|
|
TREE_LEVEL = 1;
|
|
PARENT = 0;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "cpuAddr[6]";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Hexadecimal;
|
|
TREE_INDEX = 6;
|
|
TREE_LEVEL = 1;
|
|
PARENT = 0;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "cpuAddr[7]";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Hexadecimal;
|
|
TREE_INDEX = 7;
|
|
TREE_LEVEL = 1;
|
|
PARENT = 0;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "cpuAddr[8]";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Hexadecimal;
|
|
TREE_INDEX = 8;
|
|
TREE_LEVEL = 1;
|
|
PARENT = 0;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "cpuAddr[9]";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Hexadecimal;
|
|
TREE_INDEX = 9;
|
|
TREE_LEVEL = 1;
|
|
PARENT = 0;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "cpuAddr[10]";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Hexadecimal;
|
|
TREE_INDEX = 10;
|
|
TREE_LEVEL = 1;
|
|
PARENT = 0;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "cpuAddr[11]";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Hexadecimal;
|
|
TREE_INDEX = 11;
|
|
TREE_LEVEL = 1;
|
|
PARENT = 0;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "cpuAddr[12]";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Hexadecimal;
|
|
TREE_INDEX = 12;
|
|
TREE_LEVEL = 1;
|
|
PARENT = 0;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "cpuAddr[13]";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Hexadecimal;
|
|
TREE_INDEX = 13;
|
|
TREE_LEVEL = 1;
|
|
PARENT = 0;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "cpuAddr[14]";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Hexadecimal;
|
|
TREE_INDEX = 14;
|
|
TREE_LEVEL = 1;
|
|
PARENT = 0;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "cpuAddr[15]";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Hexadecimal;
|
|
TREE_INDEX = 15;
|
|
TREE_LEVEL = 1;
|
|
PARENT = 0;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "cpuAddr[16]";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Hexadecimal;
|
|
TREE_INDEX = 16;
|
|
TREE_LEVEL = 1;
|
|
PARENT = 0;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "cpuAddr[17]";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Hexadecimal;
|
|
TREE_INDEX = 17;
|
|
TREE_LEVEL = 1;
|
|
PARENT = 0;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "cpuAddr[18]";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Hexadecimal;
|
|
TREE_INDEX = 18;
|
|
TREE_LEVEL = 1;
|
|
PARENT = 0;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "cpuAddr[19]";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Hexadecimal;
|
|
TREE_INDEX = 19;
|
|
TREE_LEVEL = 1;
|
|
PARENT = 0;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "cpuAddr[20]";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Hexadecimal;
|
|
TREE_INDEX = 20;
|
|
TREE_LEVEL = 1;
|
|
PARENT = 0;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "cpuAddr[21]";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Hexadecimal;
|
|
TREE_INDEX = 21;
|
|
TREE_LEVEL = 1;
|
|
PARENT = 0;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "cpuAddr[22]";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Hexadecimal;
|
|
TREE_INDEX = 22;
|
|
TREE_LEVEL = 1;
|
|
PARENT = 0;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "cpuAddr[23]";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Hexadecimal;
|
|
TREE_INDEX = 23;
|
|
TREE_LEVEL = 1;
|
|
PARENT = 0;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "cpuClk";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Binary;
|
|
TREE_INDEX = 24;
|
|
TREE_LEVEL = 0;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "cpuData";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Hexadecimal;
|
|
TREE_INDEX = 25;
|
|
TREE_LEVEL = 0;
|
|
CHILDREN = 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "cpuData[15]";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Hexadecimal;
|
|
TREE_INDEX = 26;
|
|
TREE_LEVEL = 1;
|
|
PARENT = 25;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "cpuData[14]";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Hexadecimal;
|
|
TREE_INDEX = 27;
|
|
TREE_LEVEL = 1;
|
|
PARENT = 25;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "cpuData[13]";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Hexadecimal;
|
|
TREE_INDEX = 28;
|
|
TREE_LEVEL = 1;
|
|
PARENT = 25;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "cpuData[12]";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Hexadecimal;
|
|
TREE_INDEX = 29;
|
|
TREE_LEVEL = 1;
|
|
PARENT = 25;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "cpuData[11]";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Hexadecimal;
|
|
TREE_INDEX = 30;
|
|
TREE_LEVEL = 1;
|
|
PARENT = 25;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "cpuData[10]";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Hexadecimal;
|
|
TREE_INDEX = 31;
|
|
TREE_LEVEL = 1;
|
|
PARENT = 25;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "cpuData[9]";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Hexadecimal;
|
|
TREE_INDEX = 32;
|
|
TREE_LEVEL = 1;
|
|
PARENT = 25;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "cpuData[8]";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Hexadecimal;
|
|
TREE_INDEX = 33;
|
|
TREE_LEVEL = 1;
|
|
PARENT = 25;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "cpuData[7]";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Hexadecimal;
|
|
TREE_INDEX = 34;
|
|
TREE_LEVEL = 1;
|
|
PARENT = 25;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "cpuData[6]";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Hexadecimal;
|
|
TREE_INDEX = 35;
|
|
TREE_LEVEL = 1;
|
|
PARENT = 25;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "cpuData[5]";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Hexadecimal;
|
|
TREE_INDEX = 36;
|
|
TREE_LEVEL = 1;
|
|
PARENT = 25;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "cpuData[4]";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Hexadecimal;
|
|
TREE_INDEX = 37;
|
|
TREE_LEVEL = 1;
|
|
PARENT = 25;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "cpuData[3]";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Hexadecimal;
|
|
TREE_INDEX = 38;
|
|
TREE_LEVEL = 1;
|
|
PARENT = 25;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "cpuData[2]";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Hexadecimal;
|
|
TREE_INDEX = 39;
|
|
TREE_LEVEL = 1;
|
|
PARENT = 25;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "cpuData[1]";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Hexadecimal;
|
|
TREE_INDEX = 40;
|
|
TREE_LEVEL = 1;
|
|
PARENT = 25;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "cpuData[0]";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Hexadecimal;
|
|
TREE_INDEX = 41;
|
|
TREE_LEVEL = 1;
|
|
PARENT = 25;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "cpuRnW";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Binary;
|
|
TREE_INDEX = 42;
|
|
TREE_LEVEL = 0;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "nReset";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Binary;
|
|
TREE_INDEX = 43;
|
|
TREE_LEVEL = 0;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "ncpuAS";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Binary;
|
|
TREE_INDEX = 44;
|
|
TREE_LEVEL = 0;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "ncpuLDS";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Binary;
|
|
TREE_INDEX = 45;
|
|
TREE_LEVEL = 0;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "ncpuUDS";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Binary;
|
|
TREE_INDEX = 46;
|
|
TREE_LEVEL = 0;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "nhSync";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Binary;
|
|
TREE_INDEX = 47;
|
|
TREE_LEVEL = 0;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "nvSync";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Binary;
|
|
TREE_INDEX = 48;
|
|
TREE_LEVEL = 0;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "nvramOE";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Binary;
|
|
TREE_INDEX = 49;
|
|
TREE_LEVEL = 0;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "nvramWE";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Binary;
|
|
TREE_INDEX = 50;
|
|
TREE_LEVEL = 0;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "pixClk";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Binary;
|
|
TREE_INDEX = 51;
|
|
TREE_LEVEL = 0;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "ramSize";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Octal;
|
|
TREE_INDEX = 52;
|
|
TREE_LEVEL = 0;
|
|
CHILDREN = 53, 54, 55;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "ramSize[2]";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Octal;
|
|
TREE_INDEX = 53;
|
|
TREE_LEVEL = 1;
|
|
PARENT = 52;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "ramSize[1]";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Octal;
|
|
TREE_INDEX = 54;
|
|
TREE_LEVEL = 1;
|
|
PARENT = 52;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "ramSize[0]";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Octal;
|
|
TREE_INDEX = 55;
|
|
TREE_LEVEL = 1;
|
|
PARENT = 52;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "vidOut";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Binary;
|
|
TREE_INDEX = 56;
|
|
TREE_LEVEL = 0;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "vramAddr";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Hexadecimal;
|
|
TREE_INDEX = 57;
|
|
TREE_LEVEL = 0;
|
|
CHILDREN = 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "vramAddr[14]";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Hexadecimal;
|
|
TREE_INDEX = 58;
|
|
TREE_LEVEL = 1;
|
|
PARENT = 57;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "vramAddr[13]";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Hexadecimal;
|
|
TREE_INDEX = 59;
|
|
TREE_LEVEL = 1;
|
|
PARENT = 57;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "vramAddr[12]";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Hexadecimal;
|
|
TREE_INDEX = 60;
|
|
TREE_LEVEL = 1;
|
|
PARENT = 57;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "vramAddr[11]";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Hexadecimal;
|
|
TREE_INDEX = 61;
|
|
TREE_LEVEL = 1;
|
|
PARENT = 57;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "vramAddr[10]";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Hexadecimal;
|
|
TREE_INDEX = 62;
|
|
TREE_LEVEL = 1;
|
|
PARENT = 57;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "vramAddr[9]";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Hexadecimal;
|
|
TREE_INDEX = 63;
|
|
TREE_LEVEL = 1;
|
|
PARENT = 57;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "vramAddr[8]";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Hexadecimal;
|
|
TREE_INDEX = 64;
|
|
TREE_LEVEL = 1;
|
|
PARENT = 57;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "vramAddr[7]";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Hexadecimal;
|
|
TREE_INDEX = 65;
|
|
TREE_LEVEL = 1;
|
|
PARENT = 57;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "vramAddr[6]";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Hexadecimal;
|
|
TREE_INDEX = 66;
|
|
TREE_LEVEL = 1;
|
|
PARENT = 57;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "vramAddr[5]";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Hexadecimal;
|
|
TREE_INDEX = 67;
|
|
TREE_LEVEL = 1;
|
|
PARENT = 57;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "vramAddr[4]";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Hexadecimal;
|
|
TREE_INDEX = 68;
|
|
TREE_LEVEL = 1;
|
|
PARENT = 57;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "vramAddr[3]";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Hexadecimal;
|
|
TREE_INDEX = 69;
|
|
TREE_LEVEL = 1;
|
|
PARENT = 57;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "vramAddr[2]";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Hexadecimal;
|
|
TREE_INDEX = 70;
|
|
TREE_LEVEL = 1;
|
|
PARENT = 57;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "vramAddr[1]";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Hexadecimal;
|
|
TREE_INDEX = 71;
|
|
TREE_LEVEL = 1;
|
|
PARENT = 57;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "vramAddr[0]";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Hexadecimal;
|
|
TREE_INDEX = 72;
|
|
TREE_LEVEL = 1;
|
|
PARENT = 57;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "vramData";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Hexadecimal;
|
|
TREE_INDEX = 73;
|
|
TREE_LEVEL = 0;
|
|
CHILDREN = 74, 75, 76, 77, 78, 79, 80, 81;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "vramData[7]";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Hexadecimal;
|
|
TREE_INDEX = 74;
|
|
TREE_LEVEL = 1;
|
|
PARENT = 73;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "vramData[6]";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Hexadecimal;
|
|
TREE_INDEX = 75;
|
|
TREE_LEVEL = 1;
|
|
PARENT = 73;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "vramData[5]";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Hexadecimal;
|
|
TREE_INDEX = 76;
|
|
TREE_LEVEL = 1;
|
|
PARENT = 73;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "vramData[4]";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Hexadecimal;
|
|
TREE_INDEX = 77;
|
|
TREE_LEVEL = 1;
|
|
PARENT = 73;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "vramData[3]";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Hexadecimal;
|
|
TREE_INDEX = 78;
|
|
TREE_LEVEL = 1;
|
|
PARENT = 73;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "vramData[2]";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Hexadecimal;
|
|
TREE_INDEX = 79;
|
|
TREE_LEVEL = 1;
|
|
PARENT = 73;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "vramData[1]";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Hexadecimal;
|
|
TREE_INDEX = 80;
|
|
TREE_LEVEL = 1;
|
|
PARENT = 73;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "vramData[0]";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Hexadecimal;
|
|
TREE_INDEX = 81;
|
|
TREE_LEVEL = 1;
|
|
PARENT = 73;
|
|
}
|
|
|
|
TIME_BAR
|
|
{
|
|
TIME = 0;
|
|
MASTER = TRUE;
|
|
}
|
|
;
|