245 lines
12 KiB
Systemverilog
245 lines
12 KiB
Systemverilog
/******************************************************************************
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* SE-VGA
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* CPU Bus Snoop
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* techav
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* 2021-04-06
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******************************************************************************
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* Watches for writes to frame buffer memory addresses and copies that data
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* into VRAM
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*****************************************************************************/
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module cpusnoop (
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input wire nReset, // System Reset signal
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input wire pixClock, // 25.175MHz Pixel Clock
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input logic [2:0] seq, // Sequence count (low 3 bits of hCount)
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input logic [22:0] cpuAddr, // CPU Address bus
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input logic [15:0] cpuData, // CPU Data bus
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input wire ncpuAS, // CPU Address Strobe signal
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input wire ncpuUDS, // CPU Upper Data Strobe signal
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input wire ncpuLDS, // CPU Lower Data Strobe signal
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input wire cpuRnW, // CPU Read/Write select signal
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input wire cpuClk, // CPU Clock
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output logic [14:0] vramAddr, // VRAM Address Bus
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output logic [7:0] vramDataOut,// VRAM Data Bus Output
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output wire nvramWE, // VRAM Write strobe
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output wire nvramCE0, // VRAM Main select
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output wire nvramCE1, // VRAM Alt select
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output wire vidBufSelOut,// VRAM Video Buffer selection
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input logic [2:0] ramSize // CPU RAM size selection
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);
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wire pendWriteLo; // low byte write to VRAM pending
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wire pendWriteHi; // high byte write to VRAM pending
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logic [13:0] addrCache; // store address for cpu writes to framebuffer
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logic [7:0] dataCacheLo; // store data for cpu writes to low byte
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logic [7:0] dataCacheHi; // store data for cpu writes to high byte
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wire cpuBufSel; // is CPU accessing frame buffer?
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logic [2:0] cycleState; // state machine state
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reg cpuCycleEnded; // mark cpu has ended its cycle
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reg cpuCycleBufSel; // which frame buffer was selected for the cpu cycle
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reg vidBufSel; // which frame buffer was selected for video output
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// define state machine states
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parameter
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S0 = 0,
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S1 = 1,
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S2 = 2,
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S3 = 3,
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S4 = 4,
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S5 = 5;
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// when cpu addresses the framebuffer, set our enable signal
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/* Main framebuffer starts $5900 below the top of RAM, alt frame buffer is
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* $8000 below the main frame buffer
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* ramSize is used to mask the CPU Address bits [21:19] to select the amount
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* of memory installed in the computer. Not all possible ramSize selections
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* are valid memory sizes when using 30-pin SIMMs in the Mac SE.
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* They may be possible using PDS RAM expansion cards.
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* ramSize mainBuffer altBuffer ramTop+1 ramSize Valid? Installed SIMMs
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* $7 $3fa700 $3f2700 $400000 4.0MB Y [ 1MB 1MB ][ 1MB 1MB ]
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* $6 $37a700 $372700 $380000 3.5MB N
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* $5 $2fa700 $2f2700 $300000 3.0MB N
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* $4 $27a700 $272700 $280000 2.5MB Y [ 1MB 1MB ][256kB 256kB]
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* $3 $1fa700 $1f2700 $200000 2.0MB Y [ 1MB 1MB ][ --- --- ]
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* $2 $17a700 $172700 $180000 1.5MB N
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* $1 $0fa700 $0f2700 $100000 1.0MB Y [256kB 256kB][256kB 256kB]
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* $0 $07a700 $072700 $080000 0.5MB Y [256kB 256kB][ --- --- ]
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*/
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always_comb begin
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// remember cpuAddr is shifted right by one since 68000 does not output A0
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if(cpuAddr[22:21] == 2'b00 // initial constant
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&& ramSize == cpuAddr[20:18] // ram size selection
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&& cpuAddr[17:15] == 3'b111 // trailing constant
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// next bit is main/alt select
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&& (cpuAddr[13:0] >= 14'h1380 // bottom of buffer range (0x2700>>1)
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&& cpuAddr[13:0] <= 14'h3e3f) // top of buffer range (0x7C70>>1)
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) begin
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cpuBufSel <= 1'b1;
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end else begin
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cpuBufSel <= 1'b0;
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end
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end
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// keep an eye out for cpu ending its cycle
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always @(negedge pixClock or negedge nReset) begin
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if(!nReset) cpuCycleEnded <= 0;
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else if(cycleState == S2) cpuCycleEnded <= 0;
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else if(ncpuUDS && ncpuLDS
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&& (cycleState == S3
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|| cycleState == S4
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|| cycleState == S5
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|| cycleState == S1)
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) begin
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cpuCycleEnded <= 1;
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end else cpuCycleEnded <= cpuCycleEnded;
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end
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// CPU Write to VRAM state machine
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always @(negedge pixClock or negedge nReset) begin
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if(!nReset) begin
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cycleState <= S0;
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pendWriteHi <= 0;
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pendWriteLo <= 0;
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addrCache <= 0;
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dataCacheHi <= 0;
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dataCacheLo <= 0;
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end else begin
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case (cycleState)
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S0 : begin
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// idle state, wait for valid address and ncpuAS asserted
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if(ncpuAS == 0
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&& cpuBufSel == 1
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&& cpuRnW == 0
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&& (ncpuLDS == 0
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|| ncpuUDS == 0)) begin
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pendWriteHi <= !ncpuUDS;
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pendWriteLo <= !ncpuLDS;
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dataCacheHi <= cpuData[15:8];
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dataCacheLo <= cpuData[7:0];
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// Valid CPU-VRAM cycle, so subtract constant $1380 from the
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// cpu address and store the result in addrCache register.
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// Constant $1380 corresponds to $2700 shifted right by 1.
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// Once the selection bits above are masked out, we're left
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// with buffer addresses starting at $2700
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// e.g. with 4MB of RAM, fram buffer starts at $3FA700
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// buffer address: 0011 1111 1010 0111 0000 0000 = $3FA700
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// vram addr mask: 0000 0000 0011 1111 1111 1111 - $003FFF
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// vram address: 0000 0000 0010 0111 0000 0000 = $002700
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// Since CPU is 16-bit and does not provide A0, our cpuAddr
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// signals are shifted right by one, so we need to do the same
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// to our offset before subtracting it from cpuAddr
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// offset: 0000 0000 0010 0111 0000 0000 = $002700
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// shifted offset: 0000 0000 0001 0011 1000 0000 = $001380
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addrCache <= cpuAddr[13:0] - 14'h1380;
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// The next address bit selects which frame buffer the CPU
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// is writing to for this cycle. 1 = Main ; 0 = Alt
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// Invert & save for later
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cpuCycleBufSel <= !cpuAddr[14];
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cycleState <= S2;
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end else if(ncpuAS == 0
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&& cpuRnW == 0
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&& ncpuUDS == 0
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&& cpuAddr[22:18] == 5'h1D
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&& cpuAddr[11:7] == 5'h1F) begin
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// the CPU is addressing VIA Port A. We need to check what
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// bit 6 is set to to determine which buffer is selected
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// for video output. 1 = Main ; 0 = Alt
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vidBufSel <= !cpuData[14];
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// now that we've saved the buffer selection, go to state
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// S5 to wait for the CPU to end the bus cycle.
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cycleState <= S5;
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end else begin
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cycleState <= S0;
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end
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end
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S2 : begin
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// wait for sequence
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if(pendWriteLo && !seq[0]) cycleState <= S3;
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else if (pendWriteHi && !seq[0]) cycleState <= S4;
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else if (!pendWriteHi && !pendWriteLo) cycleState <= S0; // in case something weird happens
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else cycleState <= S2;
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end
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S3 : begin
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// write CPU low byte to VRAM
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if (seq == 0) begin
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cycleState <= S3; // we shouldn't be here during a read cycle, so delay
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end else if(pendWriteHi == 1) begin
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cycleState <= S1; // move on to delay before second write cycle
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end else begin
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cycleState <= S5;
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end
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pendWriteLo <= 0;
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end
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S4 : begin
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// write CPU high byte to VRAM
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if (seq == 0) begin
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cycleState <= S4; // we shouldn't be here during a read cycle, so delay
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end else begin
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cycleState <= S5;
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end
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pendWriteHi <= 0;
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end
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S5 : begin
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// wait for CPU to negate both ncpuUDS and ncpuLDS
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if(cpuCycleEnded == 1) begin
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cycleState <= S0;
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end else begin
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cycleState <= S5;
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end
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end
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S1 : begin
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// delay moving to second write cycle
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if (!seq[0]) cycleState <= S4;
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else cycleState <= S1;
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end
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default: begin
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// how did we end up here? reset to S0
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cycleState <= S0;
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end
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endcase
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end
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end
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always_comb begin
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// output VRAM address
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// we actually do an endian swap here assigning the low-order bit of
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// the VRAM address because the video shift register in the SE loads
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// a full 16-bit word and shifts out starting with the MSB.
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// An endian swap here ensures that when we load the VRAM for output
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// the bits are in the right order.
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vramAddr[14:1] <= addrCache[13:0];
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if(cycleState == S4) begin
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vramAddr[0] <= 0;
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end else begin
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vramAddr[0] <= 1;
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end
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// Assert VRAM Write signal during CPU Cycle states S3 & S4
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// Also assert VRAM chip enable signals based on which buffer the CPU
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// addressed for the VRAM write cycle
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if(seq != 0 && (cycleState == S3 || cycleState == S4)) begin
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nvramWE <= 0;
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nvramCE0 <= cpuCycleBufSel;
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nvramCE1 <= !cpuCycleBufSel;
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end else begin
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nvramWE <= 1;
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nvramCE0 <= 1;
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nvramCE1 <= 1;
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end
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// Output our internal data cache registers on CPU Cycle states S3 & S4
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// Otherwise, just output 0. This will be muxed for the VRAM data bus
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// in the next module outside of here.
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if(cycleState == S3) begin
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vramDataOut <= dataCacheLo;
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end else if(cycleState == S4) begin
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vramDataOut <= dataCacheHi;
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end else begin
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vramDataOut <= 0;
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end
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end
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assign vidBufSelOut = vidBufSel;
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endmodule |