229 lines
7.2 KiB
Systemverilog
229 lines
7.2 KiB
Systemverilog
/******************************************************************************
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* SE-VGA
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* Top-level module
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* techav
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* 2021-10-16
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******************************************************************************
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* Trying again again again
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*****************************************************************************/
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module sevga (
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input wire nReset, // System reset signal
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input wire pixClk, // 65MHz pixel clock
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output reg nhSync, // HSync signal
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output reg nvSync, // VSync signal
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output reg vidOut, // 1-bit Monochrome video signal
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output logic [14:0] vramAddr, // VRAM Address bus
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inout logic [7:0] vramData, // VRAM Data bus
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output reg nvramOE, // VRAM Read strobe
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output reg nvramWE, // VRAM Write strobe
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output reg nvramCE0, // VRAM Main chip select signal
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output reg nvramCE1, // VRAM Alt chip select signal
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input wire [23:1] cpuAddr, // CPU Address bus
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input wire [15:0] cpuData, // CPU Data bus
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input wire ncpuAS, // CPU Address Strobe signal
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input wire ncpuUDS, // CPU Upper Data Strobe signal
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input wire ncpuLDS, // CPU Lower Data Strobe signal
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input wire cpuRnW, // CPU Read/Write select signal
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input logic [2:0] ramSize // Select installed RAM size
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);
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/******************************************************************************
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* Initial Video Signal Timing
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* The following functions establish the basic XGA signal timing and
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* assert the horizontal and vertical sync signals as appropriate.
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* These functions are the minimum required for a signal presence detect test.
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*****************************************************************************/
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// Primary sync counters
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logic [10:0] hCount; // 0..1343
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logic [9:0] vCount; // 0..805
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always @(negedge pixClk) begin
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if(hCount < 1343) hCount <= hCount + 11'h1;
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else begin
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hCount <= 0;
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if(vCount <= 805) vCount <= vCount + 10'h1;
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else vCount <= 0;
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end
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end
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// Horizontal sync
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always @(negedge pixClk) begin
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if(hCount == 0) nhSync <= 1;
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else if(hCount == 1052) nhSync <= 0;
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else if(hCount == 1186) nhSync <= 1;
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end
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// Vertical sync
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always @(negedge pixClk) begin
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if(vCount == 0) nvSync <= 1;
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else if(vCount == 729) nvSync <= 0;
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else if(vCount == 734) nvSync <= 0;
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end
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/******************************************************************************
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* Useful signals
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* Here we break out a few useful signals, derived from the timing above, that
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* will help us elsewhere.
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*****************************************************************************/
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// Horizontal active
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reg hActive;
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always @(negedge pixClk) begin
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if(hCount == 0) hActive <= 1;
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else if(hCount == 1023) hActive <= 0;
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else if(hCount == 1343) hActive <= 1;
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end
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// Vertical active
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reg vActive;
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always @(negedge pixClk) begin
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if(vCount == 0) vActive <= 1;
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else if(vCount == 683) vActive <= 0;
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else if(vCount == 805) vActive <= 1;
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end
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// Horizontal fetch active
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// asserted just before active video to enable video data pre-fetch
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reg fhActive;
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always @(negedge pixClk) begin
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if(hCount == 0) fhActive <= 1;
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else if(hCount == 1022) fhActive <= 0;
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else if(hCount == 1342) fhActive <= 1;
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end
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// Vertical fetch active
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//
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reg fvActive;
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always @(negedge pixClk) begin
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if(vCount == 0) fvActive <= 1;
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else if(vCount == 684) fvActive <= 0;
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if(vCount == 805) fvActive <= 1;
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end
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// combined active signals
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wire vidActive = hActive & vActive;
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wire fetchActive = fhActive & fvActive;
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/******************************************************************************
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* VRAM State Machine
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* Coordinates VRAM load/store actions
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*****************************************************************************/
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// rising edge signals: nvramWE, nvramOE, nvramCE[1:0]
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// falling edge signals: vramAddr, vramData
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// VRAM read signal
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//always @(posedge pixClk) begin nvramOE <= ~(hCount == 7); end
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// VRAM write signal
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always @(posedge pixClk) begin
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if(hCount[3:1] == 0) nvramWE <= 1;
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else if(hCount[3:1] == 1) nvramWE <= 0;
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else if(hCount[3:1] == 6) nvramWE <= 1;
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end
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// VRAM data/address busses
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always @(negedge pixClk) begin
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if(hCount[0] && !hCount[1]) begin
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case(hCount[3:2])
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3: begin
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// start read cycle
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vramData <= 8'hZ;
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vramAddr[14:6] <= vCount[9:1];
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vramAddr[5:0] <= hCount[9:4];
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end
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default: begin
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// write slots
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vramAddr[14:1] <= cpuAddr[14:1] - 14'h1380;
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if(!ncpuUDSr && !cpuLDSsrv) begin
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vramAddr[0] <= 0;
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vramData <= cpuData[15:8];
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end else if(!ncpuLDSr && !cpuLDSsrv) begin
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vramAddr[0] <= 1;
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vramData <= cpuData[7:0];
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end
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end
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endcase
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end
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end
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// VRAM chip enable signals
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reg cpuUDSsrv, cpuLDSsrv;
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always @(posedge pixClk) begin
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if(hCount[3:1] == 7 && fetchActive) begin
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nvramCE0 <= vidBufSel;
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nvramCE1 <= ~vidBufSel;
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nvramOE <= 0;
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end else if(!hCount[0] && hCount[1]) begin
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// write cycle
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if(!ncpuUDSr && !cpuUDSsrv) begin
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nvramCE0 <= ~cpuAddr[15];
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nvramCE1 <= cpuAddr[15];
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cpuUDSsrv <= 1;
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end else if(!ncpuLDSr && !cpuLDSsrv) begin
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nvramCE0 <= ~cpuAddr[15];
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nvramCE1 <= cpuAddr[15];
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cpuLDSsrv <= 1;
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end else begin
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nvramCE0 <= 1;
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nvramCE1 <= 1;
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end
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nvramOE <= 1;
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end else begin
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nvramCE0 <= 1;
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nvramCE1 <= 1;
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nvramOE <= 1;
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end
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// reset the upper/lower serve signals when cycle ended by CPU
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if(ncpuLDS) cpuLDSsrv <= 0;
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if(ncpuUDS) cpuUDSsrv <= 0;
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end
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// Video data shift register & output
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reg [7:0] vidShiftr;
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always @(negedge pixClk) begin
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if(hCount[3:0] == 4'hF) vidShiftr <= ~vramData;
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else if(hCount[0]) begin
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vidShiftr[7:1] <= vidShiftr[6:0];
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vidShiftr[0] <= 0;
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end
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end
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always_comb begin
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if(vidActive) vidOut = vidShiftr[7];
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else vidOut <= 0;
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end
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/******************************************************************************
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* CPU Bus Snooping
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* Watches the CPU bus and aligns its operations with the pixel clock
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*****************************************************************************/
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reg ncpuUDSr, ncpuLDSr;
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always @(negedge pixClk) begin
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// this condition evaluates true when cpu is writing to video buffer
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if(!ncpuAS && !cpuRnW
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&& !cpuAddr[23] && !cpuAddr[22]
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&& !(cpuAddr[21] ^ ramSize[2])
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&& !(cpuAddr[20] ^ ramSize[1])
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&& !(cpuAddr[19] ^ ramSize[0])
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&& cpuAddr[18] && cpuAddr[17]
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&& cpuAddr[16]
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&& ((cpuAddr[14:1] >= 14'h1380)
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&& (cpuAddr[14:1] < 14'h3E40)))
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begin
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if(!ncpuUDS) ncpuUDSr <= 0;
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else ncpuUDSr <= 1;
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if(!ncpuLDS) ncpuLDSr <= 0;
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else ncpuLDSr <= 1;
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end else begin
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ncpuUDSr <= 1;
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ncpuLDSr <= 1;
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end
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end
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// hold low for now
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reg vidBufSel = 0;
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endmodule |