76 lines
2.6 KiB
Systemverilog
76 lines
2.6 KiB
Systemverilog
/******************************************************************************
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* SE-VGA
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* VGA Output Test
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* techav
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* 2021-05-14
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******************************************************************************
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* Test configuration for testily testing testy test hardware.
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* This is not a part of the actual configuration. It is a separate top-level
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* entity for testing modules and hardware. Outputs a 512x342 pixel window of
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* alternating black and white pixels in a 640x480 resolution screen.
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*****************************************************************************/
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// all the same I's and O's as our proper configuration
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module vgatest (
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input wire nReset, // System reset signal
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input wire pixClk, // 25.175MHz pixel clock
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output wire nhSync, // HSync signal
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output wire nvSync, // VSync signal
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output wire vidOut, // 1-bit Monochrome video signal
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output logic [14:0] vramAddr, // VRAM Address bus
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//inout logic [7:0] vramData, // VRAM Data bus
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input logic [7:0] vramData,
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output wire nvramOE, // VRAM Read strobe
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output wire nvramWE, // VRAM Write strobe
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output wire nvramCE0, // VRAM Main chip select signal
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output wire nvramCE1, // VRAM Alt chip select signal
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input logic [23:1] cpuAddr, // CPU Address bus
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//input logic [15:0] cpuData, // CPU Data bus
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output logic [15:0] cpuData,
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input wire ncpuAS, // CPU Address Strobe signal
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input wire ncpuUDS, // CPU Upper Data Strobe signal
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input wire ncpuLDS, // CPU Lower Data Strobe signal
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input wire cpuRnW, // CPU Read/Write select signal
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input logic [2:0] ramSize // Select installed RAM size
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);
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logic [9:0] hCount, vCount;
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wire hActive, hSEActive;
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wire vActive, vSEActive;
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vgagen vgatiming(
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.nReset(nReset),
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.pixClk(pixClk),
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.hCount(hCount),
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.hActive(hActive),
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.hSEActive(hSEActive),
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.nhSync(nhSync),
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.vCount(vCount),
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.vActive(vActive),
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.vSEActive(vSEActive),
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.nvSync(nvSync)
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);
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reg outTog;
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always @(negedge pixClk or negedge nReset) begin
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if(nReset == 0) begin
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outTog <= 0;
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end else begin
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outTog <= !outTog;
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end
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end
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assign vidOut = outTog & hSEActive & vSEActive;
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assign vramAddr = 0;
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assign nvramOE = 1;
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assign nvramWE = 1;
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assign nvramCE0 = 1;
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assign nvramCE1 = 1;
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assign cpuData[7:0] = ~vramData;
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assign cpuData[15:8] = vramData;
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endmodule
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