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< HTML > < HEAD > < TITLE > Xilinx Design Summary< / TITLE > < / HEAD >
< BODY TEXT = '#000000' BGCOLOR = '#FFFFFF' LINK = '#0000EE' VLINK = '#551A8B' ALINK = '#FF0000' >
< TABLE BORDER CELLSPACING = 0 CELLPADDING = 3 WIDTH = '100%' >
< TR ALIGN = CENTER BGCOLOR = '#99CCFF' >
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< TD ALIGN = CENTER COLSPAN = '4' > < B > WarpLC Project Status (10/29/2021 - 17:59:59)< / B > < / TD > < / TR >
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< TR ALIGN = LEFT >
< TD BGCOLOR = '#FFFF99' > < B > Project File:< / B > < / TD >
< TD > WarpLC.xise< / TD >
< TD BGCOLOR = '#FFFF99' > < b > Parser Errors:< / b > < / TD >
< TD > No Errors < / TD >
< / TR >
< TR ALIGN = LEFT >
< TD BGCOLOR = '#FFFF99' > < B > Module Name:< / B > < / TD >
< TD > WarpLC< / TD >
< TD BGCOLOR = '#FFFF99' > < B > Implementation State:< / B > < / TD >
< TD > Placed and Routed< / TD >
< / TR >
< TR ALIGN = LEFT >
< TD BGCOLOR = '#FFFF99' > < B > Target Device:< / B > < / TD >
< TD > xc6slx9-2ftg256< / TD >
< TD BGCOLOR = '#FFFF99' > < UL > < LI > < B > Errors:< / B > < / LI > < / UL > < / TD >
< TD >
No Errors< / TD >
< / TR >
< TR ALIGN = LEFT >
< TD BGCOLOR = '#FFFF99' > < B > Product Version:< / B > < / TD > < TD > ISE 14.7< / TD >
< TD BGCOLOR = '#FFFF99' > < UL > < LI > < B > Warnings:< / B > < / LI > < / UL > < / TD >
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< TD ALIGN = LEFT > < A HREF_DISABLED = 'C:/Users/zanek/Documents/GitHub/Warp-LC/fpga\_xmsgs/*.xmsgs?&DataKey=Warning' > 7 Warnings (0 new)< / A > < / TD >
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< / TR >
< TR ALIGN = LEFT >
< TD BGCOLOR = '#FFFF99' > < B > Design Goal:< / B > < / dif > < / TD >
< TD > Balanced< / TD >
< TD BGCOLOR = '#FFFF99' > < UL > < LI > < B > Routing Results:< / B > < / LI > < / UL > < / TD >
< TD >
< A HREF_DISABLED = 'C:/Users/zanek/Documents/GitHub/Warp-LC/fpga\WarpLC.unroutes' > All Signals Completely Routed< / A > < / TD >
< / TR >
< TR ALIGN = LEFT >
< TD BGCOLOR = '#FFFF99' > < B > Design Strategy:< / B > < / dif > < / TD >
< TD > < A HREF_DISABLED = 'Xilinx Default (unlocked)?&DataKey=Strategy' > Xilinx Default (unlocked)< / A > < / TD >
< TD BGCOLOR = '#FFFF99' > < UL > < LI > < B > Timing Constraints:< / B > < / LI > < / UL > < / TD >
< TD >
< A HREF_DISABLED = 'C:/Users/zanek/Documents/GitHub/Warp-LC/fpga\WarpLC.ptwx?&DataKey=ConstraintsData' > All Constraints Met< / A > < / TD >
< / TR >
< TR ALIGN = LEFT >
< TD BGCOLOR = '#FFFF99' > < B > Environment:< / B > < / dif > < / TD >
< TD >
< A HREF_DISABLED = 'C:/Users/zanek/Documents/GitHub/Warp-LC/fpga\WarpLC_envsettings.html' >
System Settings< / A >
< / TD >
< TD BGCOLOR = '#FFFF99' > < UL > < LI > < B > Final Timing Score:< / B > < / LI > < / UL > < / TD >
< TD > 0 < A HREF_DISABLED = 'C:/Users/zanek/Documents/GitHub/Warp-LC/fpga\WarpLC.twx?&DataKey=XmlTimingReport' > (Timing Report)< / A > < / TD >
< / TR >
< / TABLE >
< BR > < TABLE BORDER CELLSPACING = 0 CELLPADDING = 3 WIDTH = '100%' >
< TR ALIGN = CENTER BGCOLOR = '#99CCFF' > < TD ALIGN = CENTER COLSPAN = '5' > < B > Device Utilization Summary< / B > < / TD > < TD ALIGN = RIGHT WIDTH = '10%' COLSPAN = 1 > < A HREF_DISABLED = "?&ExpandedTable=DeviceUtilizationSummary" > < B > [-]< / B > < / a > < / TD > < / TR >
< TR ALIGN = CENTER BGCOLOR = '#FFFF99' >
< TD ALIGN = LEFT > < B > Slice Logic Utilization< / B > < / TD > < TD > < B > Used< / B > < / TD > < TD > < B > Available< / B > < / TD > < TD > < B > Utilization< / B > < / TD > < TD COLSPAN = '2' > < B > Note(s)< / B > < / TD >
< / TR >
< TR ALIGN = RIGHT > < TD ALIGN = LEFT > Number of Slice Registers< / TD >
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< TD ALIGN = RIGHT > 34< / TD >
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< TD ALIGN = RIGHT > 11,440< / TD >
< TD ALIGN = RIGHT > 1%< / TD >
< TD COLSPAN = '2' > < / TD >
< / TR >
< TR ALIGN = RIGHT > < TD ALIGN = LEFT > Number used as Flip Flops< / TD >
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< TD ALIGN = RIGHT > 34< / TD >
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< TD > < / TD >
< TD > < / TD >
< TD COLSPAN = '2' > < / TD >
< / TR >
< TR ALIGN = RIGHT > < TD ALIGN = LEFT > Number used as Latches< / TD >
< TD ALIGN = RIGHT > 0< / TD >
< TD > < / TD >
< TD > < / TD >
< TD COLSPAN = '2' > < / TD >
< / TR >
< TR ALIGN = RIGHT > < TD ALIGN = LEFT > Number used as Latch-thrus< / TD >
< TD ALIGN = RIGHT > 0< / TD >
< TD > < / TD >
< TD > < / TD >
< TD COLSPAN = '2' > < / TD >
< / TR >
< TR ALIGN = RIGHT > < TD ALIGN = LEFT > Number used as AND/OR logics< / TD >
< TD ALIGN = RIGHT > 0< / TD >
< TD > < / TD >
< TD > < / TD >
< TD COLSPAN = '2' > < / TD >
< / TR >
< TR ALIGN = RIGHT > < TD ALIGN = LEFT > Number of Slice LUTs< / TD >
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< TD ALIGN = RIGHT > 17< / TD >
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< TD ALIGN = RIGHT > 5,720< / TD >
< TD ALIGN = RIGHT > 1%< / TD >
< TD COLSPAN = '2' > < / TD >
< / TR >
< TR ALIGN = RIGHT > < TD ALIGN = LEFT > Number used as logic< / TD >
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< TD ALIGN = RIGHT > 13< / TD >
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< TD ALIGN = RIGHT > 5,720< / TD >
< TD ALIGN = RIGHT > 1%< / TD >
< TD COLSPAN = '2' > < / TD >
< / TR >
< TR ALIGN = RIGHT > < TD ALIGN = LEFT > Number using O6 output only< / TD >
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< TD ALIGN = RIGHT > 11< / TD >
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< TD > < / TD >
< TD > < / TD >
< TD COLSPAN = '2' > < / TD >
< / TR >
< TR ALIGN = RIGHT > < TD ALIGN = LEFT > Number using O5 output only< / TD >
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< TD ALIGN = RIGHT > 0< / TD >
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< TD > < / TD >
< TD > < / TD >
< TD COLSPAN = '2' > < / TD >
< / TR >
< TR ALIGN = RIGHT > < TD ALIGN = LEFT > Number using O5 and O6< / TD >
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< TD ALIGN = RIGHT > 2< / TD >
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< TD > < / TD >
< TD > < / TD >
< TD COLSPAN = '2' > < / TD >
< / TR >
< TR ALIGN = RIGHT > < TD ALIGN = LEFT > Number used as ROM< / TD >
< TD ALIGN = RIGHT > 0< / TD >
< TD > < / TD >
< TD > < / TD >
< TD COLSPAN = '2' > < / TD >
< / TR >
< TR ALIGN = RIGHT > < TD ALIGN = LEFT > Number used as Memory< / TD >
< TD ALIGN = RIGHT > 0< / TD >
< TD ALIGN = RIGHT > 1,440< / TD >
< TD ALIGN = RIGHT > 0%< / TD >
< TD COLSPAN = '2' > < / TD >
< / TR >
< TR ALIGN = RIGHT > < TD ALIGN = LEFT > Number used exclusively as route-thrus< / TD >
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< TD ALIGN = RIGHT > 4< / TD >
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< TD > < / TD >
< TD > < / TD >
< TD COLSPAN = '2' > < / TD >
< / TR >
< TR ALIGN = RIGHT > < TD ALIGN = LEFT > Number with same-slice register load< / TD >
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< TD ALIGN = RIGHT > 4< / TD >
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< TD > < / TD >
< TD > < / TD >
< TD COLSPAN = '2' > < / TD >
< / TR >
< TR ALIGN = RIGHT > < TD ALIGN = LEFT > Number with same-slice carry load< / TD >
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< TD ALIGN = RIGHT > 0< / TD >
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< TD > < / TD >
< TD > < / TD >
< TD COLSPAN = '2' > < / TD >
< / TR >
< TR ALIGN = RIGHT > < TD ALIGN = LEFT > Number with other load< / TD >
< TD ALIGN = RIGHT > 0< / TD >
< TD > < / TD >
< TD > < / TD >
< TD COLSPAN = '2' > < / TD >
< / TR >
< TR ALIGN = RIGHT > < TD ALIGN = LEFT > Number of occupied Slices< / TD >
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< TD ALIGN = RIGHT > 11< / TD >
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< TD ALIGN = RIGHT > 1,430< / TD >
< TD ALIGN = RIGHT > 1%< / TD >
< TD COLSPAN = '2' > < / TD >
< / TR >
< TR ALIGN = RIGHT > < TD ALIGN = LEFT > Number of MUXCYs used< / TD >
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< TD ALIGN = RIGHT > 12< / TD >
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< TD ALIGN = RIGHT > 2,860< / TD >
< TD ALIGN = RIGHT > 1%< / TD >
< TD COLSPAN = '2' > < / TD >
< / TR >
< TR ALIGN = RIGHT > < TD ALIGN = LEFT > Number of LUT Flip Flop pairs used< / TD >
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< TD ALIGN = RIGHT > 41< / TD >
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< TD > < / TD >
< TD > < / TD >
< TD COLSPAN = '2' > < / TD >
< / TR >
< TR ALIGN = RIGHT > < TD ALIGN = LEFT > Number with an unused Flip Flop< / TD >
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< TD ALIGN = RIGHT > 11< / TD >
< TD ALIGN = RIGHT > 41< / TD >
< TD ALIGN = RIGHT > 26%< / TD >
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< TD COLSPAN = '2' > < / TD >
< / TR >
< TR ALIGN = RIGHT > < TD ALIGN = LEFT > Number with an unused LUT< / TD >
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< TD ALIGN = RIGHT > 24< / TD >
< TD ALIGN = RIGHT > 41< / TD >
< TD ALIGN = RIGHT > 58%< / TD >
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< TD COLSPAN = '2' > < / TD >
< / TR >
< TR ALIGN = RIGHT > < TD ALIGN = LEFT > Number of fully used LUT-FF pairs< / TD >
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< TD ALIGN = RIGHT > 6< / TD >
< TD ALIGN = RIGHT > 41< / TD >
< TD ALIGN = RIGHT > 14%< / TD >
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< TD COLSPAN = '2' > < / TD >
< / TR >
< TR ALIGN = RIGHT > < TD ALIGN = LEFT > Number of unique control sets< / TD >
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< TD ALIGN = RIGHT > 1< / TD >
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< TD > < / TD >
< TD > < / TD >
< TD COLSPAN = '2' > < / TD >
< / TR >
< TR ALIGN = RIGHT > < TD ALIGN = LEFT > Number of slice register sites lost< BR > to control set restrictions< / TD >
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< TD ALIGN = RIGHT > 6< / TD >
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< TD ALIGN = RIGHT > 11,440< / TD >
< TD ALIGN = RIGHT > 1%< / TD >
< TD COLSPAN = '2' > < / TD >
< / TR >
< TR ALIGN = RIGHT > < TD ALIGN = LEFT > Number of bonded < A HREF_DISABLED = 'C:/Users/zanek/Documents/GitHub/Warp-LC/fpga\WarpLC_map.xrpt?&DataKey=IOBProperties' > IOBs< / A > < / TD >
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< TD ALIGN = RIGHT > 43< / TD >
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< TD ALIGN = RIGHT > 186< / TD >
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< TD ALIGN = RIGHT > 23%< / TD >
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< TD COLSPAN = '2' > < / TD >
< / TR >
< TR ALIGN = RIGHT > < TD ALIGN = LEFT > IOB Flip Flops< / TD >
< TD ALIGN = RIGHT > 5< / TD >
< TD > < / TD >
< TD > < / TD >
< TD COLSPAN = '2' > < / TD >
< / TR >
< TR ALIGN = RIGHT > < TD ALIGN = LEFT > Number of RAMB16BWERs< / TD >
< TD ALIGN = RIGHT > 0< / TD >
< TD ALIGN = RIGHT > 32< / TD >
< TD ALIGN = RIGHT > 0%< / TD >
< TD COLSPAN = '2' > < / TD >
< / TR >
< TR ALIGN = RIGHT > < TD ALIGN = LEFT > Number of RAMB8BWERs< / TD >
< TD ALIGN = RIGHT > 0< / TD >
< TD ALIGN = RIGHT > 64< / TD >
< TD ALIGN = RIGHT > 0%< / TD >
< TD COLSPAN = '2' > < / TD >
< / TR >
< TR ALIGN = RIGHT > < TD ALIGN = LEFT > Number of BUFIO2/BUFIO2_2CLKs< / TD >
< TD ALIGN = RIGHT > 1< / TD >
< TD ALIGN = RIGHT > 32< / TD >
< TD ALIGN = RIGHT > 3%< / TD >
< TD COLSPAN = '2' > < / TD >
< / TR >
< TR ALIGN = RIGHT > < TD ALIGN = LEFT > Number used as BUFIO2s< / TD >
< TD ALIGN = RIGHT > 1< / TD >
< TD > < / TD >
< TD > < / TD >
< TD COLSPAN = '2' > < / TD >
< / TR >
< TR ALIGN = RIGHT > < TD ALIGN = LEFT > Number used as BUFIO2_2CLKs< / TD >
< TD ALIGN = RIGHT > 0< / TD >
< TD > < / TD >
< TD > < / TD >
< TD COLSPAN = '2' > < / TD >
< / TR >
< TR ALIGN = RIGHT > < TD ALIGN = LEFT > Number of BUFIO2FB/BUFIO2FB_2CLKs< / TD >
< TD ALIGN = RIGHT > 1< / TD >
< TD ALIGN = RIGHT > 32< / TD >
< TD ALIGN = RIGHT > 3%< / TD >
< TD COLSPAN = '2' > < / TD >
< / TR >
< TR ALIGN = RIGHT > < TD ALIGN = LEFT > Number used as BUFIO2FBs< / TD >
< TD ALIGN = RIGHT > 1< / TD >
< TD > < / TD >
< TD > < / TD >
< TD COLSPAN = '2' > < / TD >
< / TR >
< TR ALIGN = RIGHT > < TD ALIGN = LEFT > Number used as BUFIO2FB_2CLKs< / TD >
< TD ALIGN = RIGHT > 0< / TD >
< TD > < / TD >
< TD > < / TD >
< TD COLSPAN = '2' > < / TD >
< / TR >
< TR ALIGN = RIGHT > < TD ALIGN = LEFT > Number of BUFG/BUFGMUXs< / TD >
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< TD ALIGN = RIGHT > 2< / TD >
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< TD ALIGN = RIGHT > 16< / TD >
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< TD ALIGN = RIGHT > 12%< / TD >
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< TD COLSPAN = '2' > < / TD >
< / TR >
< TR ALIGN = RIGHT > < TD ALIGN = LEFT > Number used as BUFGs< / TD >
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< TD ALIGN = RIGHT > 2< / TD >
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< TD > < / TD >
< TD > < / TD >
< TD COLSPAN = '2' > < / TD >
< / TR >
< TR ALIGN = RIGHT > < TD ALIGN = LEFT > Number used as BUFGMUX< / TD >
< TD ALIGN = RIGHT > 0< / TD >
< TD > < / TD >
< TD > < / TD >
< TD COLSPAN = '2' > < / TD >
< / TR >
< TR ALIGN = RIGHT > < TD ALIGN = LEFT > Number of DCM/DCM_CLKGENs< / TD >
< TD ALIGN = RIGHT > 0< / TD >
< TD ALIGN = RIGHT > 4< / TD >
< TD ALIGN = RIGHT > 0%< / TD >
< TD COLSPAN = '2' > < / TD >
< / TR >
< TR ALIGN = RIGHT > < TD ALIGN = LEFT > Number of ILOGIC2/ISERDES2s< / TD >
< TD ALIGN = RIGHT > 0< / TD >
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< TD ALIGN = RIGHT > 200< / TD >
< TD ALIGN = RIGHT > 0%< / TD >
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< TD COLSPAN = '2' > < / TD >
< / TR >
< TR ALIGN = RIGHT > < TD ALIGN = LEFT > Number of IODELAY2/IODRP2/IODRP2_MCBs< / TD >
< TD ALIGN = RIGHT > 0< / TD >
< TD ALIGN = RIGHT > 200< / TD >
< TD ALIGN = RIGHT > 0%< / TD >
< TD COLSPAN = '2' > < / TD >
< / TR >
< TR ALIGN = RIGHT > < TD ALIGN = LEFT > Number of OLOGIC2/OSERDES2s< / TD >
< TD ALIGN = RIGHT > 5< / TD >
< TD ALIGN = RIGHT > 200< / TD >
< TD ALIGN = RIGHT > 2%< / TD >
< TD COLSPAN = '2' > < / TD >
< / TR >
< TR ALIGN = RIGHT > < TD ALIGN = LEFT > Number used as OLOGIC2s< / TD >
< TD ALIGN = RIGHT > 5< / TD >
< TD > < / TD >
< TD > < / TD >
< TD COLSPAN = '2' > < / TD >
< / TR >
< TR ALIGN = RIGHT > < TD ALIGN = LEFT > Number used as OSERDES2s< / TD >
< TD ALIGN = RIGHT > 0< / TD >
< TD > < / TD >
< TD > < / TD >
< TD COLSPAN = '2' > < / TD >
< / TR >
< TR ALIGN = RIGHT > < TD ALIGN = LEFT > Number of BSCANs< / TD >
< TD ALIGN = RIGHT > 0< / TD >
< TD ALIGN = RIGHT > 4< / TD >
< TD ALIGN = RIGHT > 0%< / TD >
< TD COLSPAN = '2' > < / TD >
< / TR >
< TR ALIGN = RIGHT > < TD ALIGN = LEFT > Number of BUFHs< / TD >
< TD ALIGN = RIGHT > 0< / TD >
< TD ALIGN = RIGHT > 128< / TD >
< TD ALIGN = RIGHT > 0%< / TD >
< TD COLSPAN = '2' > < / TD >
< / TR >
< TR ALIGN = RIGHT > < TD ALIGN = LEFT > Number of BUFPLLs< / TD >
< TD ALIGN = RIGHT > 0< / TD >
< TD ALIGN = RIGHT > 8< / TD >
< TD ALIGN = RIGHT > 0%< / TD >
< TD COLSPAN = '2' > < / TD >
< / TR >
< TR ALIGN = RIGHT > < TD ALIGN = LEFT > Number of BUFPLL_MCBs< / TD >
< TD ALIGN = RIGHT > 0< / TD >
< TD ALIGN = RIGHT > 4< / TD >
< TD ALIGN = RIGHT > 0%< / TD >
< TD COLSPAN = '2' > < / TD >
< / TR >
< TR ALIGN = RIGHT > < TD ALIGN = LEFT > Number of DSP48A1s< / TD >
< TD ALIGN = RIGHT > 0< / TD >
< TD ALIGN = RIGHT > 16< / TD >
< TD ALIGN = RIGHT > 0%< / TD >
< TD COLSPAN = '2' > < / TD >
< / TR >
< TR ALIGN = RIGHT > < TD ALIGN = LEFT > Number of ICAPs< / TD >
< TD ALIGN = RIGHT > 0< / TD >
< TD ALIGN = RIGHT > 1< / TD >
< TD ALIGN = RIGHT > 0%< / TD >
< TD COLSPAN = '2' > < / TD >
< / TR >
< TR ALIGN = RIGHT > < TD ALIGN = LEFT > Number of MCBs< / TD >
< TD ALIGN = RIGHT > 0< / TD >
< TD ALIGN = RIGHT > 2< / TD >
< TD ALIGN = RIGHT > 0%< / TD >
< TD COLSPAN = '2' > < / TD >
< / TR >
< TR ALIGN = RIGHT > < TD ALIGN = LEFT > Number of PCILOGICSEs< / TD >
< TD ALIGN = RIGHT > 0< / TD >
< TD ALIGN = RIGHT > 2< / TD >
< TD ALIGN = RIGHT > 0%< / TD >
< TD COLSPAN = '2' > < / TD >
< / TR >
< TR ALIGN = RIGHT > < TD ALIGN = LEFT > Number of PLL_ADVs< / TD >
< TD ALIGN = RIGHT > 1< / TD >
< TD ALIGN = RIGHT > 2< / TD >
< TD ALIGN = RIGHT > 50%< / TD >
< TD COLSPAN = '2' > < / TD >
< / TR >
< TR ALIGN = RIGHT > < TD ALIGN = LEFT > Number of PMVs< / TD >
< TD ALIGN = RIGHT > 0< / TD >
< TD ALIGN = RIGHT > 1< / TD >
< TD ALIGN = RIGHT > 0%< / TD >
< TD COLSPAN = '2' > < / TD >
< / TR >
< TR ALIGN = RIGHT > < TD ALIGN = LEFT > Number of STARTUPs< / TD >
< TD ALIGN = RIGHT > 0< / TD >
< TD ALIGN = RIGHT > 1< / TD >
< TD ALIGN = RIGHT > 0%< / TD >
< TD COLSPAN = '2' > < / TD >
< / TR >
< TR ALIGN = RIGHT > < TD ALIGN = LEFT > Number of SUSPEND_SYNCs< / TD >
< TD ALIGN = RIGHT > 0< / TD >
< TD ALIGN = RIGHT > 1< / TD >
< TD ALIGN = RIGHT > 0%< / TD >
< TD COLSPAN = '2' > < / TD >
< / TR >
< TR ALIGN = RIGHT > < TD ALIGN = LEFT > Average Fanout of Non-Clock Nets< / TD >
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< TD ALIGN = RIGHT > 1.41< / TD >
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< TD > < / TD >
< TD > < / TD >
< TD COLSPAN = '2' > < / TD >
< / TR >
< / TABLE >
< BR > < TABLE BORDER CELLSPACING = 0 CELLPADDING = 3 WIDTH = '100%' >
< TR ALIGN = CENTER BGCOLOR = '#99CCFF' > < TD ALIGN = CENTER COLSPAN = '4' > < B > Performance Summary< / B > < / TD > < TD ALIGN = RIGHT WIDTH = '10%' COLSPAN = 1 > < A HREF_DISABLED = "?&ExpandedTable=PerformanceSummary" > < B > [-]< / B > < / a > < / TD > < / TR >
< TR ALIGN = LEFT >
< TD BGCOLOR = '#FFFF99' > < B > Final Timing Score:< / B > < / TD >
< TD > 0 (Setup: 0, Hold: 0, Component Switching Limit: 0)< / TD >
< TD BGCOLOR = '#FFFF99' > < B > Pinout Data:< / B > < / TD >
< TD COLSPAN = '2' > < A HREF_DISABLED = 'C:/Users/zanek/Documents/GitHub/Warp-LC/fpga\WarpLC_par.xrpt?&DataKey=PinoutData' > Pinout Report< / A > < / TD >
< / TR >
< TR ALIGN = LEFT >
< TD BGCOLOR = '#FFFF99' > < B > Routing Results:< / B > < / TD > < TD >
< A HREF_DISABLED = 'C:/Users/zanek/Documents/GitHub/Warp-LC/fpga\WarpLC.unroutes' > All Signals Completely Routed< / A > < / TD >
< TD BGCOLOR = '#FFFF99' > < B > Clock Data:< / B > < / TD >
< TD COLSPAN = '2' > < A HREF_DISABLED = 'C:/Users/zanek/Documents/GitHub/Warp-LC/fpga\WarpLC_par.xrpt?&DataKey=ClocksData' > Clock Report< / A > < / TD >
< / TR >
< TR ALIGN = LEFT >
< TD BGCOLOR = '#FFFF99' > < B > Timing Constraints:< / B > < / TD >
< TD >
< A HREF_DISABLED = 'C:/Users/zanek/Documents/GitHub/Warp-LC/fpga\WarpLC.ptwx?&DataKey=ConstraintsData' > All Constraints Met< / A > < / TD >
< TD BGCOLOR = '#FFFF99' > < B > < / B > < / TD >
< TD COLSPAN = '2' > < / TD >
< / TABLE >
< BR > < TABLE BORDER CELLSPACING = 0 CELLPADDING = 3 WIDTH = '100%' >
< TR ALIGN = CENTER BGCOLOR = '#99CCFF' > < TD ALIGN = CENTER COLSPAN = '6' > < B > Detailed Reports< / B > < / TD > < TD ALIGN = RIGHT WIDTH = '10%' COLSPAN = 1 > < A HREF_DISABLED = "?&ExpandedTable=DetailedReports" > < B > [-]< / B > < / a > < / TD > < / TR >
< TR BGCOLOR = '#FFFF99' > < TD > < B > Report Name< / B > < / TD > < TD > < B > Status< / B > < / TD > < TD > < B > Generated< / B > < / TD >
< TD ALIGN = LEFT > < B > Errors< / B > < / TD > < TD ALIGN = LEFT > < B > Warnings< / B > < / TD > < TD ALIGN = LEFT COLSPAN = '2' > < B > Infos< / B > < / TD > < / TR >
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< TR ALIGN = LEFT > < TD > < A HREF_DISABLED = 'C:/Users/zanek/Documents/GitHub/Warp-LC/fpga\WarpLC.syr' > Synthesis Report< / A > < / TD > < TD > Current< / TD > < TD > Fri Oct 29 17:59:39 2021< / TD > < TD ALIGN = LEFT > 0< / TD > < TD ALIGN = LEFT > < A HREF_DISABLED = 'C:/Users/zanek/Documents/GitHub/Warp-LC/fpga\_xmsgs/xst.xmsgs?&DataKey=Warning' > 7 Warnings (0 new)< / A > < / TD > < TD ALIGN = LEFT COLSPAN = '2' > < A HREF_DISABLED = 'C:/Users/zanek/Documents/GitHub/Warp-LC/fpga\_xmsgs/xst.xmsgs?&DataKey=Info' > 2 Infos (0 new)< / A > < / TD > < / TR >
< TR ALIGN = LEFT > < TD > < A HREF_DISABLED = 'C:/Users/zanek/Documents/GitHub/Warp-LC/fpga\WarpLC.bld' > Translation Report< / A > < / TD > < TD > Current< / TD > < TD > Fri Oct 29 17:59:43 2021< / TD > < TD ALIGN = LEFT > 0< / TD > < TD ALIGN = LEFT > 0< / TD > < TD ALIGN = LEFT COLSPAN = '2' > < A HREF_DISABLED = 'C:/Users/zanek/Documents/GitHub/Warp-LC/fpga\_xmsgs/ngdbuild.xmsgs?&DataKey=Info' > 1 Info (0 new)< / A > < / TD > < / TR >
< TR ALIGN = LEFT > < TD > < A HREF_DISABLED = 'C:/Users/zanek/Documents/GitHub/Warp-LC/fpga\WarpLC_map.mrp' > Map Report< / A > < / TD > < TD > Current< / TD > < TD > Fri Oct 29 17:59:48 2021< / TD > < TD ALIGN = LEFT > 0< / TD > < TD ALIGN = LEFT > 0< / TD > < TD ALIGN = LEFT COLSPAN = '2' > < A HREF_DISABLED = 'C:/Users/zanek/Documents/GitHub/Warp-LC/fpga\_xmsgs/map.xmsgs?&DataKey=Info' > 6 Infos (0 new)< / A > < / TD > < / TR >
< TR ALIGN = LEFT > < TD > < A HREF_DISABLED = 'C:/Users/zanek/Documents/GitHub/Warp-LC/fpga\WarpLC.par' > Place and Route Report< / A > < / TD > < TD > Current< / TD > < TD > Fri Oct 29 17:59:53 2021< / TD > < TD ALIGN = LEFT > 0< / TD > < TD ALIGN = LEFT > 0< / TD > < TD ALIGN = LEFT COLSPAN = '2' > 0< / TD > < / TR >
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< TR ALIGN = LEFT > < TD > Power Report< / TD > < TD > < / TD > < TD > < / TD > < TD > < / TD > < TD > < / TD > < TD COLSPAN = '2' > < / TD > < / TR >
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< TR ALIGN = LEFT > < TD > < A HREF_DISABLED = 'C:/Users/zanek/Documents/GitHub/Warp-LC/fpga\WarpLC.twr' > Post-PAR Static Timing Report< / A > < / TD > < TD > Current< / TD > < TD > Fri Oct 29 17:59:57 2021< / TD > < TD ALIGN = LEFT > 0< / TD > < TD ALIGN = LEFT > 0< / TD > < TD ALIGN = LEFT COLSPAN = '2' > < A HREF_DISABLED = 'C:/Users/zanek/Documents/GitHub/Warp-LC/fpga\_xmsgs/trce.xmsgs?&DataKey=Info' > 3 Infos (0 new)< / A > < / TD > < / TR >
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< TR ALIGN = LEFT > < TD > Bitgen Report< / TD > < TD > < / TD > < TD > < / TD > < TD > < / TD > < TD > < / TD > < TD COLSPAN = '2' > < / TD > < / TR >
< / TABLE >
< BR > < TABLE BORDER CELLSPACING = 0 CELLPADDING = 3 WIDTH = '100%' >
< TR ALIGN = CENTER BGCOLOR = '#99CCFF' > < TD ALIGN = CENTER COLSPAN = '3' > < B > Secondary Reports< / B > < / TD > < TD ALIGN = RIGHT WIDTH = '10%' COLSPAN = 1 > < A HREF_DISABLED = "?&ExpandedTable=SecondaryReports" > < B > [-]< / B > < / a > < / TD > < / TR >
< TR BGCOLOR = '#FFFF99' > < TD > < B > Report Name< / B > < / TD > < TD > < B > Status< / B > < / TD > < TD COLSPAN = '2' > < B > Generated< / B > < / TD > < / TR >
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< TR ALIGN = LEFT > < TD > < A HREF_DISABLED = 'C:/Users/zanek/Documents/GitHub/Warp-LC/fpga\WarpLC_preroute.twr' > Post-Map Static Timing Report< / A > < / TD > < TD > Out of Date< / TD > < TD COLSPAN = '2' > Fri Oct 29 10:25:28 2021< / TD > < / TR >
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< / TABLE >
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< br > < center > < b > Date Generated:< / b > 10/29/2021 - 17:59:59< / center >
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< / BODY > < / HTML >
