From 9522519ce782799b242c71a10de2c450644b5898 Mon Sep 17 00:00:00 2001 From: Zane Kaminski Date: Tue, 2 Nov 2021 14:18:24 -0400 Subject: [PATCH] idk more --- fpga/Prefetch.v | 4 +- fpga/SDRAM.v | 46 ++++ fpga/WarpLC.gise | 8 + fpga/WarpLC.v | 4 - fpga/WarpLC.xise | 4 + fpga/WarpLC_summary.html | 8 +- fpga/ipcore_dir/L2WayRAM.xise | 335 +------------------------ fpga/ipcore_dir/PrefetchTagRAM.xise | 335 +------------------------ fpga/ipcore_dir/_xmsgs/pn_parser.xmsgs | 2 +- fpga/iseconfig/WarpLC.projectmgr | 12 +- fpga/iseconfig/WarpLC.xreport | 2 +- 11 files changed, 78 insertions(+), 682 deletions(-) create mode 100644 fpga/SDRAM.v diff --git a/fpga/Prefetch.v b/fpga/Prefetch.v index 0b35ab6..940b74e 100644 --- a/fpga/Prefetch.v +++ b/fpga/Prefetch.v @@ -50,14 +50,14 @@ module L2Prefetch( .clka(CLK), .ena(~CPUCLKr), .wea(4'b0), - .addra({RDFixed7k5SEL ? RDA[12:9] : 4'hF , RDAIndex[6:0]}), + .addra({RDFixed7k5SEL ? RDA[12:9] : 4'hF , RDAIndex}), .dina(32'b0), .douta(RDD[31:0]), .clkb(CLK), .enb(1'b0), .web(WRM[3:0]), - .addrb({RDFixed7k5SEL ? WRA[12:9] : 4'hF , WRAIndex[6:0]}), + .addrb({RDFixed7k5SEL ? WRA[12:9] : 4'hF , WRAIndex}), .dinb(WRD[31:0])); endmodule diff --git a/fpga/SDRAM.v b/fpga/SDRAM.v new file mode 100644 index 0000000..fce32de --- /dev/null +++ b/fpga/SDRAM.v @@ -0,0 +1,46 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 12:02:55 11/02/2021 +// Design Name: +// Module Name: SDRAM +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module SDRAM( + input [25:2] A, + input [3:0] B, + input WR, + input SEL, + input CLK, + input [31:0] WRD, + input RDD, + output nCS, + output nRAS, + output nCAS, + output nWE, + output [3:0] DQM, + output [1:0] BA, + output [12:0] RA, + output STERM, + output RAMEN, + output CA, + input CTS, + input CWR, + input CPUCLKr, + input BURST + ); + + +endmodule diff --git a/fpga/WarpLC.gise b/fpga/WarpLC.gise index e4be11e..4036107 100644 --- a/fpga/WarpLC.gise +++ b/fpga/WarpLC.gise @@ -82,6 +82,9 @@ + + + @@ -105,16 +108,20 @@ + + + + @@ -131,6 +138,7 @@ + diff --git a/fpga/WarpLC.v b/fpga/WarpLC.v index 0dfa118..8c75ec4 100644 --- a/fpga/WarpLC.v +++ b/fpga/WarpLC.v @@ -150,14 +150,10 @@ endmodule /* Cacheable areas of RAM * ... - * 0x50FFFFFF VRAM alias 0101 0000 1111 11XX XXXX XXXX XXXX XXXX - * 0x50FC0000 * 0x50FBFFFF VRAM 0101 0000 1111 10XX XXXX XXXX XXXX XXXX * 0x50F80000 * 0x50F7FFFF VRAM 0101 0000 1111 01XX XXXX XXXX XXXX XXXX * 0x50F40000 - * 0x50F3FFFF VRAM alias 0101 0000 1111 00XX XXXX XXXX XXXX XXXX - * 0x50F00000 * ... * 0x40FFFFFF ROM alias? 0100 0000 111X XXXX XXXX XXXX XXXX XXXX * 0x40E00000 diff --git a/fpga/WarpLC.xise b/fpga/WarpLC.xise index 9ca4596..625de9d 100644 --- a/fpga/WarpLC.xise +++ b/fpga/WarpLC.xise @@ -62,6 +62,10 @@ + + + + diff --git a/fpga/WarpLC_summary.html b/fpga/WarpLC_summary.html index 72a9b19..8e062a8 100644 --- a/fpga/WarpLC_summary.html +++ b/fpga/WarpLC_summary.html @@ -2,7 +2,7 @@ - + @@ -429,10 +429,10 @@ System Settings  
WarpLC Project Status (11/02/2021 - 00:33:38)
WarpLC Project Status (11/01/2021 - 06:10:50)
Project File: WarpLC.xise
- - + +
Secondary Reports [-]
Report NameStatusGenerated
Post-Map Static Timing ReportOut of DateTue Nov 2 00:33:37 2021
Physical Synthesis ReportOut of DateTue Nov 2 00:33:32 2021
Post-Map Static Timing ReportCurrentTue Nov 2 00:33:37 2021
Physical Synthesis ReportCurrentTue Nov 2 00:33:32 2021
-
Date Generated: 11/02/2021 - 00:35:21
+
Date Generated: 11/02/2021 - 11:45:39
\ No newline at end of file diff --git a/fpga/ipcore_dir/L2WayRAM.xise b/fpga/ipcore_dir/L2WayRAM.xise index 4efb9ff..eb701c3 100644 --- a/fpga/ipcore_dir/L2WayRAM.xise +++ b/fpga/ipcore_dir/L2WayRAM.xise @@ -29,357 +29,28 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + - - - - - - - diff --git a/fpga/ipcore_dir/PrefetchTagRAM.xise b/fpga/ipcore_dir/PrefetchTagRAM.xise index 8571ac9..40df69d 100644 --- a/fpga/ipcore_dir/PrefetchTagRAM.xise +++ b/fpga/ipcore_dir/PrefetchTagRAM.xise @@ -29,357 +29,28 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + - - - - - - - diff --git a/fpga/ipcore_dir/_xmsgs/pn_parser.xmsgs b/fpga/ipcore_dir/_xmsgs/pn_parser.xmsgs index 1a5f4a5..bf7057d 100644 --- a/fpga/ipcore_dir/_xmsgs/pn_parser.xmsgs +++ b/fpga/ipcore_dir/_xmsgs/pn_parser.xmsgs @@ -8,7 +8,7 @@ -Analyzing Verilog file "C:/Users/Dog/Documents/GitHub/Warp-LC/fpga/ipcore_dir/PrefetchTagRAM.v" into library work +Analyzing Verilog file "C:/Users/Dog/Documents/GitHub/Warp-LC/fpga/ipcore_dir/L2WayRAM.v" into library work diff --git a/fpga/iseconfig/WarpLC.projectmgr b/fpga/iseconfig/WarpLC.projectmgr index dc2d2fc..6cd6e3a 100644 --- a/fpga/iseconfig/WarpLC.projectmgr +++ b/fpga/iseconfig/WarpLC.projectmgr @@ -10,13 +10,13 @@ /ClkGen C:|Users|Dog|Documents|GitHub|Warp-LC|fpga|ClkGen.v - WarpLC (C:/Users/Dog/Documents/GitHub/Warp-LC/fpga/WarpLC.v) + cs - CS (C:/Users/Dog/Documents/GitHub/Warp-LC/fpga/CS.v) 0 0 000000ff0000000000000001000000010000000000000000000000000000000002020000000100000001000000640000016a000000020000000000000000000000000200000064ffffffff0000008100000003000000020000016a0000000100000003000000000000000100000003 true - WarpLC (C:/Users/Dog/Documents/GitHub/Warp-LC/fpga/WarpLC.v) + cs - CS (C:/Users/Dog/Documents/GitHub/Warp-LC/fpga/CS.v) @@ -43,9 +43,9 @@ 0 0 - 000000ff0000000000000001000000000000000001000000000000000000000000000000000000032b000000040101000100000000000000000000000064ffffffff0000008100000000000000040000004200000001000000000000002400000001000000000000006600000001000000000000025f0000000100000000 + 000000ff00000000000000010000000000000000010000000000000000000000000000000000000153000000040101000100000000000000000000000064ffffffff000000810000000000000004000000420000000100000000000000240000000100000000000000660000000100000000000000870000000100000000 false - WarpLC.v + ClkGen.v @@ -87,9 +87,9 @@ - 12 + 0 0 - 000000ff00000000000000010000000100000000000000000000000000000000000000000000000142000000010000000100000000000000000000000064ffffffff000000810000000000000001000001420000000100000000 + 000000ff00000000000000010000000100000000000000000000000000000000000000000000000153000000010000000100000000000000000000000064ffffffff000000810000000000000001000001530000000100000000 false diff --git a/fpga/iseconfig/WarpLC.xreport b/fpga/iseconfig/WarpLC.xreport index bad34af..08c303b 100644 --- a/fpga/iseconfig/WarpLC.xreport +++ b/fpga/iseconfig/WarpLC.xreport @@ -1,7 +1,7 @@
- 2021-11-02T00:18:51 + 2021-11-02T11:02:50 WarpLC 2021-11-01T06:10:50 C:/Users/Dog/Documents/GitHub/Warp-LC/fpga/iseconfig/WarpLC.xreport