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This commit is contained in:
Zane Kaminski 2022-02-03 00:34:12 -05:00
parent 9522519ce7
commit ea671fe500
10 changed files with 1851 additions and 1692 deletions
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20
LICENSE Normal file
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@ -0,0 +1,20 @@
Copyright (c) Garrett's Workshop
Rationale
----------------------------------------
We at Garrett's Workshop create our products and release their source in
hopes of encouraging others to contribute and build their own "clones,"
even selling them and competing with us. One day, GW will be defunct,
and it would be a shame if our hardware and software die along with GW.
At the same time, however, we seek to protect our trademark and ensure
that clones and derivative products do not masquerade as genuine
Garrett's Workshop products.
License Terms
----------------------------------------
This project may be licensed under one of two licenses:
1. You may elect to license this project under CC BY-NC-SA 4.0.
2. You may elect to license this project under CC BY-SA 4.0 ONLY IF
you remove all "Garrett's Workshop" trademarks from the project.

BIN
SE-030-backups/SE-030-2022-02-02_021941.zip Normal file
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SE-030-backups/SE-030-2022-02-02_152026.zip Normal file
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SE-030-backups/SE-030-2022-02-02_153807.zip Normal file
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2961
SE-030.kicad_pcb
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75
SE-030.kicad_prl Normal file
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@ -0,0 +1,75 @@
{
"board": {
"active_layer": 0,
"active_layer_preset": "All Layers",
"auto_track_width": true,
"hidden_nets": [],
"high_contrast_mode": 0,
"net_color_mode": 1,
"opacity": {
"pads": 1.0,
"tracks": 1.0,
"vias": 1.0,
"zones": 0.6
},
"ratsnest_display_mode": 0,
"selection_filter": {
"dimensions": true,
"footprints": true,
"graphics": true,
"keepouts": true,
"lockedItems": true,
"otherItems": true,
"pads": true,
"text": true,
"tracks": true,
"vias": true,
"zones": true
},
"visible_items": [
0,
1,
2,
3,
4,
5,
8,
9,
10,
11,
12,
13,
14,
15,
16,
17,
18,
19,
20,
21,
22,
23,
24,
25,
26,
27,
28,
29,
30,
32,
33,
34,
35,
36
],
"visible_layers": "fffffff_ffffffff",
"zone_display_mode": 0
},
"meta": {
"filename": "SE-030.kicad_prl",
"version": 3
},
"project": {
"files": []
}
}

225
SE-030.kicad_pro Normal file
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@ -0,0 +1,225 @@
{
"board": {
"design_settings": {
"defaults": {
"board_outline_line_width": 0.15,
"copper_line_width": 0.15239999999999998,
"copper_text_italic": false,
"copper_text_size_h": 1.5,
"copper_text_size_v": 1.5,
"copper_text_thickness": 0.3,
"copper_text_upright": false,
"courtyard_line_width": 0.049999999999999996,
"dimension_precision": 4,
"dimension_units": 3,
"dimensions": {
"arrow_length": 1270000,
"extension_offset": 500000,
"keep_text_aligned": true,
"suppress_zeroes": false,
"text_position": 0,
"units_format": 1
},
"fab_line_width": 0.09999999999999999,
"fab_text_italic": false,
"fab_text_size_h": 1.0,
"fab_text_size_v": 1.0,
"fab_text_thickness": 0.15,
"fab_text_upright": false,
"other_line_width": 0.09999999999999999,
"other_text_italic": false,
"other_text_size_h": 1.0,
"other_text_size_v": 1.0,
"other_text_thickness": 0.15,
"other_text_upright": false,
"pads": {
"drill": 0.0,
"height": 0.95,
"width": 0.7
},
"silk_line_width": 0.15,
"silk_text_italic": false,
"silk_text_size_h": 1.0,
"silk_text_size_v": 1.0,
"silk_text_thickness": 0.15,
"silk_text_upright": false,
"zones": {
"45_degree_only": false,
"min_clearance": 0.15239999999999998
}
},
"diff_pair_dimensions": [],
"drc_exclusions": [],
"meta": {
"filename": "board_design_settings.json",
"version": 2
},
"rule_severities": {
"annular_width": "error",
"clearance": "error",
"copper_edge_clearance": "error",
"courtyards_overlap": "error",
"diff_pair_gap_out_of_range": "error",
"diff_pair_uncoupled_length_too_long": "error",
"drill_out_of_range": "error",
"duplicate_footprints": "warning",
"extra_footprint": "warning",
"footprint_type_mismatch": "error",
"hole_clearance": "error",
"hole_near_hole": "error",
"invalid_outline": "error",
"item_on_disabled_layer": "error",
"items_not_allowed": "error",
"length_out_of_range": "error",
"malformed_courtyard": "error",
"microvia_drill_out_of_range": "error",
"missing_courtyard": "ignore",
"missing_footprint": "warning",
"net_conflict": "warning",
"npth_inside_courtyard": "ignore",
"padstack": "error",
"pth_inside_courtyard": "ignore",
"shorting_items": "error",
"silk_over_copper": "warning",
"silk_overlap": "warning",
"skew_out_of_range": "error",
"through_hole_pad_without_hole": "error",
"too_many_vias": "error",
"track_dangling": "warning",
"track_width": "error",
"tracks_crossing": "error",
"unconnected_items": "error",
"unresolved_variable": "error",
"via_dangling": "warning",
"zone_has_empty_net": "error",
"zones_intersect": "error"
},
"rule_severitieslegacy_courtyards_overlap": true,
"rule_severitieslegacy_no_courtyard_defined": false,
"rules": {
"allow_blind_buried_vias": false,
"allow_microvias": false,
"max_error": 0.005,
"min_clearance": 0.0,
"min_copper_edge_clearance": 0.075,
"min_hole_clearance": 0.25,
"min_hole_to_hole": 0.25,
"min_microvia_diameter": 0.19999999999999998,
"min_microvia_drill": 0.09999999999999999,
"min_silk_clearance": 0.0,
"min_through_hole_diameter": 0.19999999999999998,
"min_track_width": 0.15,
"min_via_annular_width": 0.049999999999999996,
"min_via_diameter": 0.5,
"use_height_for_length_calcs": true
},
"track_widths": [
0.0,
0.2,
0.25,
0.3,
0.35,
0.4,
0.45,
0.5,
0.55,
0.6,
0.8,
1.0,
1.27,
1.524
],
"via_dimensions": [
{
"diameter": 0.0,
"drill": 0.0
},
{
"diameter": 0.6,
"drill": 0.3
},
{
"diameter": 0.8,
"drill": 0.4
},
{
"diameter": 1.0,
"drill": 0.5
},
{
"diameter": 1.524,
"drill": 0.762
}
],
"zones_allow_external_fillets": false,
"zones_use_no_outline": true
},
"layer_presets": []
},
"boards": [],
"cvpcb": {
"equivalence_files": []
},
"libraries": {
"pinned_footprint_libs": [],
"pinned_symbol_libs": []
},
"meta": {
"filename": "SE-030.kicad_pro",
"version": 1
},
"net_settings": {
"classes": [
{
"bus_width": 12.0,
"clearance": 0.15,
"diff_pair_gap": 0.25,
"diff_pair_via_gap": 0.25,
"diff_pair_width": 0.2,
"line_style": 0,
"microvia_diameter": 0.3,
"microvia_drill": 0.1,
"name": "Default",
"pcb_color": "rgba(0, 0, 0, 0.000)",
"schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 0.15,
"via_diameter": 0.5,
"via_drill": 0.2,
"wire_width": 6.0
}
],
"meta": {
"version": 2
},
"net_colors": null
},
"pcbnew": {
"last_paths": {
"gencad": "",
"idf": "",
"netlist": "SE-030.net",
"specctra_dsn": "",
"step": "",
"vrml": ""
},
"page_layout_descr_file": ""
},
"schematic": {
"drawing": {
"default_text_size": 50,
"label_size_ratio": 0.25,
"pin_symbol_size": 0,
"text_offset_ratio": 0.08
},
"legacy_lib_dir": "",
"legacy_lib_list": [],
"net_format_name": "Pcbnew",
"page_layout_descr_file": "",
"plot_directory": "",
"spice_adjust_passive_values": false,
"subpart_first_id": 65,
"subpart_id_separator": 0
},
"sheets": [],
"text_variables": {}
}

242
SE-030.sch
View File

@ -183,13 +183,13 @@ Connection ~ 1200 3400
Wire Wire Line Wire Wire Line
1100 3400 1200 3400 1100 3400 1200 3400
Wire Bus Line Wire Bus Line
4300 3100 4300 3500 4150 3100 4150 3500
Wire Bus Line Wire Bus Line
2500 700 4000 700 2500 700 4000 700
Wire Wire Line Wire Wire Line
4400 1800 3900 1800 4300 1800 3900 1800
Wire Bus Line Wire Bus Line
4300 3500 4400 3500 4150 3500 4300 3500
Wire Wire Line Wire Wire Line
2500 900 4200 900 2500 900 4200 900
Wire Bus Line Wire Bus Line
@ -198,99 +198,99 @@ Wire Bus Line
4000 1200 3900 1200 4000 1200 3900 1200
Connection ~ 4000 700 Connection ~ 4000 700
Wire Bus Line Wire Bus Line
4000 700 4400 700 4000 700 4300 700
Wire Bus Line Wire Bus Line
3900 1300 4100 1300 3900 1300 4100 1300
Wire Bus Line Wire Bus Line
4100 1300 4100 800 4100 1300 4100 800
Connection ~ 4100 800 Connection ~ 4100 800
Wire Bus Line Wire Bus Line
4100 800 4400 800 4100 800 4300 800
Wire Wire Line Wire Wire Line
4200 900 4200 1400 4200 900 4200 1400
Wire Wire Line Wire Wire Line
4200 1400 3900 1400 4200 1400 3900 1400
Connection ~ 4200 900 Connection ~ 4200 900
Wire Wire Line Wire Wire Line
4200 900 4400 900 4200 900 4300 900
Wire Bus Line Wire Bus Line
2500 800 4100 800 2500 800 4100 800
$Sheet $Sheet
S 5750 600 550 5700 S 5650 600 550 5700
U 5F72F108 U 5F72F108
F0 "MC68k" 50 F0 "MC68k" 50
F1 "MC68k.sch" 50 F1 "MC68k.sch" 50
F2 "~AS~" O L 5750 2100 50 F2 "~AS~" O L 5650 2100 50
F3 "~RESET~" B L 5750 6100 50 F3 "~RESET~" B L 5650 6100 50
F4 "~BERR~" I L 5750 5900 50 F4 "~BERR~" I L 5650 5900 50
F5 "~CBREQ~" O L 5750 2300 50 F5 "~CBREQ~" O L 5650 2300 50
F6 "D[31..0]" B L 5750 3100 50 F6 "D[31..0]" B L 5650 3100 50
F7 "~CIOUT~" O L 5750 1700 50 F7 "~CIOUT~" O L 5650 1700 50
F8 "R~W~" O L 5750 900 50 F8 "R~W~" O L 5650 900 50
F9 "~RMC~" O L 5750 1000 50 F9 "~RMC~" O L 5650 1000 50
F10 "A[31..0]" O L 5750 800 50 F10 "A[31..0]" O L 5650 800 50
F11 "FC[2..0]" O L 5750 700 50 F11 "FC[2..0]" O L 5650 700 50
F12 "SIZ[1..0]" O L 5750 1600 50 F12 "SIZ[1..0]" O L 5650 1600 50
F13 "~DSACK~1" B L 5750 2500 50 F13 "~DSACK~1" B L 5650 2500 50
F14 "~DSACK~0" B L 5750 2600 50 F14 "~DSACK~0" B L 5650 2600 50
F15 "~IPL~[2..0]" I L 5750 6200 50 F15 "~IPL~[2..0]" I L 5650 6200 50
F16 "~DS~" O L 5750 2200 50 F16 "~DS~" O L 5650 2200 50
F17 "CPUCLK" I L 5750 5000 50 F17 "CPUCLK" I L 5650 5000 50
F18 "~CIIN~" I L 5750 5700 50 F18 "~CIIN~" I L 5650 5700 50
F19 "~STERM~" I L 5750 5500 50 F19 "~STERM~" I L 5650 5500 50
F20 "~HALT~" I L 5750 5800 50 F20 "~HALT~" I L 5650 5800 50
F21 "~CBACK~" I L 5750 5600 50 F21 "~CBACK~" I L 5650 5600 50
F22 "~ECS~" O L 5750 2000 50 F22 "~ECS~" O L 5650 2000 50
F23 "FPUCLK" I L 5750 5200 50 F23 "FPUCLK" I L 5650 5200 50
F24 "FPU~CS~" I L 5750 5300 50 F24 "FPU~CS~" I L 5650 5300 50
$EndSheet $EndSheet
Connection ~ 4300 3100 Connection ~ 4150 3100
Wire Bus Line Wire Bus Line
4300 3100 4400 3100 4150 3100 4300 3100
Wire Bus Line Wire Bus Line
4400 1600 3900 1600 4300 1600 3900 1600
Wire Wire Line Wire Wire Line
4400 1700 3900 1700 4300 1700 3900 1700
Wire Wire Line Wire Wire Line
1200 6100 5750 6100 1200 6100 5650 6100
Wire Bus Line Wire Bus Line
1100 6200 5750 6200 1100 6200 5650 6200
Wire Wire Line Wire Wire Line
3900 2900 4400 2900 3900 2900 4300 2900
Wire Wire Line Wire Wire Line
3900 3000 4400 3000 3900 3000 4300 3000
Wire Wire Line Wire Wire Line
3900 2100 4400 2100 3900 2100 4300 2100
Wire Wire Line Wire Wire Line
3900 2000 4400 2000 3900 2000 4300 2000
Wire Wire Line Wire Wire Line
3900 2300 4400 2300 3900 2300 4300 2300
Wire Wire Line Wire Wire Line
3900 2200 4400 2200 3900 2200 4300 2200
Wire Wire Line Wire Wire Line
3900 2600 4400 2600 3900 2600 4300 2600
Wire Wire Line Wire Wire Line
3900 2700 4400 2700 3900 2700 4300 2700
Wire Wire Line Wire Wire Line
3900 2500 4400 2500 3900 2500 4300 2500
Wire Bus Line Wire Bus Line
3900 3100 4300 3100 3900 3100 4150 3100
Wire Wire Line Wire Wire Line
3900 5000 5750 5000 3900 5000 5650 5000
Wire Wire Line Wire Wire Line
3900 5200 5750 5200 3900 5200 5650 5200
Wire Wire Line Wire Wire Line
3900 5300 5750 5300 3900 5300 5650 5300
Wire Wire Line Wire Wire Line
3900 5600 5750 5600 3900 5600 5650 5600
Wire Wire Line Wire Wire Line
3900 5500 5750 5500 3900 5500 5650 5500
Wire Wire Line Wire Wire Line
3900 5700 5750 5700 3900 5700 5650 5700
Wire Wire Line Wire Wire Line
3900 5900 5750 5900 3900 5900 5650 5900
Wire Wire Line Wire Wire Line
3900 5800 5750 5800 3900 5800 5650 5800
Wire Wire Line Wire Wire Line
2600 5000 2500 5000 2600 5000 2500 5000
Wire Wire Line Wire Wire Line
@ -324,68 +324,68 @@ Wire Wire Line
Wire Bus Line Wire Bus Line
2500 3100 2600 3100 2500 3100 2600 3100
Wire Bus Line Wire Bus Line
5650 3100 5750 3100 5550 3100 5650 3100
Wire Wire Line Wire Wire Line
5750 2600 5650 2600 5650 2600 5550 2600
Wire Wire Line Wire Wire Line
5750 2500 5650 2500 5650 2500 5550 2500
Wire Wire Line Wire Wire Line
5750 2300 5650 2300 5650 2300 5550 2300
Wire Wire Line Wire Wire Line
5750 2200 5650 2200 5650 2200 5550 2200
Wire Wire Line Wire Wire Line
5750 2100 5650 2100 5650 2100 5550 2100
Wire Wire Line Wire Wire Line
5750 2000 5650 2000 5650 2000 5550 2000
Wire Wire Line Wire Wire Line
5750 1700 5650 1700 5650 1700 5550 1700
Wire Bus Line Wire Bus Line
5650 1600 5750 1600 5550 1600 5650 1600
Wire Wire Line Wire Wire Line
5750 1000 5650 1000 5650 1000 5550 1000
Wire Wire Line Wire Wire Line
5750 900 5650 900 5650 900 5550 900
Wire Bus Line Wire Bus Line
5650 800 5750 800 5550 800 5650 800
Wire Bus Line Wire Bus Line
5650 700 5750 700 5550 700 5650 700
$Sheet $Sheet
S 4400 3400 1250 1500 S 4300 3400 1250 1500
U 63261D60 U 63261D60
F0 "RAM" 50 F0 "RAM" 50
F1 "RAM.sch" 50 F1 "RAM.sch" 50
F2 "~RAS~" I L 4400 3800 50 F2 "~RAS~" I L 4300 3800 50
F3 "~CAS~" I L 4400 3900 50 F3 "~CAS~" I L 4300 3900 50
F4 "~CS~" I L 4400 3700 50 F4 "~CS~" I L 4300 3700 50
F5 "~WE~" I L 4400 4000 50 F5 "~WE~" I L 4300 4000 50
F6 "CKE" I L 4400 4100 50 F6 "CKE" I L 4300 4100 50
F7 "CLK01" I L 4400 4700 50 F7 "CLK01" I L 4300 4700 50
F8 "RA[12..0]" I L 4400 4400 50 F8 "RA[12..0]" I L 4300 4400 50
F9 "D[31..0]" B L 4400 3500 50 F9 "D[31..0]" B L 4300 3500 50
F10 "CLK23" I L 4400 4800 50 F10 "CLK23" I L 4300 4800 50
F11 "BA[1..0]" I L 4400 4300 50 F11 "BA[1..0]" I L 4300 4300 50
F12 "DQM[3..0]" I L 4400 4500 50 F12 "DQM[3..0]" I L 4300 4500 50
$EndSheet $EndSheet
Wire Wire Line Wire Wire Line
3900 4800 4400 4800 3900 4800 4300 4800
Wire Wire Line Wire Wire Line
3900 4700 4400 4700 3900 4700 4300 4700
Wire Bus Line Wire Bus Line
4400 4500 3900 4500 4300 4500 3900 4500
Wire Bus Line Wire Bus Line
4400 4400 3900 4400 4300 4400 3900 4400
Wire Bus Line Wire Bus Line
4400 4300 3900 4300 4300 4300 3900 4300
Wire Wire Line Wire Wire Line
3900 4100 4400 4100 3900 4100 4300 4100
Wire Wire Line Wire Wire Line
3900 4000 4400 4000 3900 4000 4300 4000
Wire Wire Line Wire Wire Line
3900 3900 4400 3900 3900 3900 4300 3900
Wire Wire Line Wire Wire Line
3900 3800 4400 3800 3900 3800 4300 3800
Wire Wire Line Wire Wire Line
3900 3700 4400 3700 3900 3700 4300 3700
Wire Wire Line Wire Wire Line
1100 5900 1300 5900 1100 5900 1300 5900
Wire Wire Line Wire Wire Line
@ -489,41 +489,41 @@ F51 "RAM_CLK01" O R 3900 4700 50
F52 "RAM_CLK23" O R 3900 4800 50 F52 "RAM_CLK23" O R 3900 4800 50
$EndSheet $EndSheet
$Sheet $Sheet
S 4400 600 1250 2600 S 4300 600 1250 2600
U 629B918A U 629B918A
F0 "CPUBuf" 50 F0 "CPUBuf" 50
F1 "CPUBuf.sch" 50 F1 "CPUBuf.sch" 50
F2 "D~OE~" I L 4400 2900 50 F2 "D~OE~" I L 4300 2900 50
F3 "DDIR" I L 4400 3000 50 F3 "DDIR" I L 4300 3000 50
F4 "CPU_D[31..0]" B R 5650 3100 50 F4 "CPU_D[31..0]" B R 5550 3100 50
F5 "A~OE~" I L 4400 1800 50 F5 "A~OE~" I L 4300 1800 50
F6 "CPU_~CBREQ~" I R 5650 2300 50 F6 "CPU_~CBREQ~" I R 5550 2300 50
F7 "CPU_~DS~" I R 5650 2200 50 F7 "CPU_~DS~" I R 5550 2200 50
F8 "CPU_~AS~" I R 5650 2100 50 F8 "CPU_~AS~" I R 5550 2100 50
F9 "CPU_~CIOUT~" I R 5650 1700 50 F9 "CPU_~CIOUT~" I R 5550 1700 50
F10 "CPU_R~W~" I R 5650 900 50 F10 "CPU_R~W~" I R 5550 900 50
F11 "CPU_~RMC~" I R 5650 1000 50 F11 "CPU_~RMC~" I R 5550 1000 50
F12 "FSB_~DS~" O L 4400 2200 50 F12 "FSB_~DS~" O L 4300 2200 50
F13 "FSB_~AS~" O L 4400 2100 50 F13 "FSB_~AS~" O L 4300 2100 50
F14 "FSB_R~W~" T L 4400 900 50 F14 "FSB_R~W~" T L 4300 900 50
F15 "FSB_~RMC~" T L 4400 1500 50 F15 "FSB_~RMC~" T L 4300 1500 50
F16 "FSB_~CIOUT~" O L 4400 1700 50 F16 "FSB_~CIOUT~" O L 4300 1700 50
F17 "FSB_A[31..0]" T L 4400 800 50 F17 "FSB_A[31..0]" T L 4300 800 50
F18 "CPU_A[31..0]" I R 5650 800 50 F18 "CPU_A[31..0]" I R 5550 800 50
F19 "FSB_FC[2..0]" T L 4400 700 50 F19 "FSB_FC[2..0]" T L 4300 700 50
F20 "FSB_SIZ[1..0]" O L 4400 1600 50 F20 "FSB_SIZ[1..0]" O L 4300 1600 50
F21 "FSB_~CBREQ~" O L 4400 2300 50 F21 "FSB_~CBREQ~" O L 4300 2300 50
F22 "FSB_D[31..0]" B L 4400 3100 50 F22 "FSB_D[31..0]" B L 4300 3100 50
F23 "CPU_FC[2..0]" I R 5650 700 50 F23 "CPU_FC[2..0]" I R 5550 700 50
F24 "CPU_SIZ[1..0]" I R 5650 1600 50 F24 "CPU_SIZ[1..0]" I R 5550 1600 50
F25 "DSACK~OE~" I L 4400 2700 50 F25 "DSACK~OE~" I L 4300 2700 50
F26 "CPU_~DSACK~1" T R 5650 2500 50 F26 "CPU_~DSACK~1" T R 5550 2500 50
F27 "CPU_~DSACK~0" T R 5650 2600 50 F27 "CPU_~DSACK~0" T R 5550 2600 50
F28 "FSB_~DSACK~1" I L 4400 2500 50 F28 "FSB_~DSACK~1" I L 4300 2500 50
F29 "FSB_~DSACK~0" I L 4400 2600 50 F29 "FSB_~DSACK~0" I L 4300 2600 50
F30 "CPU_~ECS~" I R 5650 2000 50 F30 "CPU_~ECS~" I R 5550 2000 50
F31 "FSB_~ECS~" O L 4400 2000 50 F31 "FSB_~ECS~" O L 4300 2000 50
$EndSheet $EndSheet
Wire Wire Line Wire Wire Line
3900 1500 4400 1500 3900 1500 4300 1500
$EndSCHEMATC $EndSCHEMATC

2
fp-lib-table
View File

@ -1,3 +1,3 @@
(fp_lib_table (fp_lib_table
(lib (name stdpads)(type KiCad)(uri "$(KIPRJMOD)/../../stdpads.pretty")(options "")(descr "")) (lib (name stdpads)(type KiCad)(uri "$(KIPRJMOD)/../stdpads.pretty")(options "")(descr ""))
) )

18
sym-lib-table
View File

@ -1,11 +1,11 @@
(sym_lib_table (sym_lib_table
(lib (name GW_PLD)(type Legacy)(uri ${KIPRJMOD}/../../GW_Parts/GW_PLD.lib)(options "")(descr "")) (lib (name GW_PLD)(type Legacy)(uri ${KIPRJMOD}/../GW_Parts/GW_PLD.lib)(options "")(descr ""))
(lib (name GW_Logic)(type Legacy)(uri ${KIPRJMOD}/../../GW_Parts/GW_Logic.lib)(options "")(descr "")) (lib (name GW_Logic)(type Legacy)(uri ${KIPRJMOD}/../GW_Parts/GW_Logic.lib)(options "")(descr ""))
(lib (name GW_Power)(type Legacy)(uri ${KIPRJMOD}/../../GW_Parts/GW_Power.lib)(options "")(descr "")) (lib (name GW_Power)(type Legacy)(uri ${KIPRJMOD}/../GW_Parts/GW_Power.lib)(options "")(descr ""))
(lib (name GW_RFModule)(type Legacy)(uri ${KIPRJMOD}/../../GW_Parts/GW_RFModule.lib)(options "")(descr "")) (lib (name GW_RFModule)(type Legacy)(uri ${KIPRJMOD}/../GW_Parts/GW_RFModule.lib)(options "")(descr ""))
(lib (name GW_MCU)(type Legacy)(uri ${KIPRJMOD}/../../GW_Parts/GW_MCU.lib)(options "")(descr "")) (lib (name GW_MCU)(type Legacy)(uri ${KIPRJMOD}/../GW_Parts/GW_MCU.lib)(options "")(descr ""))
(lib (name GW_Connector)(type Legacy)(uri ${KIPRJMOD}/../../GW_Parts/GW_Connector.lib)(options "")(descr "")) (lib (name GW_Connector)(type Legacy)(uri ${KIPRJMOD}/../GW_Parts/GW_Connector.lib)(options "")(descr ""))
(lib (name GW_Digital)(type Legacy)(uri ${KIPRJMOD}/../../GW_Parts/GW_Digital.lib)(options "")(descr "")) (lib (name GW_Digital)(type Legacy)(uri ${KIPRJMOD}/../GW_Parts/GW_Digital.lib)(options "")(descr ""))
(lib (name GW_RAM)(type Legacy)(uri ${KIPRJMOD}/../../GW_Parts/GW_RAM.lib)(options "")(descr "")) (lib (name GW_RAM)(type Legacy)(uri ${KIPRJMOD}/../GW_Parts/GW_RAM.lib)(options "")(descr ""))
(lib (name GW_CPU)(type Legacy)(uri ${KIPRJMOD}/../../GW_Parts/GW_CPU.lib)(options "")(descr "")) (lib (name GW_CPU)(type Legacy)(uri ${KIPRJMOD}/../GW_Parts/GW_CPU.lib)(options "")(descr ""))
) )