]> Release 14.7 Trace (nt)Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.C:\Xilinx\14.7\ISE_DS\ISE\bin\nt\unwrapped\trce.exe -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml WarpLC.twx WarpLC.ncd -o WarpLC.twr WarpLC.pcf -ucf PLL.ucf WarpLC.ncdWarpLC.ncdWarpLC.pcfWarpLC.pcfxc6slx9C-2PRODUCTION 1.23 2013-10-1313INFO:Timing:3412 - To improve timing, see the Timing Closure User Guide (UG612).INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths option. All paths that are not constrained will be reported in the unconstrained paths section(s) of the report.INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on a 50 Ohm transmission line loading model. For the details of this model, and for more information on accounting for different loading conditions, please see the device datasheet.NET "FSBCLK" PERIOD = 10 ns HIGH 50%;20000201.489Paths for end point OUTt (SLICE_X1Y7.B1), 1 path 8.511CPUCLKOUTt1.3410.00010.0000.148CPUCLKOUTt1SLICE_X1Y7.CLKFSBCLKSLICE_X1Y7.AQTcko0.430OUTt_OBUFCPUCLKSLICE_X1Y7.B1net30.538CPUCLK_OBUFSLICE_X1Y7.CLKTas0.373OUTt_OBUFCPU_nAS_CPUCLKi_AND_2_o1OUTt0.8030.5381.341FSBCLK59.940.1Paths for end point CPUCLK (SLICE_X1Y7.A6), 1 path 8.889CPUCLKCPUCLK0.9630.00010.0000.148CPUCLKCPUCLK1SLICE_X1Y7.CLKFSBCLKSLICE_X1Y7.AQTcko0.430OUTt_OBUFCPUCLKSLICE_X1Y7.A6net30.160CPUCLK_OBUFSLICE_X1Y7.CLKTas0.373OUTt_OBUFCPUCLK_rstpot1_INV_0CPUCLK0.8030.1600.963FSBCLK83.416.6Hold Paths: NET "FSBCLK" PERIOD = 10 ns HIGH 50%; Paths for end point CPUCLK (SLICE_X1Y7.A6), 1 path 0.444CPUCLKCPUCLK0.4440.0000.0000.000CPUCLKCPUCLK1SLICE_X1Y7.CLKFSBCLKSLICE_X1Y7.AQTcko0.198OUTt_OBUFCPUCLKSLICE_X1Y7.A6net30.031CPUCLK_OBUFSLICE_X1Y7.CLKTah0.215OUTt_OBUFCPUCLK_rstpot1_INV_0CPUCLK0.4130.0310.444FSBCLK93.07.0Paths for end point OUTt (SLICE_X1Y7.B1), 1 path 0.684CPUCLKOUTt0.6840.0000.0000.000CPUCLKOUTt1SLICE_X1Y7.CLKFSBCLKSLICE_X1Y7.AQTcko0.198OUTt_OBUFCPUCLKSLICE_X1Y7.B1net30.271CPUCLK_OBUFSLICE_X1Y7.CLKTah0.215OUTt_OBUFCPU_nAS_CPUCLKi_AND_2_o1OUTt0.4130.2710.684FSBCLK60.439.6Component Switching Limit Checks: NET "FSBCLK" PERIOD = 10 ns HIGH 50%;NET "instance_name/clkin1" PERIOD = 20 ns HIGH 50%;00000005.000Component Switching Limit Checks: NET "instance_name/clkin1" PERIOD = 20 ns HIGH 50%;PERIOD analysis for net "instance_name/clkfbout" derived from NET "instance_name/clkin1" PERIOD = 20 ns HIGH 50%; duty cycle corrected to 20 nS HIGH 10 nS 00000002.666Component Switching Limit Checks: PERIOD analysis for net "instance_name/clkfbout" derived from NET "instance_name/clkin1" PERIOD = 20 ns HIGH 50%; duty cycle corrected to 20 nS HIGH 10 nS PERIOD analysis for net "instance_name/clkout0" derived from NET "instance_name/clkin1" PERIOD = 20 ns HIGH 50%; divided by 2.00 to 10 nS 00000002.666Component Switching Limit Checks: PERIOD analysis for net "instance_name/clkout0" derived from NET "instance_name/clkin1" PERIOD = 20 ns HIGH 50%; divided by 2.00 to 10 nS 0CLKINCLKIN1.489000020115.000200.000Fri Oct 29 10:30:09 2021 TraceTrace Settings Peak Memory Usage: 168 MB