INFO:sim:172 - Generating IP... Applying current project options... Finished applying current project options. WARNING:sim - A core named 'CLK' already exists in the project. Output products for this core may be overwritten. Resolving generics for 'CLK'... WARNING:sim - A core named 'CLK' already exists in the project. Output products for this core may be overwritten. Applying external generics to 'CLK'... Delivering associated files for 'CLK'... WARNING:sim - Component clk_wiz_v3_6 does not have a valid model name for Verilog synthesis Delivering EJava files for 'CLK'... Delivered 3 files into directory C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/ipcore_dir/tmp/_cg/CLK Delivered 1 file into directory C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/ipcore_dir/tmp/_cg/CLK Generating ASY schematic symbol... Loading device for application Rf_Device from file '6slx9.nph' in environment C:\Xilinx\14.7\ISE_DS\ISE\. INFO:sim:949 - Finished generation of ASY schematic symbol. Generating SYM schematic symbol for 'CLK'... Generating ISE project... XCO file found: CLK.xco XMDF file found: CLK_xmdf.tcl Adding C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/ipcore_dir/tmp/_cg/CLK.asy -view all -origin_type imported Adding C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/ipcore_dir/tmp/_cg/CLK.ucf -view all -origin_type created Adding C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/ipcore_dir/tmp/_cg/CLK.v -view all -origin_type created INFO:HDLCompiler:1845 - Analyzing Verilog file "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/ipcore_dir/tmp/_cg/CLK.v" into library work INFO:ProjectMgmt - Parsing design hierarchy completed successfully. Adding C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/ipcore_dir/tmp/_cg/CLK.veo -view all -origin_type imported INFO:TclTasksC:2116 - The automatic calculation of top has been turned-off. Please set the new top explicitly by running the "project set top" command. To re-calculate the new top automatically, set the "Auto Implementation Top" property to true. Top level has been set to "/CLK" Generating README file... Generating FLIST file... INFO:sim:948 - Finished FLIST file generation. Launching README viewer... Moving files to output directory... Finished moving files to output directory Wrote CGP file for project 'CLK'.