Release 14.7 - xst P.20131013 (nt) Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. --> Parameter TMPDIR set to xst/projnav.tmp Total REAL time to Xst completion: 0.00 secs Total CPU time to Xst completion: 0.08 secs --> Parameter xsthdpdir set to xst Total REAL time to Xst completion: 0.00 secs Total CPU time to Xst completion: 0.08 secs --> Reading design: STERMINATOR.prj TABLE OF CONTENTS 1) Synthesis Options Summary 2) HDL Compilation 3) Design Hierarchy Analysis 4) HDL Analysis 5) HDL Synthesis 5.1) HDL Synthesis Report 6) Advanced HDL Synthesis 6.1) Advanced HDL Synthesis Report 7) Low Level Synthesis 8) Partition Report 9) Final Report ========================================================================= * Synthesis Options Summary * ========================================================================= ---- Source Parameters Input File Name : "STERMINATOR.prj" Input Format : mixed Ignore Synthesis Constraint File : NO ---- Target Parameters Output File Name : "STERMINATOR" Output Format : NGC Target Device : XC9500XL CPLDs ---- Source Options Top Module Name : STERMINATOR Automatic FSM Extraction : YES FSM Encoding Algorithm : Auto Safe Implementation : No Mux Extraction : Yes Resource Sharing : YES ---- Target Options Add IO Buffers : YES MACRO Preserve : YES XOR Preserve : YES Equivalent register Removal : YES ---- General Options Optimization Goal : Speed Optimization Effort : 1 Keep Hierarchy : Yes Netlist Hierarchy : As_Optimized RTL Output : Yes Hierarchy Separator : / Bus Delimiter : <> Case Specifier : Maintain Verilog 2001 : YES ---- Other Options Clock Enable : YES wysiwyg : NO ========================================================================= ========================================================================= * HDL Compilation * ========================================================================= Compiling verilog file "../STERMINATOR.v" in library work Module compiled No errors in compilation Analysis of file <"STERMINATOR.prj"> succeeded. ========================================================================= * Design Hierarchy Analysis * ========================================================================= Analyzing hierarchy for module in library . ========================================================================= * HDL Analysis * ========================================================================= Analyzing top module . Module is correct for synthesis. ========================================================================= * HDL Synthesis * ========================================================================= Performing bidirectional port resolution... Synthesizing Unit . Related source file is "../STERMINATOR.v". WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. Found 1-bit register for signal . Found 2-bit register for signal . Found 9-bit register for signal . Found 9-bit adder for signal created at line 51. Found 13-bit register for signal . Found 2-bit comparator equal for signal created at line 59. Found 13-bit comparator equal for signal created at line 59. Found 9-bit comparator equal for signal created at line 59. Summary: inferred 1 D-type flip-flop(s). inferred 1 Adder/Subtractor(s). inferred 3 Comparator(s). Unit synthesized. ========================================================================= HDL Synthesis Report Macro Statistics # Adders/Subtractors : 1 9-bit adder : 1 # Registers : 4 1-bit register : 1 13-bit register : 1 2-bit register : 1 9-bit register : 1 # Comparators : 3 13-bit comparator equal : 1 2-bit comparator equal : 1 9-bit comparator equal : 1 ========================================================================= ========================================================================= * Advanced HDL Synthesis * ========================================================================= ========================================================================= Advanced HDL Synthesis Report Macro Statistics # Adders/Subtractors : 1 9-bit adder : 1 # Registers : 1 Flip-Flops : 1 # Comparators : 3 13-bit comparator equal : 1 2-bit comparator equal : 1 9-bit comparator equal : 1 ========================================================================= ========================================================================= * Low Level Synthesis * ========================================================================= Optimizing unit ... ========================================================================= * Partition Report * ========================================================================= Partition Implementation Status ------------------------------- No Partitions were found in this design. ------------------------------- ========================================================================= * Final Report * ========================================================================= Final Results RTL Top Level Output File Name : STERMINATOR.ngr Top Level Output File Name : STERMINATOR Output Format : NGC Optimization Goal : Speed Keep Hierarchy : Yes Target Technology : XC9500XL CPLDs Macro Preserve : YES XOR Preserve : YES Clock Enable : YES wysiwyg : NO Design Statistics # IOs : 42 Cell Usage : # BELS : 102 # AND2 : 14 # AND3 : 5 # AND4 : 2 # AND5 : 1 # AND8 : 2 # GND : 1 # INV : 41 # OR2 : 4 # XOR2 : 32 # FlipFlops/Latches : 25 # FD : 1 # FDCE : 24 # IO Buffers : 39 # IBUF : 37 # OBUF : 2 ========================================================================= Total REAL time to Xst completion: 2.00 secs Total CPU time to Xst completion: 2.08 secs --> Total memory usage is 225560 kilobytes Number of errors : 0 ( 0 filtered) Number of warnings : 2 ( 0 filtered) Number of infos : 0 ( 0 filtered)