WarpLC Project Status (10/29/2021 - 10:03:11)
Project File: WarpLC.xise Parser Errors: No Errors
Module Name: WarpLC Implementation State: Placed and Routed
Target Device: xc6slx9-2ftg256
  • Errors:
No Errors
Product Version:ISE 14.7
  • Warnings:
527 Warnings (2 new)
Design Goal: Balanced
  • Routing Results:
All Signals Completely Routed
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
All Constraints Met
Environment: System Settings
  • Final Timing Score:
0  (Timing Report)
 
Device Utilization Summary [-]
Slice Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Registers 56 11,440 1%  
    Number used as Flip Flops 56      
    Number used as Latches 0      
    Number used as Latch-thrus 0      
    Number used as AND/OR logics 0      
Number of Slice LUTs 59 5,720 1%  
    Number used as logic 56 5,720 1%  
        Number using O6 output only 24      
        Number using O5 output only 29      
        Number using O5 and O6 3      
        Number used as ROM 0      
    Number used as Memory 0 1,440 0%  
    Number used exclusively as route-thrus 3      
        Number with same-slice register load 2      
        Number with same-slice carry load 1      
        Number with other load 0      
Number of occupied Slices 25 1,430 1%  
Number of MUXCYs used 56 2,860 1%  
Number of LUT Flip Flop pairs used 76      
    Number with an unused Flip Flop 22 76 28%  
    Number with an unused LUT 17 76 22%  
    Number of fully used LUT-FF pairs 37 76 48%  
    Number of unique control sets 4      
    Number of slice register sites lost
        to control set restrictions
16 11,440 1%  
Number of bonded IOBs 49 186 26%  
    IOB Flip Flops 5      
    IOB Latches 1      
Number of RAMB16BWERs 0 32 0%  
Number of RAMB8BWERs 0 64 0%  
Number of BUFIO2/BUFIO2_2CLKs 1 32 3%  
    Number used as BUFIO2s 1      
    Number used as BUFIO2_2CLKs 0      
Number of BUFIO2FB/BUFIO2FB_2CLKs 1 32 3%  
    Number used as BUFIO2FBs 1      
    Number used as BUFIO2FB_2CLKs 0      
Number of BUFG/BUFGMUXs 3 16 18%  
    Number used as BUFGs 3      
    Number used as BUFGMUX 0      
Number of DCM/DCM_CLKGENs 0 4 0%  
Number of ILOGIC2/ISERDES2s 1 200 1%  
    Number used as ILOGIC2s 1      
    Number used as ISERDES2s 0      
Number of IODELAY2/IODRP2/IODRP2_MCBs 0 200 0%  
Number of OLOGIC2/OSERDES2s 5 200 2%  
    Number used as OLOGIC2s 5      
    Number used as OSERDES2s 0      
Number of BSCANs 0 4 0%  
Number of BUFHs 0 128 0%  
Number of BUFPLLs 0 8 0%  
Number of BUFPLL_MCBs 0 4 0%  
Number of DSP48A1s 0 16 0%  
Number of ICAPs 0 1 0%  
Number of MCBs 0 2 0%  
Number of PCILOGICSEs 0 2 0%  
Number of PLL_ADVs 1 2 50%  
Number of PMVs 0 1 0%  
Number of STARTUPs 0 1 0%  
Number of SUSPEND_SYNCs 0 1 0%  
Average Fanout of Non-Clock Nets 2.16      
 
Performance Summary [-]
Final Timing Score: 0 (Setup: 0, Hold: 0, Component Switching Limit: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentFri Oct 29 10:02:50 20210272 Warnings (0 new)2 Infos (0 new)
Translation ReportCurrentFri Oct 29 10:02:55 20210254 Warnings (1 new)1 Info (0 new)
Map ReportCurrentFri Oct 29 10:03:01 202101 Warning (1 new)8 Infos (1 new)
Place and Route ReportCurrentFri Oct 29 10:03:06 2021000
Power Report     
Post-PAR Static Timing ReportCurrentFri Oct 29 10:03:09 2021003 Infos (0 new)
Bitgen Report     
 
Secondary Reports [-]
Report NameStatusGenerated
Post-Map Static Timing ReportOut of DateFri Oct 29 08:28:45 2021

Date Generated: 10/29/2021 - 10:03:11