23 lines
415 B
Verilog
23 lines
415 B
Verilog
module CS(
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input [31:0] A,
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output RAMCS,
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output ROMCS,
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output VRAMCS,
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output CacheCS,
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output LoMemCacheCS,
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output [27:0] CA);
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assign RAMCS = A[31:30]==2'b00;
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assign ROMCS = A[31:28]==4'h4;
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assign VRAMCS = A[31:20]==12'h50F;
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assign CacheCS = RAMCS || ROMCS || VRAMCS;
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assign LoMemCacheCS = RAMCS && A[25:12]==0;
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assign CA[27] = A[30];
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assign CA[26] = A[28];
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assign CA[25:2] = A[25:2];
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endmodule
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