62 lines
4.2 KiB
XML
62 lines
4.2 KiB
XML
<?xml version="1.0" encoding="UTF-8" ?>
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<document>
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<!--The data in this file is primarily intended for consumption by Xilinx tools.
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The structure and the elements are likely to change over the next few releases.
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This means code written to parse this file will need to be revisited each subsequent release.-->
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<application name="pn" timeStamp="Tue Nov 02 00:32:55 2021">
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<section name="Project Information" visible="false">
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<property name="ProjectID" value="048F5CC81F664AF08A457B4C46CE1270" type="project"/>
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<property name="ProjectIteration" value="42" type="project"/>
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<property name="ProjectFile" value="C:/Users/Dog/Documents/GitHub/Warp-LC/fpga/WarpLC.xise" type="project"/>
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<property name="ProjectCreationTimestamp" value="2021-10-29T06:11:44" type="project"/>
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</section>
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<section name="Project Statistics" visible="true">
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<property name="PROPEXT_MapGlobalOptimization_spartan6" value="Speed" type="process"/>
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<property name="PROP_Enable_Message_Filtering" value="false" type="design"/>
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<property name="PROP_FitterReportFormat" value="HTML" type="process"/>
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<property name="PROP_LastAppliedGoal" value="Balanced" type="design"/>
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<property name="PROP_LastAppliedStrategy" value="Xilinx Default (unlocked)" type="design"/>
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<property name="PROP_ManualCompileOrderImp" value="false" type="design"/>
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<property name="PROP_MapLogicOptimization_spartan6" value="true" type="process"/>
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<property name="PROP_PostTrceGenTimegroups" value="true" type="process"/>
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<property name="PROP_PropSpecInProjFile" value="Store all values" type="design"/>
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<property name="PROP_Simulator" value="ISim (VHDL/Verilog)" type="design"/>
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<property name="PROP_SynthOptEffort_spartan6" value="High" type="process"/>
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<property name="PROP_SynthTopFile" value="changed" type="process"/>
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<property name="PROP_Top_Level_Module_Type" value="HDL" type="design"/>
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<property name="PROP_UseSmartGuide" value="false" type="design"/>
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<property name="PROP_UserConstraintEditorPreference" value="Text Editor" type="process"/>
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<property name="PROP_intProjectCreationTimestamp" value="2021-10-29T06:11:44" type="design"/>
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<property name="PROP_intWbtProjectID" value="048F5CC81F664AF08A457B4C46CE1270" type="design"/>
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<property name="PROP_intWbtProjectIteration" value="42" type="process"/>
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<property name="PROP_intWorkingDirLocWRTProjDir" value="Same" type="design"/>
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<property name="PROP_intWorkingDirUsed" value="No" type="design"/>
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<property name="PROP_lockPinsUcfFile" value="changed" type="process"/>
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<property name="PROP_xilxBitgStart_IntDone" value="true" type="process"/>
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<property name="PROP_xilxPostTrceUncovPath" value="10000" type="process"/>
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<property name="PROP_xilxSynthGlobOpt" value="Inpad To Outpad" type="process"/>
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<property name="PROP_AutoTop" value="true" type="design"/>
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<property name="PROP_DevFamily" value="Spartan6" type="design"/>
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<property name="PROP_MapExtraEffort_spartan6" value="Continue on Impossible" type="process"/>
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<property name="PROP_MapRegDuplication_spartan6" value="On" type="process"/>
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<property name="PROP_ibiswriterOutputFile" value="L2Prefetch" type="process"/>
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<property name="PROP_xilxMapEnableMultiThreading" value="2" type="process"/>
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<property name="PROPEXT_xilxPARextraEffortLevel_spartan6" value="Continue on Impossible" type="process"/>
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<property name="PROP_DevDevice" value="xc6slx9" type="design"/>
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<property name="PROP_DevFamilyPMName" value="spartan6" type="design"/>
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<property name="PROP_DevPackage" value="ftg256" type="design"/>
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<property name="PROP_Synthesis_Tool" value="XST (VHDL/Verilog)" type="design"/>
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<property name="PROP_parEnableMultiThreading_spartan6" value="4" type="process"/>
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<property name="PROP_DevSpeed" value="-2" type="design"/>
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<property name="PROP_PreferredLanguage" value="Verilog" type="design"/>
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<property name="PROP_netgenPostMapSimModelName" value="L2Prefetch_map.v" type="process"/>
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<property name="PROP_netgenPostParSimModelName" value="L2Prefetch_timesim.v" type="process"/>
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<property name="PROP_netgenPostSynthesisSimModelName" value="L2Prefetch_synthesis.v" type="process"/>
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<property name="PROP_netgenPostXlateSimModelName" value="L2Prefetch_translate.v" type="process"/>
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<property name="FILE_COREGEN" value="4" type="source"/>
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<property name="FILE_UCF" value="1" type="source"/>
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<property name="FILE_VERILOG" value="7" type="source"/>
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</section>
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</application>
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</document>
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