mirror of
https://github.com/garrettsworkshop/Warp-LC.git
synced 2025-02-27 10:29:09 +00:00
50 lines
2.2 KiB
Plaintext
50 lines
2.2 KiB
Plaintext
INFO:sim:172 - Generating IP...
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Applying current project options...
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Finished applying current project options.
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WARNING:sim - A core named 'CLK' already exists in the project. Output products
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for this core may be overwritten.
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Resolving generics for 'CLK'...
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WARNING:sim - A core named 'CLK' already exists in the project. Output products
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for this core may be overwritten.
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Applying external generics to 'CLK'...
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Delivering associated files for 'CLK'...
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WARNING:sim - Component clk_wiz_v3_6 does not have a valid model name for
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Verilog synthesis
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Delivering EJava files for 'CLK'...
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Delivered 3 files into directory
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C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/ipcore_dir/tmp/_cg/CLK
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Delivered 1 file into directory
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C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/ipcore_dir/tmp/_cg/CLK
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Generating ASY schematic symbol...
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Loading device for application Rf_Device from file '6slx9.nph' in environment
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C:\Xilinx\14.7\ISE_DS\ISE\.
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INFO:sim:949 - Finished generation of ASY schematic symbol.
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Generating SYM schematic symbol for 'CLK'...
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Generating ISE project...
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XCO file found: CLK.xco
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XMDF file found: CLK_xmdf.tcl
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Adding C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/ipcore_dir/tmp/_cg/CLK.asy
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-view all -origin_type imported
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Adding C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/ipcore_dir/tmp/_cg/CLK.ucf
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-view all -origin_type created
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Adding C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/ipcore_dir/tmp/_cg/CLK.v
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-view all -origin_type created
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INFO:HDLCompiler:1845 - Analyzing Verilog file
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"C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/ipcore_dir/tmp/_cg/CLK.v" into
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library work
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INFO:ProjectMgmt - Parsing design hierarchy completed successfully.
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Adding C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/ipcore_dir/tmp/_cg/CLK.veo
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-view all -origin_type imported
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INFO:TclTasksC:2116 - The automatic calculation of top has been turned-off.
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Please set the new top explicitly by running the "project set top" command.
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To re-calculate the new top automatically, set the "Auto Implementation Top"
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property to true.
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Top level has been set to "/CLK"
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Generating README file...
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Generating FLIST file...
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INFO:sim:948 - Finished FLIST file generation.
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Launching README viewer...
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Moving files to output directory...
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Finished moving files to output directory
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Wrote CGP file for project 'CLK'.
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