68 lines
1.3 KiB
Verilog
68 lines
1.3 KiB
Verilog
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 06:35:56 10/26/2021
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// Design Name:
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// Module Name: STERMINATOR
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// Project Name:
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// Target Devices:
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// Tool versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module STERMINATOR(
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input [2:0] FC,
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input [31:2] A,
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input nWE,
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input nAS,
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input CLK,
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input CLKdat,
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input [1:0] CMD,
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input STERM,
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output nSTERM,
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output nFPUCS);
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wire ROMCS = FC[2] && ~FC[0] && A[31:28]==4'b0100;
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wire RAMCS = FC[2] && ~FC[0] && A[31:30]==2'b00;
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wire RAMROMCS = RAMCS || ROMCS;
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reg NA;
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reg [1:0] NB;
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reg [12:0] NR;
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reg [8:0] NC;
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wire [1:0] AB = A[25:24];
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wire [12:0] AR = A[23:11];
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wire [8:0] AC = A[10:2];
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always @(posedge CLK) begin
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if (CMD==1) begin
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NA <= 1;
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NB <= AB;
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NR <= AR;
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NC <= AC+1;
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end else if (CMD==2) begin
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NA <= 0;
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end else if (CMD==3) begin
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NA <= 0;
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end
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end
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wire NSEL = RAMROMCS && NA && AB==NB && AR==NR && AC==NC;
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assign nSTERM = ~(STERM || NSEL);
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wire FPUCS = FC[02:00]==3'h7 && A[19:16]==4'h2 && A[15:13]==3'h1;
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assign nFPUCS = ~((FPUCS && ~CLKdat) || (FPUCS && ~nAS));
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endmodule
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