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42 lines
826 B
Verilog
42 lines
826 B
Verilog
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 19:13:46 10/30/2021
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// Design Name:
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// Module Name: PrefetchBuf
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// Project Name:
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// Target Devices:
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// Tool versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module PrefetchBuf(
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input [31:0] RDA,
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output [31:0] RDD,
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output Match,
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input CLK,
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input [31:0] WRA,
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input [31:0] WRDin,
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output [31:0] WRDout,
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input [3:0] WE,
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input TS);
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RAM128X1D Way0[55:0] (
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.DPO(WRDout),
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.SPO(RDD),
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.A(WRA[10:2]),
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.D({A[WRDin[7:0]),
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.DPRA(RDA),
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.WCLK(CLK),
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.WE(WE));
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endmodule
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