mirror of
https://github.com/garrettsworkshop/Warp-LC.git
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89 lines
2.0 KiB
Verilog
89 lines
2.0 KiB
Verilog
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 17:33:01 10/30/2021
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// Design Name:
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// Module Name: sterminator
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// Project Name:
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// Target Devices:
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// Tool versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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// SDRAM addressing for RAM
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// A[25:13] - Row[12:0]
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// A[12:4] - Column[8:0]
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// A[3:2] - Bank[1:0]
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// A[1:0] - SDRAM word size
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module sterminator(
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input CLK,
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input [31:2] A,
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input nWE,
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input SEL,
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input STERMin,
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output nSTERM,
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input RESET,
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input [2:0] CMD);
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reg [3:0] BankActive;
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reg [12:0] Bank0Row;
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reg [12:0] Bank1Row;
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reg [12:0] Bank2Row;
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reg [12:0] Bank3Row;
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reg SpecRDActive;
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reg [30:2] SpecRDAddr;
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wire [12:0] A_Row = A[25:13];
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wire [8:0] A_Column = A[12:4];
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wire [1:0] A_Bank = A[3:2];
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wire A_CurBankRow = A_Bank==0 ? Bank0Row :
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A_Bank==1 ? Bank1Row :
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A_Bank==2 ? Bank2Row :
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A_Bank==3 ? Bank3Row : 0;
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wire SpecRDSEL = SEL && nWE && ~A[31] && A[30:2]==SpecRDAddr[30:2];
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wire FastWRSEL = SEL && ~nWE && ~A[31] && A_CurBankRow==A_Row;
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assign nSTERM = ~(STERMin || SpecRDSEL || FastWRSEL);
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always @(posedge CLK) begin
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case (CMD)
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3'b000: begin // Reset
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BankActive <= 0;
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SpecRDActive <= 0;
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end 3'b001: begin // Row activate
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BankActive[A_Bank] <= 1;
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case (A_Bank)
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0: Bank0Row <= A_Row;
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1: Bank1Row <= A_Row;
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2: Bank2Row <= A_Row;
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3: Bank3Row <= A_Row;
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endcase
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end 3'b010: begin // Row precharge
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BankActive[A_Bank] <= 0;
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end 3'b011: begin // Precharge all
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BankActive <= 0;
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end 3'b100: begin // NOP
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end 3'b101: begin // Speculative read
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SpecRDAddr <= A[30:2];
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SpecRDActive <= 1;
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end 3'b110: begin // Clear speculation
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SpecRDActive <= 0;
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end 3'b111: begin // Reserved (NOP)
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end
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endcase
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end
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endmodule
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