64 lines
1.2 KiB
Verilog
64 lines
1.2 KiB
Verilog
/* L2 Prefetch Buffer
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* Prefetch tag RAM - 128 x 20 bits
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* (1) Valid
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* (19) Tag - {A[30], A[28], A[25:2]}
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* Prefetch data RAM -
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*/
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module L2Prefetch(
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input CLK,
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input CPUCLKr,
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input [27:2] RDA,
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input RDFixed7k5SEL,
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output [31:0] RDD,
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output Match,
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input [27:2] WRA,
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input [31:0] WRD,
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input WR,
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input [3:0] WRM,
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input CLR);
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/* Read Address */
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wire [18:0] RDATag = RDA[27:9];
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wire [6:0] RDAIndex = RDA[8:2];
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/* Write Address */
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wire [18:0] WRATag = WRA[27:9];
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wire [6:0] WRAIndex = WRA[8:2];
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/* Tag & Valid */
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wire [18:0] RDTag;
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wire [18:0] TSTag;
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wire RDValid;
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wire TSValid;
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wire RDMatch = RDValid && RDTag==RDATag;
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wire TSMatch = TSValid && TSTag==WRATag;
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PrefetchTagRAM tag (
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.clk(CLK),
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.we(WR && (WRM[3:0]==4'b1111 || TSMatch)),
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.a(WRAIndex),
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.d({~CLR, WRATag}),
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.spo({TSValid, TSTag}),
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.dpra(RDAIndex),
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.dpo({RDValid, RDTag}));
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assign Match = RDMatch || RDFixed7k5SEL;
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/* Data */
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PrefetchDataRAM data (
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.clka(CLK),
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.ena(~CPUCLKr),
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.wea(4'b0),
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.addra({RDFixed7k5SEL ? RDA[12:9] : 4'hF , RDAIndex}),
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.dina(32'b0),
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.douta(RDD[31:0]),
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.clkb(CLK),
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.enb(1'b0),
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.web(WRM[3:0]),
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.addrb({RDFixed7k5SEL ? WRA[12:9] : 4'hF , WRAIndex}),
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.dinb(WRD[31:0]));
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endmodule
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