47 lines
873 B
Verilog
47 lines
873 B
Verilog
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 12:02:55 11/02/2021
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// Design Name:
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// Module Name: SDRAM
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// Project Name:
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// Target Devices:
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// Tool versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module SDRAM(
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input [25:2] A,
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input [3:0] B,
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input WR,
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input SEL,
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input CLK,
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input [31:0] WRD,
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input RDD,
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output nCS,
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output nRAS,
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output nCAS,
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output nWE,
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output [3:0] DQM,
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output [1:0] BA,
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output [12:0] RA,
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output STERM,
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output RAMEN,
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output CA,
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input CTS,
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input CWR,
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input CPUCLKr,
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input BURST
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);
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endmodule
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