207 lines
4.9 KiB
Verilog
207 lines
4.9 KiB
Verilog
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 06:27:24 10/29/2021
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// Design Name:
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// Module Name: WarpLC
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// Project Name:
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// Target Devices:
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// Tool versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module WarpLC(
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(* IOSTANDARD = "LVCMOS33" *)
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(* IOBDELAY = "NONE" *)
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input CPU_nAS,
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(* IOSTANDARD = "LVCMOS33" *)
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(* IOBDELAY = "NONE" *)
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input [31:0] FSB_A,
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(* IOSTANDARD = "LVCMOS33" *)
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(* IOBDELAY = "NONE" *)
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input [1:0] FSB_SIZ,
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(* IOSTANDARD = "LVCMOS33" *)
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(* DRIVE = "8" *)
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(* SLEW = "SLOW" *)
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output [31:0] FSB_D,
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(* IOSTANDARD = "LVCMOS33" *)
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(* DRIVE = "24" *)
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(* SLEW = "FAST" *)
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output CPU_nSTERM,
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(* IOSTANDARD = "LVCMOS33" *)
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(* DRIVE = "24" *)
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(* SLEW = "FAST" *)
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output CPUCLK,
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(* IOSTANDARD = "LVCMOS33" *)
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(* DRIVE = "24" *)
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(* SLEW = "FAST" *)
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output FPUCLK,
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(* IOSTANDARD = "LVCMOS33" *)
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(* DRIVE = "24" *)
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(* SLEW = "FAST" *)
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output RAMCLK0,
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(* IOSTANDARD = "LVCMOS33" *)
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(* DRIVE = "24" *)
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(* SLEW = "FAST" *)
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output RAMCLK1,
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(* IOSTANDARD = "LVCMOS33" *)
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(* IOBDELAY = "NONE" *)
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input CLKIN,
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(* IOSTANDARD = "LVCMOS33" *)
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(* IOBDELAY = "NONE" *)
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input CLKFB_IN,
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(* IOSTANDARD = "LVCMOS33" *)
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(* DRIVE = "24" *)
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(* SLEW = "FAST" *)
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output CLKFB_OUT);
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wire FSBCLK;
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wire CPUCLKr;
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ClkGen cg (
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.CLKIN(CLKIN),
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.CLKFB_IN(CLKFB_IN),
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.CLKFB_OUT(CLKFB_OUT),
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.FSBCLK(FSBCLK),
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.CPUCLKr(CPUCLKr),
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.CPUCLK(CPUCLK),
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.FPUCLK(FPUCLK),
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.RAMCLK0(RAMCLK0),
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.RAMCLK1(RAMCLK1));
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wire FSB_SEL_RAM, FSB_SEL_ROM, FSB_VRAM, FSB_SEL_Cache;
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wire [27:0] FSB_CA;
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CS cs(
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.A(FSB_A),
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.RAMCS(FSB_SEL_RAM),
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.ROMCS(FSB_SEL_ROM),
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.VRAMCS(FSB_VRAM),
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.CacheCS(FSB_SEL_Cache),
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.CA(FSB_CA));
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wire [3:0] FSB_B;
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SizeDecode sd (
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.A(FSB_A[1:0]),
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.SIZ(FSB_SIZ[1:0]),
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.B(FSB_B[3:0]));
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wire L2PrefetchMatch;
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wire [31:0] L2PrefetchRDD;
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L2Prefetch prefetch (
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.CLK(FSBCLK),
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.CPUCLKr(CPUCLKr),
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.RDA({FSB_A[30], FSB_A[28], FSB_A[25:2]}),
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.RDD(L2PrefetchRDD),
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.Match(L2PrefetchMatch),
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.WRA(28'b0),
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.WRD(32'b0),
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.WR(1'b0),
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.WRM(4'b0),
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.CLR(1'b0));
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wire L2CacheMatch;
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wire [31:0] L2CacheRDD;
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L2Cache cache (
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.CLK(CLK),
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.CPUCLKr(CPUCLKr),
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.RDA({FSB_A[30], FSB_A[28], FSB_A[25:2]}),
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.RDD(L2CacheRDD),
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.Match(L2CacheMatch),
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.WRA(28'b0),
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.WRD(32'b0),
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.WRM(4'b0),
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.TS(1'b0),
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.WR(1'b0),
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.CLR(1'b0),
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.ALL(1'b0));
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assign FSB_D[31:0] = L2PrefetchMatch ? L2PrefetchRDD[31:0] :
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L2CacheMatch ? L2CacheRDD[31:0] : 0;
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reg STERMEN = 0;
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reg STERM = 0;
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assign CPU_nSTERM = ~((L2PrefetchMatch && STERMEN) || STERM);
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endmodule
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/* Cacheable areas of RAM
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* ...
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* 0x50FBFFFF VRAM 0101 0000 1111 10XX XXXX XXXX XXXX XXXX
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* 0x50F80000
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* 0x50F7FFFF VRAM 0101 0000 1111 01XX XXXX XXXX XXXX XXXX
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* 0x50F40000
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* ...
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* 0x40FFFFFF ROM alias? 0100 0000 111X XXXX XXXX XXXX XXXX XXXX
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* 0x40E00000
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* 0x40DFFFFF ROM 0100 0000 110X XXXX XXXX XXXX XXXX XXXX
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* 0x40C00000
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* 0x40BFFFFF ROM 0100 0000 101X XXXX XXXX XXXX XXXX XXXX
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* 0x40A00000
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* 0x409FFFFF ROM alias? 0100 0000 100X XXXX XXXX XXXX XXXX XXXX
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* 0x40800000
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* 0x407FFFFF ROM alias? 0100 0000 011X XXXX XXXX XXXX XXXX XXXX
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* 0x40600000
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* 0x405FFFFF ROM alias? 0100 0000 010X XXXX XXXX XXXX XXXX XXXX
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* 0x40400000
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* 0x403FFFFF ROM alias? 0100 0000 001X XXXX XXXX XXXX XXXX XXXX
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* 0x40200000
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* 0x401FFFFF ROM alias? 0100 0000 000X XXXX XXXX XXXX XXXX XXXX
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* 0x40000000
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* 0x3FFFFFFF RAM alias? 0011 11XX XXXX XXXX XXXX XXXX XXXX XXXX
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* 0x3C000000
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* 0x3BFFFFFF RAM alias? 0011 10XX XXXX XXXX XXXX XXXX XXXX XXXX
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* 0x38000000
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* 0x37FFFFFF RAM alias? 0011 01XX XXXX XXXX XXXX XXXX XXXX XXXX
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* 0x34000000
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* 0x33FFFFFF RAM alias? 0011 00XX XXXX XXXX XXXX XXXX XXXX XXXX
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* 0x30000000
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* 0x2FFFFFFF RAM alias? 0010 11XX XXXX XXXX XXXX XXXX XXXX XXXX
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* 0x2C000000
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* 0x2BFFFFFF RAM alias? 0010 10XX XXXX XXXX XXXX XXXX XXXX XXXX
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* 0x28000000
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* 0x27FFFFFF RAM alias? 0010 01XX XXXX XXXX XXXX XXXX XXXX XXXX
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* 0x24000000
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* 0x23FFFFFF RAM alias? 0010 00XX XXXX XXXX XXXX XXXX XXXX XXXX
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* 0x20000000
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* 0x1FFFFFFF RAM alias? 0001 11XX XXXX XXXX XXXX XXXX XXXX XXXX
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* 0x1C000000
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* 0x1BFFFFFF RAM alias? 0001 10XX XXXX XXXX XXXX XXXX XXXX XXXX
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* 0x18000000
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* 0x17FFFFFF RAM alias? 0001 01XX XXXX XXXX XXXX XXXX XXXX XXXX
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* 0x14000000
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* 0x13FFFFFF RAM alias? 0001 00XX XXXX XXXX XXXX XXXX XXXX XXXX
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* 0x10000000
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* 0x0FFFFFFF RAM alias? 0000 11XX XXXX XXXX XXXX XXXX XXXX XXXX
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* 0x0C000000
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* 0x0BFFFFFF RAM alias? 0000 10XX XXXX XXXX XXXX XXXX XXXX XXXX
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* 0x08000000
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* 0x07FFFFFF RAM alias? 0000 01XX XXXX XXXX XXXX XXXX XXXX XXXX
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* 0x04000000
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* 0x03FFFFFF RAM (26 bits) 0000 00XX XXXX XXXX XXXX XXXX XXXX XXXX
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* 0x00000000
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*/
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