1826 lines
43 KiB
Plaintext
1826 lines
43 KiB
Plaintext
EESchema Schematic File Version 4
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EELAYER 30 0
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EELAYER END
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$Descr A4 11693 8268
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encoding utf-8
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Sheet 7 7
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Title ""
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Date ""
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Rev ""
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Comp ""
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Comment1 ""
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Comment2 ""
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Comment3 ""
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F 3 "~" H -2650 5900 50 0001 C CNN
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F 0 "C45" H -600 5950 50 0000 L CNN
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|
Entry Wire Line
|
|
2600 3500 2700 3600
|
|
Text HLabel 2750 2900 2 50 Input ~ 0
|
|
CPU_A[31..0]
|
|
Wire Bus Line
|
|
2750 2900 2700 2900
|
|
Wire Wire Line
|
|
2300 6100 2600 6100
|
|
Wire Wire Line
|
|
2300 6000 2600 6000
|
|
Wire Wire Line
|
|
2300 5500 2600 5500
|
|
Wire Wire Line
|
|
2300 5600 2600 5600
|
|
Wire Wire Line
|
|
2300 5700 2600 5700
|
|
Wire Wire Line
|
|
2300 5800 2600 5800
|
|
Wire Wire Line
|
|
2300 5900 2600 5900
|
|
Wire Wire Line
|
|
2300 7200 2600 7200
|
|
Wire Wire Line
|
|
2300 7300 2600 7300
|
|
Wire Wire Line
|
|
2300 6700 2600 6700
|
|
Wire Wire Line
|
|
2300 6900 2600 6900
|
|
Wire Wire Line
|
|
2300 7000 2600 7000
|
|
Wire Wire Line
|
|
2300 7100 2600 7100
|
|
Wire Wire Line
|
|
2300 4800 2600 4800
|
|
Wire Wire Line
|
|
2300 4100 2600 4100
|
|
Wire Wire Line
|
|
2300 4200 2600 4200
|
|
Wire Wire Line
|
|
2300 4300 2600 4300
|
|
Wire Wire Line
|
|
2300 4400 2600 4400
|
|
Wire Wire Line
|
|
2300 4500 2600 4500
|
|
Wire Wire Line
|
|
2300 4600 2600 4600
|
|
Wire Wire Line
|
|
2300 4700 2600 4700
|
|
Entry Wire Line
|
|
2600 4800 2700 4900
|
|
Entry Wire Line
|
|
2600 4100 2700 4200
|
|
Entry Wire Line
|
|
2600 4200 2700 4300
|
|
Entry Wire Line
|
|
2600 4300 2700 4400
|
|
Entry Wire Line
|
|
2600 4400 2700 4500
|
|
Entry Wire Line
|
|
2600 4500 2700 4600
|
|
Entry Wire Line
|
|
2600 4600 2700 4700
|
|
Entry Wire Line
|
|
2600 4700 2700 4800
|
|
Entry Wire Line
|
|
2600 6100 2700 6200
|
|
Entry Wire Line
|
|
2600 6000 2700 6100
|
|
Entry Wire Line
|
|
2600 5400 2700 5500
|
|
Entry Wire Line
|
|
2600 5500 2700 5600
|
|
Entry Wire Line
|
|
2600 5600 2700 5700
|
|
Entry Wire Line
|
|
2600 5700 2700 5800
|
|
Entry Wire Line
|
|
2600 5800 2700 5900
|
|
Entry Wire Line
|
|
2600 5900 2700 6000
|
|
Entry Wire Line
|
|
2600 7200 2700 7300
|
|
Entry Wire Line
|
|
2600 7300 2700 7400
|
|
Entry Wire Line
|
|
2600 7400 2700 7500
|
|
Entry Wire Line
|
|
2600 6700 2700 6800
|
|
Entry Wire Line
|
|
2600 6800 2700 6900
|
|
Entry Wire Line
|
|
2600 6900 2700 7000
|
|
Entry Wire Line
|
|
2600 7000 2700 7100
|
|
Entry Wire Line
|
|
2600 7100 2700 7200
|
|
Wire Wire Line
|
|
2300 5400 2600 5400
|
|
Wire Wire Line
|
|
2300 7400 2600 7400
|
|
Wire Wire Line
|
|
2300 6800 2600 6800
|
|
Entry Wire Line
|
|
3550 6900 3450 6800
|
|
Entry Wire Line
|
|
3550 7100 3450 7000
|
|
Entry Wire Line
|
|
3550 7000 3450 6900
|
|
Text HLabel 3400 6800 0 50 3State ~ 0
|
|
FSB_FC[2..0]
|
|
Wire Bus Line
|
|
3400 6800 3450 6800
|
|
Wire Wire Line
|
|
3550 6900 3950 6900
|
|
Wire Wire Line
|
|
3950 7000 3550 7000
|
|
Wire Wire Line
|
|
3550 7100 3950 7100
|
|
Wire Wire Line
|
|
5150 6900 4750 6900
|
|
Wire Wire Line
|
|
4750 7000 5150 7000
|
|
Wire Wire Line
|
|
5150 7100 4750 7100
|
|
Wire Bus Line
|
|
5300 6800 5250 6800
|
|
Text HLabel 5300 6800 2 50 Input ~ 0
|
|
CPU_FC[2..0]
|
|
Entry Wire Line
|
|
5150 7000 5250 6900
|
|
Entry Wire Line
|
|
5150 7100 5250 7000
|
|
Entry Wire Line
|
|
5150 6900 5250 6800
|
|
Entry Wire Line
|
|
3550 5900 3450 5800
|
|
Entry Wire Line
|
|
3550 6000 3450 5900
|
|
Text HLabel 3400 5800 0 50 Output ~ 0
|
|
FSB_SIZ[1..0]
|
|
Wire Bus Line
|
|
3400 5800 3450 5800
|
|
Wire Wire Line
|
|
3550 5900 3950 5900
|
|
Wire Wire Line
|
|
3550 6000 3950 6000
|
|
Wire Bus Line
|
|
3450 5800 3450 5900
|
|
Text HLabel 3950 5500 0 50 Output ~ 0
|
|
FSB_~CBREQ~
|
|
Wire Wire Line
|
|
5150 6000 4750 6000
|
|
Wire Wire Line
|
|
4750 5900 5150 5900
|
|
Entry Wire Line
|
|
5150 6000 5250 5900
|
|
Entry Wire Line
|
|
5150 5900 5250 5800
|
|
Text Label 4750 5900 0 50 ~ 0
|
|
CPU_SIZ0
|
|
Text Label 4750 6000 0 50 ~ 0
|
|
CPU_SIZ1
|
|
Text HLabel 4750 4100 2 50 Input ~ 0
|
|
DSACK~OE~
|
|
Text HLabel 3950 4200 0 50 3State ~ 0
|
|
CPU_~DSACK~1
|
|
Text HLabel 3950 4300 0 50 3State ~ 0
|
|
CPU_~DSACK~0
|
|
Text HLabel 4750 4200 2 50 Input ~ 0
|
|
FSB_~DSACK~1
|
|
Text HLabel 4750 4300 2 50 Input ~ 0
|
|
FSB_~DSACK~0
|
|
Text HLabel 4750 5700 2 50 Input ~ 0
|
|
CPU_~ECS~
|
|
Text HLabel 3950 5700 0 50 Output ~ 0
|
|
FSB_~ECS~
|
|
$Comp
|
|
L GW_Logic:74573 U?
|
|
U 1 1 6372B95C
|
|
P 4350 4550
|
|
AR Path="/60941922/6372B95C" Ref="U?" Part="1"
|
|
AR Path="/629B7489/6372B95C" Ref="U?" Part="1"
|
|
AR Path="/629B918A/6372B95C" Ref="U22" Part="1"
|
|
AR Path="/62BBE81B/6372B95C" Ref="U?" Part="1"
|
|
F 0 "U22" H 4350 5150 50 0000 C CNN
|
|
F 1 "74AHCT573PW" V 4350 4550 50 0000 C CNN
|
|
F 2 "stdpads:TSSOP-20_4.4x6.5mm_P0.65mm" H 4350 3900 50 0001 C TNN
|
|
F 3 "" H 4350 4650 60 0001 C CNN
|
|
1 4350 4550
|
|
-1 0 0 -1
|
|
$EndComp
|
|
Text HLabel 4750 5800 2 50 Input ~ 0
|
|
CPU_~CIOUT~
|
|
$Comp
|
|
L power:GND #PWR?
|
|
U 1 1 62A2CF51
|
|
P 3950 7500
|
|
AR Path="/62A2CF51" Ref="#PWR?" Part="1"
|
|
AR Path="/5F723173/62A2CF51" Ref="#PWR?" Part="1"
|
|
AR Path="/60941922/62A2CF51" Ref="#PWR?" Part="1"
|
|
AR Path="/629B7489/62A2CF51" Ref="#PWR?" Part="1"
|
|
AR Path="/629B918A/62A2CF51" Ref="#PWR0182" Part="1"
|
|
F 0 "#PWR0182" H 3950 7250 50 0001 C CNN
|
|
F 1 "GND" H 3950 7350 50 0000 C CNN
|
|
F 2 "" H 3950 7500 50 0001 C CNN
|
|
F 3 "" H 3950 7500 50 0001 C CNN
|
|
1 3950 7500
|
|
-1 0 0 -1
|
|
$EndComp
|
|
NoConn ~ 3950 7400
|
|
$Comp
|
|
L power:GND #PWR?
|
|
U 1 1 637FDC9B
|
|
P 4850 7200
|
|
AR Path="/637FDC9B" Ref="#PWR?" Part="1"
|
|
AR Path="/5F723173/637FDC9B" Ref="#PWR?" Part="1"
|
|
AR Path="/60941922/637FDC9B" Ref="#PWR?" Part="1"
|
|
AR Path="/629B7489/637FDC9B" Ref="#PWR?" Part="1"
|
|
AR Path="/629B918A/637FDC9B" Ref="#PWR0183" Part="1"
|
|
F 0 "#PWR0183" H 4850 6950 50 0001 C CNN
|
|
F 1 "GND" H 4850 7050 50 0000 C CNN
|
|
F 2 "" H 4850 7200 50 0001 C CNN
|
|
F 3 "" H 4850 7200 50 0001 C CNN
|
|
1 4850 7200
|
|
-1 0 0 -1
|
|
$EndComp
|
|
Wire Wire Line
|
|
4850 7200 4750 7200
|
|
Wire Bus Line
|
|
5250 5800 5250 5900
|
|
Wire Bus Line
|
|
5300 5800 5250 5800
|
|
Text HLabel 5300 5800 2 50 Input ~ 0
|
|
CPU_SIZ[1..0]
|
|
Wire Wire Line
|
|
4750 7200 4750 7300
|
|
Connection ~ 4750 7200
|
|
Connection ~ 4750 7300
|
|
Wire Wire Line
|
|
4750 7300 4750 7400
|
|
NoConn ~ 3950 7200
|
|
NoConn ~ 3950 7300
|
|
$Comp
|
|
L power:GND #PWR?
|
|
U 1 1 639465EC
|
|
P 4750 6200
|
|
AR Path="/639465EC" Ref="#PWR?" Part="1"
|
|
AR Path="/5F723173/639465EC" Ref="#PWR?" Part="1"
|
|
AR Path="/60941922/639465EC" Ref="#PWR?" Part="1"
|
|
AR Path="/629B7489/639465EC" Ref="#PWR?" Part="1"
|
|
AR Path="/629B918A/639465EC" Ref="#PWR0184" Part="1"
|
|
F 0 "#PWR0184" H 4750 5950 50 0001 C CNN
|
|
F 1 "GND" H 4750 6050 50 0000 C CNN
|
|
F 2 "" H 4750 6200 50 0001 C CNN
|
|
F 3 "" H 4750 6200 50 0001 C CNN
|
|
1 4750 6200
|
|
-1 0 0 -1
|
|
$EndComp
|
|
$Comp
|
|
L power:GND #PWR?
|
|
U 1 1 62A6DBAA
|
|
P 4850 5000
|
|
AR Path="/62A6DBAA" Ref="#PWR?" Part="1"
|
|
AR Path="/5F723173/62A6DBAA" Ref="#PWR?" Part="1"
|
|
AR Path="/60941922/62A6DBAA" Ref="#PWR?" Part="1"
|
|
AR Path="/629B7489/62A6DBAA" Ref="#PWR?" Part="1"
|
|
AR Path="/629B918A/62A6DBAA" Ref="#PWR0185" Part="1"
|
|
F 0 "#PWR0185" H 4850 4750 50 0001 C CNN
|
|
F 1 "GND" H 4850 4850 50 0000 C CNN
|
|
F 2 "" H 4850 5000 50 0001 C CNN
|
|
F 3 "" H 4850 5000 50 0001 C CNN
|
|
1 4850 5000
|
|
1 0 0 -1
|
|
$EndComp
|
|
Wire Wire Line
|
|
4750 5300 4750 5000
|
|
Wire Wire Line
|
|
4750 5000 4850 5000
|
|
Connection ~ 4750 5000
|
|
$Comp
|
|
L power:+3V3 #PWR?
|
|
U 1 1 639D3B7B
|
|
P 3950 4100
|
|
AR Path="/639D3B7B" Ref="#PWR?" Part="1"
|
|
AR Path="/5F723173/639D3B7B" Ref="#PWR?" Part="1"
|
|
AR Path="/60941922/639D3B7B" Ref="#PWR?" Part="1"
|
|
AR Path="/629B7489/639D3B7B" Ref="#PWR?" Part="1"
|
|
AR Path="/629B918A/639D3B7B" Ref="#PWR0186" Part="1"
|
|
F 0 "#PWR0186" H 3950 3950 50 0001 C CNN
|
|
F 1 "+3V3" H 3950 4250 50 0000 C CNN
|
|
F 2 "" H 3950 4100 50 0001 C CNN
|
|
F 3 "" H 3950 4100 50 0001 C CNN
|
|
1 3950 4100
|
|
1 0 0 -1
|
|
$EndComp
|
|
$Comp
|
|
L power:+3V3 #PWR?
|
|
U 1 1 639D4094
|
|
P 3750 5000
|
|
AR Path="/639D4094" Ref="#PWR?" Part="1"
|
|
AR Path="/5F723173/639D4094" Ref="#PWR?" Part="1"
|
|
AR Path="/60941922/639D4094" Ref="#PWR?" Part="1"
|
|
AR Path="/629B7489/639D4094" Ref="#PWR?" Part="1"
|
|
AR Path="/629B918A/639D4094" Ref="#PWR0187" Part="1"
|
|
F 0 "#PWR0187" H 3750 4850 50 0001 C CNN
|
|
F 1 "+3V3" H 3750 5150 50 0000 C CNN
|
|
F 2 "" H 3750 5000 50 0001 C CNN
|
|
F 3 "" H 3750 5000 50 0001 C CNN
|
|
1 3750 5000
|
|
1 0 0 -1
|
|
$EndComp
|
|
Wire Wire Line
|
|
3750 5000 3950 5000
|
|
Wire Wire Line
|
|
4750 6100 4750 6200
|
|
Connection ~ 4750 6200
|
|
NoConn ~ 3950 6100
|
|
Text HLabel 8450 1700 0 50 BiDi ~ 0
|
|
FSB_D[31..0]
|
|
Text Label 9700 2100 0 50 ~ 0
|
|
CPU_D1
|
|
Text Label 8900 1700 2 50 ~ 0
|
|
FSB_D5
|
|
Entry Wire Line
|
|
10000 5800 10100 5900
|
|
Entry Wire Line
|
|
10000 5700 10100 5800
|
|
Entry Wire Line
|
|
10000 5600 10100 5700
|
|
Entry Wire Line
|
|
10000 5500 10100 5600
|
|
Entry Wire Line
|
|
10000 5400 10100 5500
|
|
Entry Wire Line
|
|
10000 5300 10100 5400
|
|
Entry Wire Line
|
|
10000 5200 10100 5300
|
|
Entry Wire Line
|
|
10000 5100 10100 5200
|
|
Entry Wire Line
|
|
10000 4600 10100 4700
|
|
Entry Wire Line
|
|
10000 4500 10100 4600
|
|
Entry Wire Line
|
|
10000 4400 10100 4500
|
|
Entry Wire Line
|
|
10000 4300 10100 4400
|
|
Entry Wire Line
|
|
10000 4200 10100 4300
|
|
Entry Wire Line
|
|
10000 4100 10100 4200
|
|
Entry Wire Line
|
|
10000 4000 10100 4100
|
|
Entry Wire Line
|
|
10000 3900 10100 4000
|
|
Entry Wire Line
|
|
10000 3400 10100 3500
|
|
Entry Wire Line
|
|
10000 3300 10100 3400
|
|
Entry Wire Line
|
|
10000 3200 10100 3300
|
|
Entry Wire Line
|
|
10000 3100 10100 3200
|
|
Entry Wire Line
|
|
10000 3000 10100 3100
|
|
Entry Wire Line
|
|
10000 2900 10100 3000
|
|
Entry Wire Line
|
|
10000 2800 10100 2900
|
|
Entry Wire Line
|
|
10000 2700 10100 2800
|
|
Wire Wire Line
|
|
9700 3400 10000 3400
|
|
Wire Wire Line
|
|
9700 3300 10000 3300
|
|
Wire Wire Line
|
|
9700 3200 10000 3200
|
|
Wire Wire Line
|
|
9700 3100 10000 3100
|
|
Wire Wire Line
|
|
9700 3000 10000 3000
|
|
Wire Wire Line
|
|
9700 2900 10000 2900
|
|
Wire Wire Line
|
|
9700 2700 10000 2700
|
|
Wire Wire Line
|
|
9700 2800 10000 2800
|
|
Wire Wire Line
|
|
9700 5800 10000 5800
|
|
Wire Wire Line
|
|
9700 5700 10000 5700
|
|
Wire Wire Line
|
|
9700 5600 10000 5600
|
|
Wire Wire Line
|
|
9700 5500 10000 5500
|
|
Wire Wire Line
|
|
9700 5400 10000 5400
|
|
Wire Wire Line
|
|
9700 5300 10000 5300
|
|
Wire Wire Line
|
|
9700 5200 10000 5200
|
|
Wire Wire Line
|
|
9700 5100 10000 5100
|
|
Wire Wire Line
|
|
9700 4500 10000 4500
|
|
Wire Wire Line
|
|
9700 4600 10000 4600
|
|
Wire Wire Line
|
|
9700 4400 10000 4400
|
|
Wire Wire Line
|
|
9700 4300 10000 4300
|
|
Wire Wire Line
|
|
9700 4200 10000 4200
|
|
Wire Wire Line
|
|
9700 4100 10000 4100
|
|
Wire Wire Line
|
|
9700 4000 10000 4000
|
|
Wire Wire Line
|
|
9700 3900 10000 3900
|
|
Wire Bus Line
|
|
10150 1600 10100 1600
|
|
Text HLabel 10150 1600 2 50 BiDi ~ 0
|
|
CPU_D[31..0]
|
|
Entry Wire Line
|
|
10000 2200 10100 2300
|
|
Entry Wire Line
|
|
10000 2100 10100 2200
|
|
Entry Wire Line
|
|
10000 2000 10100 2100
|
|
Entry Wire Line
|
|
10000 1900 10100 2000
|
|
Entry Wire Line
|
|
10000 1800 10100 1900
|
|
Entry Wire Line
|
|
10000 1700 10100 1800
|
|
Entry Wire Line
|
|
10000 1600 10100 1700
|
|
Entry Wire Line
|
|
10000 1500 10100 1600
|
|
Wire Wire Line
|
|
9700 2200 10000 2200
|
|
Wire Wire Line
|
|
9700 2100 10000 2100
|
|
Wire Wire Line
|
|
9700 1900 10000 1900
|
|
Wire Wire Line
|
|
9700 1700 10000 1700
|
|
Wire Wire Line
|
|
9700 1500 10000 1500
|
|
Wire Wire Line
|
|
9700 1600 10000 1600
|
|
Wire Wire Line
|
|
9700 1800 10000 1800
|
|
Wire Wire Line
|
|
9700 2000 10000 2000
|
|
Text Label 9700 2000 0 50 ~ 0
|
|
CPU_D7
|
|
Text Label 9700 1800 0 50 ~ 0
|
|
CPU_D6
|
|
Text Label 9700 1600 0 50 ~ 0
|
|
CPU_D5
|
|
Text Label 9700 1500 0 50 ~ 0
|
|
CPU_D4
|
|
Text Label 9700 1700 0 50 ~ 0
|
|
CPU_D3
|
|
Text Label 9700 1900 0 50 ~ 0
|
|
CPU_D2
|
|
Text Label 9700 2200 0 50 ~ 0
|
|
CPU_D0
|
|
Text Label 9700 5800 0 50 ~ 0
|
|
CPU_D31
|
|
Text Label 9700 5700 0 50 ~ 0
|
|
CPU_D30
|
|
Text Label 9700 5600 0 50 ~ 0
|
|
CPU_D29
|
|
Text Label 9700 5500 0 50 ~ 0
|
|
CPU_D28
|
|
Text Label 9700 5400 0 50 ~ 0
|
|
CPU_D27
|
|
Text Label 9700 5300 0 50 ~ 0
|
|
CPU_D26
|
|
Text Label 9700 5200 0 50 ~ 0
|
|
CPU_D25
|
|
Text Label 9700 5100 0 50 ~ 0
|
|
CPU_D24
|
|
Text Label 9700 4500 0 50 ~ 0
|
|
CPU_D23
|
|
Text Label 9700 4600 0 50 ~ 0
|
|
CPU_D22
|
|
Text Label 9700 4400 0 50 ~ 0
|
|
CPU_D21
|
|
Text Label 9700 4300 0 50 ~ 0
|
|
CPU_D20
|
|
Text Label 9700 4200 0 50 ~ 0
|
|
CPU_D19
|
|
Text Label 9700 4100 0 50 ~ 0
|
|
CPU_D18
|
|
Text Label 9700 4000 0 50 ~ 0
|
|
CPU_D17
|
|
Text Label 9700 3900 0 50 ~ 0
|
|
CPU_D16
|
|
Text Label 9700 3400 0 50 ~ 0
|
|
CPU_D15
|
|
Text Label 9700 3300 0 50 ~ 0
|
|
CPU_D14
|
|
Text Label 9700 3200 0 50 ~ 0
|
|
CPU_D13
|
|
Text Label 9700 3100 0 50 ~ 0
|
|
CPU_D12
|
|
Text Label 9700 3000 0 50 ~ 0
|
|
CPU_D11
|
|
Text Label 9700 2900 0 50 ~ 0
|
|
CPU_D10
|
|
Text Label 9700 2700 0 50 ~ 0
|
|
CPU_D9
|
|
Text Label 9700 2800 0 50 ~ 0
|
|
CPU_D8
|
|
Text HLabel 9700 1400 2 50 Input ~ 0
|
|
DDIR
|
|
Text HLabel 9700 2600 2 50 Input ~ 0
|
|
DDIR
|
|
Text HLabel 9700 3800 2 50 Input ~ 0
|
|
DDIR
|
|
Text HLabel 9700 5000 2 50 Input ~ 0
|
|
DDIR
|
|
Text HLabel 8900 5100 0 50 Input ~ 0
|
|
D~OE~
|
|
Text HLabel 8900 3900 0 50 Input ~ 0
|
|
D~OE~
|
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